ia64/linux-2.6.18-xen.hg

view drivers/net/3c505.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*****************************************************************
2 *
3 * defines for 3Com Etherlink Plus adapter
4 *
5 *****************************************************************/
7 #define ELP_DMA 6
8 #define ELP_RX_PCBS 4
9 #define ELP_MAX_CARDS 4
11 /*
12 * I/O register offsets
13 */
14 #define PORT_COMMAND 0x00 /* read/write, 8-bit */
15 #define PORT_STATUS 0x02 /* read only, 8-bit */
16 #define PORT_AUXDMA 0x02 /* write only, 8-bit */
17 #define PORT_DATA 0x04 /* read/write, 16-bit */
18 #define PORT_CONTROL 0x06 /* read/write, 8-bit */
20 #define ELP_IO_EXTENT 0x10 /* size of used IO registers */
22 /*
23 * host control registers bits
24 */
25 #define ATTN 0x80 /* attention */
26 #define FLSH 0x40 /* flush data register */
27 #define DMAE 0x20 /* DMA enable */
28 #define DIR 0x10 /* direction */
29 #define TCEN 0x08 /* terminal count interrupt enable */
30 #define CMDE 0x04 /* command register interrupt enable */
31 #define HSF2 0x02 /* host status flag 2 */
32 #define HSF1 0x01 /* host status flag 1 */
34 /*
35 * combinations of HSF flags used for PCB transmission
36 */
37 #define HSF_PCB_ACK HSF1
38 #define HSF_PCB_NAK HSF2
39 #define HSF_PCB_END (HSF2|HSF1)
40 #define HSF_PCB_MASK (HSF2|HSF1)
42 /*
43 * host status register bits
44 */
45 #define HRDY 0x80 /* data register ready */
46 #define HCRE 0x40 /* command register empty */
47 #define ACRF 0x20 /* adapter command register full */
48 /* #define DIR 0x10 direction - same as in control register */
49 #define DONE 0x08 /* DMA done */
50 #define ASF3 0x04 /* adapter status flag 3 */
51 #define ASF2 0x02 /* adapter status flag 2 */
52 #define ASF1 0x01 /* adapter status flag 1 */
54 /*
55 * combinations of ASF flags used for PCB reception
56 */
57 #define ASF_PCB_ACK ASF1
58 #define ASF_PCB_NAK ASF2
59 #define ASF_PCB_END (ASF2|ASF1)
60 #define ASF_PCB_MASK (ASF2|ASF1)
62 /*
63 * host aux DMA register bits
64 */
65 #define DMA_BRST 0x01 /* DMA burst */
67 /*
68 * maximum amount of data allowed in a PCB
69 */
70 #define MAX_PCB_DATA 62
72 /*****************************************************************
73 *
74 * timeout value
75 * this is a rough value used for loops to stop them from
76 * locking up the whole machine in the case of failure or
77 * error conditions
78 *
79 *****************************************************************/
81 #define TIMEOUT 300
83 /*****************************************************************
84 *
85 * PCB commands
86 *
87 *****************************************************************/
89 enum {
90 /*
91 * host PCB commands
92 */
93 CMD_CONFIGURE_ADAPTER_MEMORY = 0x01,
94 CMD_CONFIGURE_82586 = 0x02,
95 CMD_STATION_ADDRESS = 0x03,
96 CMD_DMA_DOWNLOAD = 0x04,
97 CMD_DMA_UPLOAD = 0x05,
98 CMD_PIO_DOWNLOAD = 0x06,
99 CMD_PIO_UPLOAD = 0x07,
100 CMD_RECEIVE_PACKET = 0x08,
101 CMD_TRANSMIT_PACKET = 0x09,
102 CMD_NETWORK_STATISTICS = 0x0a,
103 CMD_LOAD_MULTICAST_LIST = 0x0b,
104 CMD_CLEAR_PROGRAM = 0x0c,
105 CMD_DOWNLOAD_PROGRAM = 0x0d,
106 CMD_EXECUTE_PROGRAM = 0x0e,
107 CMD_SELF_TEST = 0x0f,
108 CMD_SET_STATION_ADDRESS = 0x10,
109 CMD_ADAPTER_INFO = 0x11,
110 NUM_TRANSMIT_CMDS,
112 /*
113 * adapter PCB commands
114 */
115 CMD_CONFIGURE_ADAPTER_RESPONSE = 0x31,
116 CMD_CONFIGURE_82586_RESPONSE = 0x32,
117 CMD_ADDRESS_RESPONSE = 0x33,
118 CMD_DOWNLOAD_DATA_REQUEST = 0x34,
119 CMD_UPLOAD_DATA_REQUEST = 0x35,
120 CMD_RECEIVE_PACKET_COMPLETE = 0x38,
121 CMD_TRANSMIT_PACKET_COMPLETE = 0x39,
122 CMD_NETWORK_STATISTICS_RESPONSE = 0x3a,
123 CMD_LOAD_MULTICAST_RESPONSE = 0x3b,
124 CMD_CLEAR_PROGRAM_RESPONSE = 0x3c,
125 CMD_DOWNLOAD_PROGRAM_RESPONSE = 0x3d,
126 CMD_EXECUTE_RESPONSE = 0x3e,
127 CMD_SELF_TEST_RESPONSE = 0x3f,
128 CMD_SET_ADDRESS_RESPONSE = 0x40,
129 CMD_ADAPTER_INFO_RESPONSE = 0x41
130 };
132 /* Definitions for the PCB data structure */
134 /* Data units */
135 typedef unsigned char byte;
136 typedef unsigned short int word;
137 typedef unsigned long int dword;
139 /* Data structures */
140 struct Memconf {
141 word cmd_q,
142 rcv_q,
143 mcast,
144 frame,
145 rcv_b,
146 progs;
147 };
149 struct Rcv_pkt {
150 word buf_ofs,
151 buf_seg,
152 buf_len,
153 timeout;
154 };
156 struct Xmit_pkt {
157 word buf_ofs,
158 buf_seg,
159 pkt_len;
160 };
162 struct Rcv_resp {
163 word buf_ofs,
164 buf_seg,
165 buf_len,
166 pkt_len,
167 timeout,
168 status;
169 dword timetag;
170 };
172 struct Xmit_resp {
173 word buf_ofs,
174 buf_seg,
175 c_stat,
176 status;
177 };
180 struct Netstat {
181 dword tot_recv,
182 tot_xmit;
183 word err_CRC,
184 err_align,
185 err_res,
186 err_ovrrun;
187 };
190 struct Selftest {
191 word error;
192 union {
193 word ROM_cksum;
194 struct {
195 word ofs, seg;
196 } RAM;
197 word i82586;
198 } failure;
199 };
201 struct Info {
202 byte minor_vers,
203 major_vers;
204 word ROM_cksum,
205 RAM_sz,
206 free_ofs,
207 free_seg;
208 };
210 struct Memdump {
211 word size,
212 off,
213 seg;
214 };
216 /*
217 Primary Command Block. The most important data structure. All communication
218 between the host and the adapter is done with these. (Except for the actual
219 Ethernet data, which has different packaging.)
220 */
221 typedef struct {
222 byte command;
223 byte length;
224 union {
225 struct Memconf memconf;
226 word configure;
227 struct Rcv_pkt rcv_pkt;
228 struct Xmit_pkt xmit_pkt;
229 byte multicast[10][6];
230 byte eth_addr[6];
231 byte failed;
232 struct Rcv_resp rcv_resp;
233 struct Xmit_resp xmit_resp;
234 struct Netstat netstat;
235 struct Selftest selftest;
236 struct Info info;
237 struct Memdump memdump;
238 byte raw[62];
239 } data;
240 } pcb_struct;
242 /* These defines for 'configure' */
243 #define RECV_STATION 0x00
244 #define RECV_BROAD 0x01
245 #define RECV_MULTI 0x02
246 #define RECV_PROMISC 0x04
247 #define NO_LOOPBACK 0x00
248 #define INT_LOOPBACK 0x08
249 #define EXT_LOOPBACK 0x10
251 /*****************************************************************
252 *
253 * structure to hold context information for adapter
254 *
255 *****************************************************************/
257 #define DMA_BUFFER_SIZE 1600
258 #define BACKLOG_SIZE 4
260 typedef struct {
261 volatile short got[NUM_TRANSMIT_CMDS]; /* flags for
262 command completion */
263 pcb_struct tx_pcb; /* PCB for foreground sending */
264 pcb_struct rx_pcb; /* PCB for foreground receiving */
265 pcb_struct itx_pcb; /* PCB for background sending */
266 pcb_struct irx_pcb; /* PCB for background receiving */
267 struct net_device_stats stats;
269 void *dma_buffer;
271 struct {
272 unsigned int length[BACKLOG_SIZE];
273 unsigned int in;
274 unsigned int out;
275 } rx_backlog;
277 struct {
278 unsigned int direction;
279 unsigned int length;
280 struct sk_buff *skb;
281 void *target;
282 unsigned long start_time;
283 } current_dma;
285 /* flags */
286 unsigned long send_pcb_semaphore;
287 unsigned long dmaing;
288 unsigned long busy;
290 unsigned int rx_active; /* number of receive PCBs */
291 volatile unsigned char hcr_val; /* what we think the HCR contains */
292 spinlock_t lock; /* Interrupt v tx lock */
293 } elp_device;