ia64/linux-2.6.18-xen.hg

view drivers/mtd/maps/l440gx.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * $Id: l440gx.c,v 1.18 2005/11/07 11:14:27 gleixner Exp $
3 *
4 * BIOS Flash chip on Intel 440GX board.
5 *
6 * Bugs this currently does not work under linuxBIOS.
7 */
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <asm/io.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/map.h>
17 #define PIIXE_IOBASE_RESOURCE 11
19 #define WINDOW_ADDR 0xfff00000
20 #define WINDOW_SIZE 0x00100000
21 #define BUSWIDTH 1
23 static u32 iobase;
24 #define IOBASE iobase
25 #define TRIBUF_PORT (IOBASE+0x37)
26 #define VPP_PORT (IOBASE+0x28)
28 static struct mtd_info *mymtd;
31 /* Is this really the vpp port? */
32 static void l440gx_set_vpp(struct map_info *map, int vpp)
33 {
34 unsigned long l;
36 l = inl(VPP_PORT);
37 if (vpp) {
38 l |= 1;
39 } else {
40 l &= ~1;
41 }
42 outl(l, VPP_PORT);
43 }
45 static struct map_info l440gx_map = {
46 .name = "L440GX BIOS",
47 .size = WINDOW_SIZE,
48 .bankwidth = BUSWIDTH,
49 .phys = WINDOW_ADDR,
50 #if 0
51 /* FIXME verify that this is the
52 * appripriate code for vpp enable/disable
53 */
54 .set_vpp = l440gx_set_vpp
55 #endif
56 };
58 static int __init init_l440gx(void)
59 {
60 struct pci_dev *dev, *pm_dev;
61 struct resource *pm_iobase;
62 __u16 word;
64 dev = pci_find_device(PCI_VENDOR_ID_INTEL,
65 PCI_DEVICE_ID_INTEL_82371AB_0, NULL);
67 pm_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
68 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
70 if (!dev || !pm_dev) {
71 printk(KERN_NOTICE "L440GX flash mapping: failed to find PIIX4 ISA bridge, cannot continue\n");
72 return -ENODEV;
73 }
75 l440gx_map.virt = ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
77 if (!l440gx_map.virt) {
78 printk(KERN_WARNING "Failed to ioremap L440GX flash region\n");
79 return -ENOMEM;
80 }
81 simple_map_init(&l440gx_map);
82 printk(KERN_NOTICE "window_addr = 0x%08lx\n", (unsigned long)l440gx_map.virt);
84 /* Setup the pm iobase resource
85 * This code should move into some kind of generic bridge
86 * driver but for the moment I'm content with getting the
87 * allocation correct.
88 */
89 pm_iobase = &pm_dev->resource[PIIXE_IOBASE_RESOURCE];
90 if (!(pm_iobase->flags & IORESOURCE_IO)) {
91 pm_iobase->name = "pm iobase";
92 pm_iobase->start = 0;
93 pm_iobase->end = 63;
94 pm_iobase->flags = IORESOURCE_IO;
96 /* Put the current value in the resource */
97 pci_read_config_dword(pm_dev, 0x40, &iobase);
98 iobase &= ~1;
99 pm_iobase->start += iobase & ~1;
100 pm_iobase->end += iobase & ~1;
102 /* Allocate the resource region */
103 if (pci_assign_resource(pm_dev, PIIXE_IOBASE_RESOURCE) != 0) {
104 printk(KERN_WARNING "Could not allocate pm iobase resource\n");
105 iounmap(l440gx_map.virt);
106 return -ENXIO;
107 }
108 }
109 /* Set the iobase */
110 iobase = pm_iobase->start;
111 pci_write_config_dword(pm_dev, 0x40, iobase | 1);
114 /* Set XBCS# */
115 pci_read_config_word(dev, 0x4e, &word);
116 word |= 0x4;
117 pci_write_config_word(dev, 0x4e, word);
119 /* Supply write voltage to the chip */
120 l440gx_set_vpp(&l440gx_map, 1);
122 /* Enable the gate on the WE line */
123 outb(inb(TRIBUF_PORT) & ~1, TRIBUF_PORT);
125 printk(KERN_NOTICE "Enabled WE line to L440GX BIOS flash chip.\n");
127 mymtd = do_map_probe("jedec_probe", &l440gx_map);
128 if (!mymtd) {
129 printk(KERN_NOTICE "JEDEC probe on BIOS chip failed. Using ROM\n");
130 mymtd = do_map_probe("map_rom", &l440gx_map);
131 }
132 if (mymtd) {
133 mymtd->owner = THIS_MODULE;
135 add_mtd_device(mymtd);
136 return 0;
137 }
139 iounmap(l440gx_map.virt);
140 return -ENXIO;
141 }
143 static void __exit cleanup_l440gx(void)
144 {
145 del_mtd_device(mymtd);
146 map_destroy(mymtd);
148 iounmap(l440gx_map.virt);
149 }
151 module_init(init_l440gx);
152 module_exit(cleanup_l440gx);
154 MODULE_LICENSE("GPL");
155 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
156 MODULE_DESCRIPTION("MTD map driver for BIOS chips on Intel L440GX motherboards");