ia64/linux-2.6.18-xen.hg

view drivers/atm/horizon.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
21 */
23 /*
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
26 */
28 /* too many macros - change to inline functions */
30 #ifndef DRIVER_ATM_HORIZON_H
31 #define DRIVER_ATM_HORIZON_H
34 #ifdef CONFIG_ATM_HORIZON_DEBUG
35 #define DEBUG_HORIZON
36 #endif
38 #define DEV_LABEL "hrz"
40 #ifndef PCI_VENDOR_ID_MADGE
41 #define PCI_VENDOR_ID_MADGE 0x10B6
42 #endif
43 #ifndef PCI_DEVICE_ID_MADGE_HORIZON
44 #define PCI_DEVICE_ID_MADGE_HORIZON 0x1000
45 #endif
47 // diagnostic output
49 #define PRINTK(severity,format,args...) \
50 printk(severity DEV_LABEL ": " format "\n" , ## args)
52 #ifdef DEBUG_HORIZON
54 #define DBG_ERR 0x0001
55 #define DBG_WARN 0x0002
56 #define DBG_INFO 0x0004
57 #define DBG_VCC 0x0008
58 #define DBG_QOS 0x0010
59 #define DBG_TX 0x0020
60 #define DBG_RX 0x0040
61 #define DBG_SKB 0x0080
62 #define DBG_IRQ 0x0100
63 #define DBG_FLOW 0x0200
64 #define DBG_BUS 0x0400
65 #define DBG_REGS 0x0800
66 #define DBG_DATA 0x1000
67 #define DBG_MASK 0x1fff
69 /* the ## prevents the annoying double expansion of the macro arguments */
70 /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
71 #define PRINTDB(bits,format,args...) \
72 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
73 #define PRINTDM(bits,format,args...) \
74 ( (debug & (bits)) ? printk (format , ## args) : 1 )
75 #define PRINTDE(bits,format,args...) \
76 ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
77 #define PRINTD(bits,format,args...) \
78 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
80 #else
82 #define PRINTD(bits,format,args...)
83 #define PRINTDB(bits,format,args...)
84 #define PRINTDM(bits,format,args...)
85 #define PRINTDE(bits,format,args...)
87 #endif
89 #define PRINTDD(sec,fmt,args...)
90 #define PRINTDDB(sec,fmt,args...)
91 #define PRINTDDM(sec,fmt,args...)
92 #define PRINTDDE(sec,fmt,args...)
94 // fixed constants
96 #define SPARE_BUFFER_POOL_SIZE MAX_VCS
97 #define HRZ_MAX_VPI 4
98 #define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL
100 /* Horizon specific bits */
101 /* Register offsets */
103 #define HRZ_IO_EXTENT 0x80
105 #define DATA_PORT_OFF 0x00
106 #define TX_CHANNEL_PORT_OFF 0x04
107 #define TX_DESCRIPTOR_PORT_OFF 0x08
108 #define MEMORY_PORT_OFF 0x0C
109 #define MEM_WR_ADDR_REG_OFF 0x14
110 #define MEM_RD_ADDR_REG_OFF 0x18
111 #define CONTROL_0_REG 0x1C
112 #define INT_SOURCE_REG_OFF 0x20
113 #define INT_ENABLE_REG_OFF 0x24
114 #define MASTER_RX_ADDR_REG_OFF 0x28
115 #define MASTER_RX_COUNT_REG_OFF 0x2C
116 #define MASTER_TX_ADDR_REG_OFF 0x30
117 #define MASTER_TX_COUNT_REG_OFF 0x34
118 #define TX_DESCRIPTOR_REG_OFF 0x38
119 #define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40
120 #define TX_CHANNEL_CONFIG_DATA_OFF 0x44
121 #define TX_FREE_BUFFER_COUNT_OFF 0x48
122 #define RX_FREE_BUFFER_COUNT_OFF 0x4C
123 #define TX_CONFIG_OFF 0x50
124 #define TX_STATUS_OFF 0x54
125 #define RX_CONFIG_OFF 0x58
126 #define RX_LINE_CONFIG_OFF 0x5C
127 #define RX_QUEUE_RD_PTR_OFF 0x60
128 #define RX_QUEUE_WR_PTR_OFF 0x64
129 #define MAX_AAL5_CELL_COUNT_OFF 0x68
130 #define RX_CHANNEL_PORT_OFF 0x6C
131 #define TX_CELL_COUNT_OFF 0x70
132 #define RX_CELL_COUNT_OFF 0x74
133 #define HEC_ERROR_COUNT_OFF 0x78
134 #define UNASSIGNED_CELL_COUNT_OFF 0x7C
136 /* Register bit definitions */
138 /* Control 0 register */
140 #define SEEPROM_DO 0x00000001
141 #define SEEPROM_DI 0x00000002
142 #define SEEPROM_SK 0x00000004
143 #define SEEPROM_CS 0x00000008
144 #define DEBUG_BIT_0 0x00000010
145 #define DEBUG_BIT_1 0x00000020
146 #define DEBUG_BIT_2 0x00000040
147 // RESERVED 0x00000080
148 #define DEBUG_BIT_0_OE 0x00000100
149 #define DEBUG_BIT_1_OE 0x00000200
150 #define DEBUG_BIT_2_OE 0x00000400
151 // RESERVED 0x00000800
152 #define DEBUG_BIT_0_STATE 0x00001000
153 #define DEBUG_BIT_1_STATE 0x00002000
154 #define DEBUG_BIT_2_STATE 0x00004000
155 // RESERVED 0x00008000
156 #define GENERAL_BIT_0 0x00010000
157 #define GENERAL_BIT_1 0x00020000
158 #define GENERAL_BIT_2 0x00040000
159 #define GENERAL_BIT_3 0x00080000
160 #define RESET_HORIZON 0x00100000
161 #define RESET_ATM 0x00200000
162 #define RESET_RX 0x00400000
163 #define RESET_TX 0x00800000
164 #define RESET_HOST 0x01000000
165 // RESERVED 0x02000000
166 #define TARGET_RETRY_DISABLE 0x04000000
167 #define ATM_LAYER_SELECT 0x08000000
168 #define ATM_LAYER_STATUS 0x10000000
169 // RESERVED 0xE0000000
171 /* Interrupt source and enable registers */
173 #define RX_DATA_AV 0x00000001
174 #define RX_DISABLED 0x00000002
175 #define TIMING_MARKER 0x00000004
176 #define FORCED 0x00000008
177 #define RX_BUS_MASTER_COMPLETE 0x00000010
178 #define TX_BUS_MASTER_COMPLETE 0x00000020
179 #define ABR_TX_CELL_COUNT_INT 0x00000040
180 #define DEBUG_INT 0x00000080
181 // RESERVED 0xFFFFFF00
183 /* PIO and Bus Mastering */
185 #define MAX_PIO_COUNT 0x000000ff // 255 - make tunable?
186 // 8188 is a hard limit for bus mastering
187 #define MAX_TRANSFER_COUNT 0x00001ffc // 8188
188 #define MASTER_TX_AUTO_APPEND_DESC 0x80000000
190 /* TX channel config command port */
192 #define PCR_TIMER_ACCESS 0x0000
193 #define SCR_TIMER_ACCESS 0x0001
194 #define BUCKET_CAPACITY_ACCESS 0x0002
195 #define BUCKET_FULLNESS_ACCESS 0x0003
196 #define RATE_TYPE_ACCESS 0x0004
197 // UNUSED 0x00F8
198 #define TX_CHANNEL_CONFIG_MULT 0x0100
199 // UNUSED 0xF800
200 #define BUCKET_MAX_SIZE 0x003f
202 /* TX channel config data port */
204 #define CLOCK_SELECT_SHIFT 4
205 #define CLOCK_DISABLE 0x00ff
207 #define IDLE_RATE_TYPE 0x0
208 #define ABR_RATE_TYPE 0x1
209 #define VBR_RATE_TYPE 0x2
210 #define CBR_RATE_TYPE 0x3
212 /* TX config register */
214 #define DRVR_DRVRBAR_ENABLE 0x0001
215 #define TXCLK_MUX_SELECT_RCLK 0x0002
216 #define TRANSMIT_TIMING_MARKER 0x0004
217 #define LOOPBACK_TIMING_MARKER 0x0008
218 #define TX_TEST_MODE_16MHz 0x0000
219 #define TX_TEST_MODE_8MHz 0x0010
220 #define TX_TEST_MODE_5_33MHz 0x0020
221 #define TX_TEST_MODE_4MHz 0x0030
222 #define TX_TEST_MODE_3_2MHz 0x0040
223 #define TX_TEST_MODE_2_66MHz 0x0050
224 #define TX_TEST_MODE_2_29MHz 0x0060
225 #define TX_NORMAL_OPERATION 0x0070
226 #define ABR_ROUND_ROBIN 0x0080
228 /* TX status register */
230 #define IDLE_CHANNELS_MASK 0x00FF
231 #define ABR_CELL_COUNT_REACHED_MULT 0x0100
232 #define ABR_CELL_COUNT_REACHED_MASK 0xFF
234 /* RX config register */
236 #define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008
237 #define RX_ENABLE 0x0010
238 #define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000
239 #define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020
240 #define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040
242 /* RX line config register */
244 #define SIGNAL_LOSS 0x0001
245 #define FREQUENCY_DETECT_ERROR 0x0002
246 #define LOCK_DETECT_ERROR 0x0004
247 #define SELECT_INTERNAL_LOOPBACK 0x0008
248 #define LOCK_DETECT_ENABLE 0x0010
249 #define FREQUENCY_DETECT_ENABLE 0x0020
250 #define USER_FRAQ 0x0040
251 #define GXTALOUT_SELECT_DIV4 0x0080
252 #define GXTALOUT_SELECT_NO_GATING 0x0100
253 #define TIMING_MARKER_RECEIVED 0x0200
255 /* RX channel port */
257 #define RX_CHANNEL_MASK 0x03FF
258 // UNUSED 0x3C00
259 #define FLUSH_CHANNEL 0x4000
260 #define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000
262 /* Receive queue entry */
264 #define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF
265 #define RX_Q_ENTRY_CHANNEL_SHIFT 16
266 #define SIMONS_DODGEY_MARKER 0x08000000
267 #define RX_CONGESTION_EXPERIENCED 0x10000000
268 #define RX_CRC_10_OK 0x20000000
269 #define RX_CRC_32_OK 0x40000000
270 #define RX_COMPLETE_FRAME 0x80000000
272 /* Offsets and constants for use with the buffer memory */
274 /* Buffer pointers and channel types */
276 #define BUFFER_PTR_MASK 0x0000FFFF
277 #define RX_INT_THRESHOLD_MULT 0x00010000
278 #define RX_INT_THRESHOLD_MASK 0x07FF
279 #define INT_EVERY_N_CELLS 0x08000000
280 #define CONGESTION_EXPERIENCED 0x10000000
281 #define FIRST_CELL_OF_AAL5_FRAME 0x20000000
282 #define CHANNEL_TYPE_AAL5 0x00000000
283 #define CHANNEL_TYPE_RAW_CELLS 0x40000000
284 #define CHANNEL_TYPE_AAL3_4 0x80000000
286 /* Buffer status stuff */
288 #define BUFF_STATUS_MASK 0x00030000
289 #define BUFF_STATUS_EMPTY 0x00000000
290 #define BUFF_STATUS_CELL_AV 0x00010000
291 #define BUFF_STATUS_LAST_CELL_AV 0x00020000
293 /* Transmit channel stuff */
295 /* Receive channel stuff */
297 #define RX_CHANNEL_DISABLED 0x00000000
298 #define RX_CHANNEL_IDLE 0x00000001
300 /* General things */
302 #define INITIAL_CRC 0xFFFFFFFF
304 // A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
305 // word addresses and so standard C pointer operations break (as they
306 // assume byte addresses); so we pretend that Horizon words (and word
307 // pointers) are bytes (and byte pointers) for the purposes of having
308 // a memory map that works.
310 typedef u8 HDW;
312 typedef struct cell_buf {
313 HDW payload[12];
314 HDW next;
315 HDW cell_count; // AAL5 rx bufs
316 HDW res;
317 union {
318 HDW partial_crc; // AAL5 rx bufs
319 HDW cell_header; // RAW bufs
320 } u;
321 } cell_buf;
323 typedef struct tx_ch_desc {
324 HDW rd_buf_type;
325 HDW wr_buf_type;
326 HDW partial_crc;
327 HDW cell_header;
328 } tx_ch_desc;
330 typedef struct rx_ch_desc {
331 HDW wr_buf_type;
332 HDW rd_buf_type;
333 } rx_ch_desc;
335 typedef struct rx_q_entry {
336 HDW entry;
337 } rx_q_entry;
339 #define TX_CHANS 8
340 #define RX_CHANS 1024
341 #define RX_QS 1024
342 #define MAX_VCS RX_CHANS
344 /* Horizon buffer memory map */
346 // TX Channel Descriptors 2
347 // TX Initial Buffers 8 // TX_CHANS
348 #define BUFN1_SIZE 118 // (126 - TX_CHANS)
349 // RX/TX Start/End Buffers 4
350 #define BUFN2_SIZE 124
351 // RX Queue Entries 64
352 #define BUFN3_SIZE 192
353 // RX Channel Descriptors 128
354 #define BUFN4_SIZE 1408
355 // TOTAL cell_buff chunks 2048
357 // cell_buf bufs[2048];
358 // HDW dws[32768];
360 typedef struct MEMMAP {
361 tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020
362 cell_buf inittxbufs[TX_CHANS]; // these are really
363 cell_buf bufn1[BUFN1_SIZE]; // part of this pool
364 cell_buf txfreebufstart;
365 cell_buf txfreebufend;
366 cell_buf rxfreebufstart;
367 cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254
368 cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000
369 rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400
370 cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000
371 rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800
372 cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000
373 } MEMMAP;
375 #define memmap ((MEMMAP *)0)
377 /* end horizon specific bits */
379 typedef enum {
380 aal0,
381 aal34,
382 aal5
383 } hrz_aal;
385 typedef enum {
386 tx_busy,
387 rx_busy,
388 ultra
389 } hrz_flags;
391 // a single struct pointed to by atm_vcc->dev_data
393 typedef struct {
394 unsigned int tx_rate;
395 unsigned int rx_rate;
396 u16 channel;
397 u16 tx_xbr_bits;
398 u16 tx_pcr_bits;
399 #if 0
400 u16 tx_scr_bits;
401 u16 tx_bucket_bits;
402 #endif
403 hrz_aal aal;
404 } hrz_vcc;
406 struct hrz_dev {
408 u32 iobase;
409 u32 * membase;
411 struct sk_buff * rx_skb; // skb being RXed
412 unsigned int rx_bytes; // bytes remaining to RX within region
413 void * rx_addr; // addr to send bytes to (for PIO)
414 unsigned int rx_channel; // channel that the skb is going out on
416 struct sk_buff * tx_skb; // skb being TXed
417 unsigned int tx_bytes; // bytes remaining to TX within region
418 void * tx_addr; // addr to send bytes from (for PIO)
419 struct iovec * tx_iovec; // remaining regions
420 unsigned int tx_regions; // number of remaining regions
422 spinlock_t mem_lock;
423 wait_queue_head_t tx_queue;
425 u8 irq;
426 long flags;
427 u8 tx_last;
428 u8 tx_idle;
430 rx_q_entry * rx_q_reset;
431 rx_q_entry * rx_q_entry;
432 rx_q_entry * rx_q_wrap;
434 struct atm_dev * atm_dev;
436 u32 last_vc;
438 int noof_spare_buffers;
439 u16 spare_buffers[SPARE_BUFFER_POOL_SIZE];
441 u16 tx_channel_record[TX_CHANS];
443 // this is what we follow when we get incoming data
444 u32 txer[MAX_VCS/32];
445 struct atm_vcc * rxer[MAX_VCS];
447 // cell rate allocation
448 spinlock_t rate_lock;
449 unsigned int rx_avail;
450 unsigned int tx_avail;
452 // dev stats
453 unsigned long tx_cell_count;
454 unsigned long rx_cell_count;
455 unsigned long hec_error_count;
456 unsigned long unassigned_cell_count;
458 struct pci_dev * pci_dev;
459 struct timer_list housekeeping;
460 };
462 typedef struct hrz_dev hrz_dev;
464 /* macros for use later */
466 #define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
468 #define INTERESTING_INTERRUPTS \
469 (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
471 // 190 cells by default (192 TX buffers - 2 elbow room, see docs)
472 #define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
474 // Have enough RX buffers (unless we allow other buffer splits)
475 #define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
477 /* multi-statement macro protector */
478 #define DW(x) do{ x } while(0)
480 #define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
481 #define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
483 /* Turn the LEDs on and off */
484 // The LEDs bits are upside down in that setting the bit in the debug
485 // register will turn the appropriate LED off.
487 #define YELLOW_LED DEBUG_BIT_0
488 #define GREEN_LED DEBUG_BIT_1
489 #define YELLOW_LED_OE DEBUG_BIT_0_OE
490 #define GREEN_LED_OE DEBUG_BIT_1_OE
492 #define GREEN_LED_OFF(dev) \
493 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
494 #define GREEN_LED_ON(dev) \
495 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
496 #define YELLOW_LED_OFF(dev) \
497 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
498 #define YELLOW_LED_ON(dev) \
499 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
501 typedef enum {
502 round_up,
503 round_down,
504 round_nearest
505 } rounding;
507 #endif /* DRIVER_ATM_HORIZON_H */