ia64/linux-2.6.18-xen.hg

view arch/sparc64/kernel/pci_psycho.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /* $Id: pci_psycho.c,v 1.33 2002/02/01 00:58:33 davem Exp $
2 * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
7 */
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/interrupt.h>
16 #include <asm/pbm.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/starfire.h>
20 #include <asm/prom.h>
21 #include <asm/of_device.h>
23 #include "pci_impl.h"
24 #include "iommu_common.h"
26 /* All PSYCHO registers are 64-bits. The following accessor
27 * routines are how they are accessed. The REG parameter
28 * is a physical address.
29 */
30 #define psycho_read(__reg) \
31 ({ u64 __ret; \
32 __asm__ __volatile__("ldxa [%1] %2, %0" \
33 : "=r" (__ret) \
34 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
35 : "memory"); \
36 __ret; \
37 })
38 #define psycho_write(__reg, __val) \
39 __asm__ __volatile__("stxa %0, [%1] %2" \
40 : /* no outputs */ \
41 : "r" (__val), "r" (__reg), \
42 "i" (ASI_PHYS_BYPASS_EC_E) \
43 : "memory")
45 /* Misc. PSYCHO PCI controller register offsets and definitions. */
46 #define PSYCHO_CONTROL 0x0010UL
47 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
48 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
49 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
50 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
51 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
52 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
53 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
54 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
55 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
56 #define PSYCHO_PCIA_CTRL 0x2000UL
57 #define PSYCHO_PCIB_CTRL 0x4000UL
58 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
59 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
60 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
61 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
62 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
63 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
64 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
65 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
66 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
67 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
68 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
69 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
71 /* U2P Programmer's Manual, page 13-55, configuration space
72 * address format:
73 *
74 * 32 24 23 16 15 11 10 8 7 2 1 0
75 * ---------------------------------------------------------
76 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
77 * ---------------------------------------------------------
78 */
79 #define PSYCHO_CONFIG_BASE(PBM) \
80 ((PBM)->config_space | (1UL << 24))
81 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
82 (((unsigned long)(BUS) << 16) | \
83 ((unsigned long)(DEVFN) << 8) | \
84 ((unsigned long)(REG)))
86 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
87 unsigned char bus,
88 unsigned int devfn,
89 int where)
90 {
91 if (!pbm)
92 return NULL;
93 return (void *)
94 (PSYCHO_CONFIG_BASE(pbm) |
95 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
96 }
98 static int psycho_out_of_range(struct pci_pbm_info *pbm,
99 unsigned char bus,
100 unsigned char devfn)
101 {
102 return ((pbm->parent == 0) ||
103 ((pbm == &pbm->parent->pbm_B) &&
104 (bus == pbm->pci_first_busno) &&
105 PCI_SLOT(devfn) > 8) ||
106 ((pbm == &pbm->parent->pbm_A) &&
107 (bus == pbm->pci_first_busno) &&
108 PCI_SLOT(devfn) > 8));
109 }
111 /* PSYCHO PCI configuration space accessors. */
113 static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
114 int where, int size, u32 *value)
115 {
116 struct pci_pbm_info *pbm = bus_dev->sysdata;
117 unsigned char bus = bus_dev->number;
118 u32 *addr;
119 u16 tmp16;
120 u8 tmp8;
122 switch (size) {
123 case 1:
124 *value = 0xff;
125 break;
126 case 2:
127 *value = 0xffff;
128 break;
129 case 4:
130 *value = 0xffffffff;
131 break;
132 }
134 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
135 if (!addr)
136 return PCIBIOS_SUCCESSFUL;
138 if (psycho_out_of_range(pbm, bus, devfn))
139 return PCIBIOS_SUCCESSFUL;
140 switch (size) {
141 case 1:
142 pci_config_read8((u8 *)addr, &tmp8);
143 *value = (u32) tmp8;
144 break;
146 case 2:
147 if (where & 0x01) {
148 printk("pci_read_config_word: misaligned reg [%x]\n",
149 where);
150 return PCIBIOS_SUCCESSFUL;
151 }
152 pci_config_read16((u16 *)addr, &tmp16);
153 *value = (u32) tmp16;
154 break;
156 case 4:
157 if (where & 0x03) {
158 printk("pci_read_config_dword: misaligned reg [%x]\n",
159 where);
160 return PCIBIOS_SUCCESSFUL;
161 }
162 pci_config_read32(addr, value);
163 break;
164 }
165 return PCIBIOS_SUCCESSFUL;
166 }
168 static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
169 int where, int size, u32 value)
170 {
171 struct pci_pbm_info *pbm = bus_dev->sysdata;
172 unsigned char bus = bus_dev->number;
173 u32 *addr;
175 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
176 if (!addr)
177 return PCIBIOS_SUCCESSFUL;
179 if (psycho_out_of_range(pbm, bus, devfn))
180 return PCIBIOS_SUCCESSFUL;
182 switch (size) {
183 case 1:
184 pci_config_write8((u8 *)addr, value);
185 break;
187 case 2:
188 if (where & 0x01) {
189 printk("pci_write_config_word: misaligned reg [%x]\n",
190 where);
191 return PCIBIOS_SUCCESSFUL;
192 }
193 pci_config_write16((u16 *)addr, value);
194 break;
196 case 4:
197 if (where & 0x03) {
198 printk("pci_write_config_dword: misaligned reg [%x]\n",
199 where);
200 return PCIBIOS_SUCCESSFUL;
201 }
202 pci_config_write32(addr, value);
203 }
204 return PCIBIOS_SUCCESSFUL;
205 }
207 static struct pci_ops psycho_ops = {
208 .read = psycho_read_pci_cfg,
209 .write = psycho_write_pci_cfg,
210 };
212 /* PSYCHO error handling support. */
213 enum psycho_error_type {
214 UE_ERR, CE_ERR, PCI_ERR
215 };
217 /* Helper function of IOMMU error checking, which checks out
218 * the state of the streaming buffers. The IOMMU lock is
219 * held when this is called.
220 *
221 * For the PCI error case we know which PBM (and thus which
222 * streaming buffer) caused the error, but for the uncorrectable
223 * error case we do not. So we always check both streaming caches.
224 */
225 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
226 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
227 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
228 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
229 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
230 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
231 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
232 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
233 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
234 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
235 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
236 #define PSYCHO_STC_DATA_A 0xb000UL
237 #define PSYCHO_STC_DATA_B 0xc000UL
238 #define PSYCHO_STC_ERR_A 0xb400UL
239 #define PSYCHO_STC_ERR_B 0xc400UL
240 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
241 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
242 #define PSYCHO_STC_TAG_A 0xb800UL
243 #define PSYCHO_STC_TAG_B 0xc800UL
244 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
245 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
246 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
247 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
248 #define PSYCHO_STC_LINE_A 0xb900UL
249 #define PSYCHO_STC_LINE_B 0xc900UL
250 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
251 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
252 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
253 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
254 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
255 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
257 static DEFINE_SPINLOCK(stc_buf_lock);
258 static unsigned long stc_error_buf[128];
259 static unsigned long stc_tag_buf[16];
260 static unsigned long stc_line_buf[16];
262 static void __psycho_check_one_stc(struct pci_controller_info *p,
263 struct pci_pbm_info *pbm,
264 int is_pbm_a)
265 {
266 struct pci_strbuf *strbuf = &pbm->stc;
267 unsigned long regbase = p->pbm_A.controller_regs;
268 unsigned long err_base, tag_base, line_base;
269 u64 control;
270 int i;
272 if (is_pbm_a) {
273 err_base = regbase + PSYCHO_STC_ERR_A;
274 tag_base = regbase + PSYCHO_STC_TAG_A;
275 line_base = regbase + PSYCHO_STC_LINE_A;
276 } else {
277 err_base = regbase + PSYCHO_STC_ERR_B;
278 tag_base = regbase + PSYCHO_STC_TAG_B;
279 line_base = regbase + PSYCHO_STC_LINE_B;
280 }
282 spin_lock(&stc_buf_lock);
284 /* This is __REALLY__ dangerous. When we put the
285 * streaming buffer into diagnostic mode to probe
286 * it's tags and error status, we _must_ clear all
287 * of the line tag valid bits before re-enabling
288 * the streaming buffer. If any dirty data lives
289 * in the STC when we do this, we will end up
290 * invalidating it before it has a chance to reach
291 * main memory.
292 */
293 control = psycho_read(strbuf->strbuf_control);
294 psycho_write(strbuf->strbuf_control,
295 (control | PSYCHO_STRBUF_CTRL_DENAB));
296 for (i = 0; i < 128; i++) {
297 unsigned long val;
299 val = psycho_read(err_base + (i * 8UL));
300 psycho_write(err_base + (i * 8UL), 0UL);
301 stc_error_buf[i] = val;
302 }
303 for (i = 0; i < 16; i++) {
304 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
305 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
306 psycho_write(tag_base + (i * 8UL), 0UL);
307 psycho_write(line_base + (i * 8UL), 0UL);
308 }
310 /* OK, state is logged, exit diagnostic mode. */
311 psycho_write(strbuf->strbuf_control, control);
313 for (i = 0; i < 16; i++) {
314 int j, saw_error, first, last;
316 saw_error = 0;
317 first = i * 8;
318 last = first + 8;
319 for (j = first; j < last; j++) {
320 unsigned long errval = stc_error_buf[j];
321 if (errval != 0) {
322 saw_error++;
323 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
324 p->index,
325 (is_pbm_a ? 'A' : 'B'),
326 j,
327 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
328 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
329 }
330 }
331 if (saw_error != 0) {
332 unsigned long tagval = stc_tag_buf[i];
333 unsigned long lineval = stc_line_buf[i];
334 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
335 p->index,
336 (is_pbm_a ? 'A' : 'B'),
337 i,
338 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
339 (tagval & PSYCHO_STCTAG_VPN),
340 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
341 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
342 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
343 "V(%d)FOFN(%d)]\n",
344 p->index,
345 (is_pbm_a ? 'A' : 'B'),
346 i,
347 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
348 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
349 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
350 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
351 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
352 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
353 }
354 }
356 spin_unlock(&stc_buf_lock);
357 }
359 static void __psycho_check_stc_error(struct pci_controller_info *p,
360 unsigned long afsr,
361 unsigned long afar,
362 enum psycho_error_type type)
363 {
364 struct pci_pbm_info *pbm;
366 pbm = &p->pbm_A;
367 if (pbm->stc.strbuf_enabled)
368 __psycho_check_one_stc(p, pbm, 1);
370 pbm = &p->pbm_B;
371 if (pbm->stc.strbuf_enabled)
372 __psycho_check_one_stc(p, pbm, 0);
373 }
375 /* When an Uncorrectable Error or a PCI Error happens, we
376 * interrogate the IOMMU state to see if it is the cause.
377 */
378 #define PSYCHO_IOMMU_CONTROL 0x0200UL
379 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
380 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
381 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
382 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
383 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
384 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
385 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
386 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
387 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
388 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
389 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
390 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
391 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
392 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
393 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
394 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
395 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
396 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
397 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
398 #define PSYCHO_IOMMU_FLUSH 0x0210UL
399 #define PSYCHO_IOMMU_TAG 0xa580UL
400 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
401 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
402 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
403 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
404 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
405 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
406 #define PSYCHO_IOMMU_DATA 0xa600UL
407 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
408 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
409 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
410 static void psycho_check_iommu_error(struct pci_controller_info *p,
411 unsigned long afsr,
412 unsigned long afar,
413 enum psycho_error_type type)
414 {
415 struct pci_iommu *iommu = p->pbm_A.iommu;
416 unsigned long iommu_tag[16];
417 unsigned long iommu_data[16];
418 unsigned long flags;
419 u64 control;
420 int i;
422 spin_lock_irqsave(&iommu->lock, flags);
423 control = psycho_read(iommu->iommu_control);
424 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
425 char *type_string;
427 /* Clear the error encountered bit. */
428 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
429 psycho_write(iommu->iommu_control, control);
431 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
432 case 0:
433 type_string = "Protection Error";
434 break;
435 case 1:
436 type_string = "Invalid Error";
437 break;
438 case 2:
439 type_string = "TimeOut Error";
440 break;
441 case 3:
442 default:
443 type_string = "ECC Error";
444 break;
445 };
446 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
447 p->index, type_string);
449 /* Put the IOMMU into diagnostic mode and probe
450 * it's TLB for entries with error status.
451 *
452 * It is very possible for another DVMA to occur
453 * while we do this probe, and corrupt the system
454 * further. But we are so screwed at this point
455 * that we are likely to crash hard anyways, so
456 * get as much diagnostic information to the
457 * console as we can.
458 */
459 psycho_write(iommu->iommu_control,
460 control | PSYCHO_IOMMU_CTRL_DENAB);
461 for (i = 0; i < 16; i++) {
462 unsigned long base = p->pbm_A.controller_regs;
464 iommu_tag[i] =
465 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
466 iommu_data[i] =
467 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
469 /* Now clear out the entry. */
470 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
471 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
472 }
474 /* Leave diagnostic mode. */
475 psycho_write(iommu->iommu_control, control);
477 for (i = 0; i < 16; i++) {
478 unsigned long tag, data;
480 tag = iommu_tag[i];
481 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
482 continue;
484 data = iommu_data[i];
485 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
486 case 0:
487 type_string = "Protection Error";
488 break;
489 case 1:
490 type_string = "Invalid Error";
491 break;
492 case 2:
493 type_string = "TimeOut Error";
494 break;
495 case 3:
496 default:
497 type_string = "ECC Error";
498 break;
499 };
500 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
501 p->index, i, type_string,
502 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
503 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
504 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
505 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
506 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
507 p->index, i,
508 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
509 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
510 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
511 }
512 }
513 __psycho_check_stc_error(p, afsr, afar, type);
514 spin_unlock_irqrestore(&iommu->lock, flags);
515 }
517 /* Uncorrectable Errors. Cause of the error and the address are
518 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
519 * relating to UPA interface transactions.
520 */
521 #define PSYCHO_UE_AFSR 0x0030UL
522 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
523 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
524 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
525 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
526 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
527 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
528 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
529 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
530 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
531 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
532 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
533 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
534 #define PSYCHO_UE_AFAR 0x0038UL
536 static irqreturn_t psycho_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
537 {
538 struct pci_controller_info *p = dev_id;
539 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR;
540 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR;
541 unsigned long afsr, afar, error_bits;
542 int reported;
544 /* Latch uncorrectable error status. */
545 afar = psycho_read(afar_reg);
546 afsr = psycho_read(afsr_reg);
548 /* Clear the primary/secondary error status bits. */
549 error_bits = afsr &
550 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
551 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
552 if (!error_bits)
553 return IRQ_NONE;
554 psycho_write(afsr_reg, error_bits);
556 /* Log the error. */
557 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
558 p->index,
559 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
560 "PIO" :
561 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
562 "DMA Read" :
563 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
564 "DMA Write" : "???")))));
565 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
566 p->index,
567 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
568 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
569 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
570 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
571 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
572 printk("PSYCHO%d: UE Secondary errors [", p->index);
573 reported = 0;
574 if (afsr & PSYCHO_UEAFSR_SPIO) {
575 reported++;
576 printk("(PIO)");
577 }
578 if (afsr & PSYCHO_UEAFSR_SDRD) {
579 reported++;
580 printk("(DMA Read)");
581 }
582 if (afsr & PSYCHO_UEAFSR_SDWR) {
583 reported++;
584 printk("(DMA Write)");
585 }
586 if (!reported)
587 printk("(none)");
588 printk("]\n");
590 /* Interrogate IOMMU for error status. */
591 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
593 return IRQ_HANDLED;
594 }
596 /* Correctable Errors. */
597 #define PSYCHO_CE_AFSR 0x0040UL
598 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
599 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
600 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
601 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
602 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
603 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
604 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
605 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
606 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
607 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
608 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
609 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
610 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
611 #define PSYCHO_CE_AFAR 0x0040UL
613 static irqreturn_t psycho_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
614 {
615 struct pci_controller_info *p = dev_id;
616 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR;
617 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR;
618 unsigned long afsr, afar, error_bits;
619 int reported;
621 /* Latch error status. */
622 afar = psycho_read(afar_reg);
623 afsr = psycho_read(afsr_reg);
625 /* Clear primary/secondary error status bits. */
626 error_bits = afsr &
627 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
628 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
629 if (!error_bits)
630 return IRQ_NONE;
631 psycho_write(afsr_reg, error_bits);
633 /* Log the error. */
634 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
635 p->index,
636 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
637 "PIO" :
638 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
639 "DMA Read" :
640 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
641 "DMA Write" : "???")))));
643 /* XXX Use syndrome and afar to print out module string just like
644 * XXX UDB CE trap handler does... -DaveM
645 */
646 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
647 "UPA_MID[%02lx] was_block(%d)\n",
648 p->index,
649 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
650 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
651 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
652 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
653 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
654 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
655 printk("PSYCHO%d: CE Secondary errors [", p->index);
656 reported = 0;
657 if (afsr & PSYCHO_CEAFSR_SPIO) {
658 reported++;
659 printk("(PIO)");
660 }
661 if (afsr & PSYCHO_CEAFSR_SDRD) {
662 reported++;
663 printk("(DMA Read)");
664 }
665 if (afsr & PSYCHO_CEAFSR_SDWR) {
666 reported++;
667 printk("(DMA Write)");
668 }
669 if (!reported)
670 printk("(none)");
671 printk("]\n");
673 return IRQ_HANDLED;
674 }
676 /* PCI Errors. They are signalled by the PCI bus module since they
677 * are associated with a specific bus segment.
678 */
679 #define PSYCHO_PCI_AFSR_A 0x2010UL
680 #define PSYCHO_PCI_AFSR_B 0x4010UL
681 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
682 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
683 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
684 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
685 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
686 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
687 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
688 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
689 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
690 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
691 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
692 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
693 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
694 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
695 #define PSYCHO_PCI_AFAR_A 0x2018UL
696 #define PSYCHO_PCI_AFAR_B 0x4018UL
698 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
699 {
700 unsigned long csr_reg, csr, csr_error_bits;
701 irqreturn_t ret = IRQ_NONE;
702 u16 stat;
704 if (is_pbm_a) {
705 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
706 } else {
707 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
708 }
709 csr = psycho_read(csr_reg);
710 csr_error_bits =
711 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
712 if (csr_error_bits) {
713 /* Clear the errors. */
714 psycho_write(csr_reg, csr);
716 /* Log 'em. */
717 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
718 printk("%s: PCI streaming byte hole error asserted.\n",
719 pbm->name);
720 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
721 printk("%s: PCI SERR signal asserted.\n", pbm->name);
722 ret = IRQ_HANDLED;
723 }
724 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
725 if (stat & (PCI_STATUS_PARITY |
726 PCI_STATUS_SIG_TARGET_ABORT |
727 PCI_STATUS_REC_TARGET_ABORT |
728 PCI_STATUS_REC_MASTER_ABORT |
729 PCI_STATUS_SIG_SYSTEM_ERROR)) {
730 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
731 pbm->name, stat);
732 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
733 ret = IRQ_HANDLED;
734 }
735 return ret;
736 }
738 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
739 {
740 struct pci_pbm_info *pbm = dev_id;
741 struct pci_controller_info *p = pbm->parent;
742 unsigned long afsr_reg, afar_reg;
743 unsigned long afsr, afar, error_bits;
744 int is_pbm_a, reported;
746 is_pbm_a = (pbm == &pbm->parent->pbm_A);
747 if (is_pbm_a) {
748 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
749 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
750 } else {
751 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
752 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
753 }
755 /* Latch error status. */
756 afar = psycho_read(afar_reg);
757 afsr = psycho_read(afsr_reg);
759 /* Clear primary/secondary error status bits. */
760 error_bits = afsr &
761 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
762 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
763 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
764 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
765 if (!error_bits)
766 return psycho_pcierr_intr_other(pbm, is_pbm_a);
767 psycho_write(afsr_reg, error_bits);
769 /* Log the error. */
770 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
771 p->index, (is_pbm_a ? 'A' : 'B'),
772 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
773 "Master Abort" :
774 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
775 "Target Abort" :
776 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
777 "Excessive Retries" :
778 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
779 "Parity Error" : "???"))))));
780 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
781 p->index, (is_pbm_a ? 'A' : 'B'),
782 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
783 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
784 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
785 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
786 p->index, (is_pbm_a ? 'A' : 'B'), afar);
787 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
788 p->index, (is_pbm_a ? 'A' : 'B'));
789 reported = 0;
790 if (afsr & PSYCHO_PCIAFSR_SMA) {
791 reported++;
792 printk("(Master Abort)");
793 }
794 if (afsr & PSYCHO_PCIAFSR_STA) {
795 reported++;
796 printk("(Target Abort)");
797 }
798 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
799 reported++;
800 printk("(Excessive Retries)");
801 }
802 if (afsr & PSYCHO_PCIAFSR_SPERR) {
803 reported++;
804 printk("(Parity Error)");
805 }
806 if (!reported)
807 printk("(none)");
808 printk("]\n");
810 /* For the error types shown, scan PBM's PCI bus for devices
811 * which have logged that error type.
812 */
814 /* If we see a Target Abort, this could be the result of an
815 * IOMMU translation error of some sort. It is extremely
816 * useful to log this information as usually it indicates
817 * a bug in the IOMMU support code or a PCI device driver.
818 */
819 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
820 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
821 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
822 }
823 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
824 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
826 /* For excessive retries, PSYCHO/PBM will abort the device
827 * and there is no way to specifically check for excessive
828 * retries in the config space status registers. So what
829 * we hope is that we'll catch it via the master/target
830 * abort events.
831 */
833 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
834 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
836 return IRQ_HANDLED;
837 }
839 /* XXX What about PowerFail/PowerManagement??? -DaveM */
840 #define PSYCHO_ECC_CTRL 0x0020
841 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
842 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
843 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
844 static void psycho_register_error_handlers(struct pci_controller_info *p)
845 {
846 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
847 struct of_device *op = of_find_device_by_node(pbm->prom_node);
848 unsigned long base = p->pbm_A.controller_regs;
849 u64 tmp;
851 if (!op)
852 return;
854 /* Psycho interrupt property order is:
855 * 0: PCIERR PBM B INO
856 * 1: UE ERR
857 * 2: CE ERR
858 * 3: POWER FAIL
859 * 4: SPARE HARDWARE
860 * 5: PCIERR PBM A INO
861 */
863 if (op->num_irqs < 6)
864 return;
866 request_irq(op->irqs[1], psycho_ue_intr, IRQF_SHARED, "PSYCHO UE", p);
867 request_irq(op->irqs[2], psycho_ce_intr, IRQF_SHARED, "PSYCHO CE", p);
868 request_irq(op->irqs[5], psycho_pcierr_intr, IRQF_SHARED,
869 "PSYCHO PCIERR-A", &p->pbm_A);
870 request_irq(op->irqs[0], psycho_pcierr_intr, IRQF_SHARED,
871 "PSYCHO PCIERR-B", &p->pbm_B);
873 /* Enable UE and CE interrupts for controller. */
874 psycho_write(base + PSYCHO_ECC_CTRL,
875 (PSYCHO_ECCCTRL_EE |
876 PSYCHO_ECCCTRL_UE |
877 PSYCHO_ECCCTRL_CE));
879 /* Enable PCI Error interrupts and clear error
880 * bits for each PBM.
881 */
882 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
883 tmp |= (PSYCHO_PCICTRL_SERR |
884 PSYCHO_PCICTRL_SBH_ERR |
885 PSYCHO_PCICTRL_EEN);
886 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
887 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
889 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
890 tmp |= (PSYCHO_PCICTRL_SERR |
891 PSYCHO_PCICTRL_SBH_ERR |
892 PSYCHO_PCICTRL_EEN);
893 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
894 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
895 }
897 /* PSYCHO boot time probing and initialization. */
898 static void psycho_resource_adjust(struct pci_dev *pdev,
899 struct resource *res,
900 struct resource *root)
901 {
902 res->start += root->start;
903 res->end += root->start;
904 }
906 static void psycho_base_address_update(struct pci_dev *pdev, int resource)
907 {
908 struct pcidev_cookie *pcp = pdev->sysdata;
909 struct pci_pbm_info *pbm = pcp->pbm;
910 struct resource *res, *root;
911 u32 reg;
912 int where, size, is_64bit;
914 res = &pdev->resource[resource];
915 if (resource < 6) {
916 where = PCI_BASE_ADDRESS_0 + (resource * 4);
917 } else if (resource == PCI_ROM_RESOURCE) {
918 where = pdev->rom_base_reg;
919 } else {
920 /* Somebody might have asked allocation of a non-standard resource */
921 return;
922 }
924 is_64bit = 0;
925 if (res->flags & IORESOURCE_IO)
926 root = &pbm->io_space;
927 else {
928 root = &pbm->mem_space;
929 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
930 == PCI_BASE_ADDRESS_MEM_TYPE_64)
931 is_64bit = 1;
932 }
934 size = res->end - res->start;
935 pci_read_config_dword(pdev, where, &reg);
936 reg = ((reg & size) |
937 (((u32)(res->start - root->start)) & ~size));
938 if (resource == PCI_ROM_RESOURCE) {
939 reg |= PCI_ROM_ADDRESS_ENABLE;
940 res->flags |= IORESOURCE_ROM_ENABLE;
941 }
942 pci_write_config_dword(pdev, where, reg);
944 /* This knows that the upper 32-bits of the address
945 * must be zero. Our PCI common layer enforces this.
946 */
947 if (is_64bit)
948 pci_write_config_dword(pdev, where + 4, 0);
949 }
951 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
952 {
953 u8 *addr;
955 /* Set cache-line size to 64 bytes, this is actually
956 * a nop but I do it for completeness.
957 */
958 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
959 0, PCI_CACHE_LINE_SIZE);
960 pci_config_write8(addr, 64 / sizeof(u32));
962 /* Set PBM latency timer to 64 PCI clocks. */
963 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
964 0, PCI_LATENCY_TIMER);
965 pci_config_write8(addr, 64);
966 }
968 static void pbm_scan_bus(struct pci_controller_info *p,
969 struct pci_pbm_info *pbm)
970 {
971 struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
973 if (!cookie) {
974 prom_printf("PSYCHO: Critical allocation failure.\n");
975 prom_halt();
976 }
978 /* All we care about is the PBM. */
979 cookie->pbm = pbm;
981 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
982 p->pci_ops,
983 pbm);
984 pci_fixup_host_bridge_self(pbm->pci_bus);
985 pbm->pci_bus->self->sysdata = cookie;
987 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
988 pci_record_assignments(pbm, pbm->pci_bus);
989 pci_assign_unassigned(pbm, pbm->pci_bus);
990 pci_fixup_irq(pbm, pbm->pci_bus);
991 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
992 pci_setup_busmastering(pbm, pbm->pci_bus);
993 }
995 static void psycho_scan_bus(struct pci_controller_info *p)
996 {
997 pbm_config_busmastering(&p->pbm_B);
998 p->pbm_B.is_66mhz_capable = 0;
999 pbm_config_busmastering(&p->pbm_A);
1000 p->pbm_A.is_66mhz_capable = 1;
1001 pbm_scan_bus(p, &p->pbm_B);
1002 pbm_scan_bus(p, &p->pbm_A);
1004 /* After the PCI bus scan is complete, we can register
1005 * the error interrupt handlers.
1006 */
1007 psycho_register_error_handlers(p);
1010 static void psycho_iommu_init(struct pci_controller_info *p)
1012 struct pci_iommu *iommu = p->pbm_A.iommu;
1013 unsigned long i;
1014 u64 control;
1016 /* Register addresses. */
1017 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
1018 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
1019 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
1020 /* PSYCHO's IOMMU lacks ctx flushing. */
1021 iommu->iommu_ctxflush = 0;
1023 /* We use the main control register of PSYCHO as the write
1024 * completion register.
1025 */
1026 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
1028 /*
1029 * Invalidate TLB Entries.
1030 */
1031 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1032 control |= PSYCHO_IOMMU_CTRL_DENAB;
1033 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1034 for(i = 0; i < 16; i++) {
1035 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
1036 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1039 /* Leave diag mode enabled for full-flushing done
1040 * in pci_iommu.c
1041 */
1042 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
1044 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
1045 __pa(iommu->page_table));
1047 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1048 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
1049 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
1050 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1052 /* If necessary, hook us up for starfire IRQ translations. */
1053 if (this_is_starfire)
1054 starfire_hookup(p->pbm_A.portid);
1057 #define PSYCHO_IRQ_RETRY 0x1a00UL
1058 #define PSYCHO_PCIA_DIAG 0x2020UL
1059 #define PSYCHO_PCIB_DIAG 0x4020UL
1060 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
1061 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
1062 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
1063 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
1064 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
1065 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
1066 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
1067 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
1069 static void psycho_controller_hwinit(struct pci_controller_info *p)
1071 u64 tmp;
1073 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1075 /* Enable arbiter for all PCI slots. */
1076 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
1077 tmp |= PSYCHO_PCICTRL_AEN;
1078 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
1080 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1081 tmp |= PSYCHO_PCICTRL_AEN;
1082 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1084 /* Disable DMA write / PIO read synchronization on
1085 * both PCI bus segments.
1086 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1087 */
1088 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1089 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1090 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1092 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1093 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1094 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1097 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1098 struct pci_pbm_info *pbm)
1100 char *name = pbm->name;
1102 pbm->io_space.name = pbm->mem_space.name = name;
1104 request_resource(&ioport_resource, &pbm->io_space);
1105 request_resource(&iomem_resource, &pbm->mem_space);
1106 pci_register_legacy_regions(&pbm->io_space,
1107 &pbm->mem_space);
1110 static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1111 struct pci_pbm_info *pbm,
1112 int is_pbm_a)
1114 unsigned long base = pbm->controller_regs;
1115 u64 control;
1117 if (is_pbm_a) {
1118 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1119 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1120 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1121 } else {
1122 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1123 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1124 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1126 /* PSYCHO's streaming buffer lacks ctx flushing. */
1127 pbm->stc.strbuf_ctxflush = 0;
1128 pbm->stc.strbuf_ctxmatch_base = 0;
1130 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1131 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1132 + 63UL)
1133 & ~63UL);
1134 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1135 __pa(pbm->stc.strbuf_flushflag);
1137 /* Enable the streaming buffer. We have to be careful
1138 * just in case OBP left it with LRU locking enabled.
1140 * It is possible to control if PBM will be rerun on
1141 * line misses. Currently I just retain whatever setting
1142 * OBP left us with. All checks so far show it having
1143 * a value of zero.
1144 */
1145 #undef PSYCHO_STRBUF_RERUN_ENABLE
1146 #undef PSYCHO_STRBUF_RERUN_DISABLE
1147 control = psycho_read(pbm->stc.strbuf_control);
1148 control |= PSYCHO_STRBUF_CTRL_ENAB;
1149 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1150 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1151 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1152 #else
1153 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1154 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1155 #endif
1156 #endif
1157 psycho_write(pbm->stc.strbuf_control, control);
1159 pbm->stc.strbuf_enabled = 1;
1162 #define PSYCHO_IOSPACE_A 0x002000000UL
1163 #define PSYCHO_IOSPACE_B 0x002010000UL
1164 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1165 #define PSYCHO_MEMSPACE_A 0x100000000UL
1166 #define PSYCHO_MEMSPACE_B 0x180000000UL
1167 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1169 static void psycho_pbm_init(struct pci_controller_info *p,
1170 struct device_node *dp, int is_pbm_a)
1172 unsigned int *busrange;
1173 struct property *prop;
1174 struct pci_pbm_info *pbm;
1175 int len;
1177 if (is_pbm_a) {
1178 pbm = &p->pbm_A;
1179 pbm->pci_first_slot = 1;
1180 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_A;
1181 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_A;
1182 } else {
1183 pbm = &p->pbm_B;
1184 pbm->pci_first_slot = 2;
1185 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_B;
1186 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_B;
1189 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
1190 pbm->chip_version = 0;
1191 prop = of_find_property(dp, "version#", NULL);
1192 if (prop)
1193 pbm->chip_version = *(int *) prop->value;
1194 pbm->chip_revision = 0;
1195 prop = of_find_property(dp, "module-revision#", NULL);
1196 if (prop)
1197 pbm->chip_revision = *(int *) prop->value;
1199 pbm->io_space.end = pbm->io_space.start + PSYCHO_IOSPACE_SIZE;
1200 pbm->io_space.flags = IORESOURCE_IO;
1201 pbm->mem_space.end = pbm->mem_space.start + PSYCHO_MEMSPACE_SIZE;
1202 pbm->mem_space.flags = IORESOURCE_MEM;
1204 pbm->parent = p;
1205 pbm->prom_node = dp;
1206 pbm->name = dp->full_name;
1208 pbm_register_toplevel_resources(p, pbm);
1210 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1211 pbm->name,
1212 pbm->chip_version, pbm->chip_revision);
1214 prop = of_find_property(dp, "ranges", &len);
1215 if (prop) {
1216 pbm->pbm_ranges = prop->value;
1217 pbm->num_pbm_ranges =
1218 (len / sizeof(struct linux_prom_pci_ranges));
1219 } else {
1220 pbm->num_pbm_ranges = 0;
1223 prop = of_find_property(dp, "interrupt-map", &len);
1224 if (prop) {
1225 pbm->pbm_intmap = prop->value;
1226 pbm->num_pbm_intmap =
1227 (len / sizeof(struct linux_prom_pci_intmap));
1229 prop = of_find_property(dp, "interrupt-map-mask", NULL);
1230 pbm->pbm_intmask = prop->value;
1231 } else {
1232 pbm->num_pbm_intmap = 0;
1235 prop = of_find_property(dp, "bus-range", NULL);
1236 busrange = prop->value;
1237 pbm->pci_first_busno = busrange[0];
1238 pbm->pci_last_busno = busrange[1];
1240 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1243 #define PSYCHO_CONFIGSPACE 0x001000000UL
1245 void psycho_init(struct device_node *dp, char *model_name)
1247 struct linux_prom64_registers *pr_regs;
1248 struct pci_controller_info *p;
1249 struct pci_iommu *iommu;
1250 struct property *prop;
1251 u32 upa_portid;
1252 int is_pbm_a;
1254 upa_portid = 0xff;
1255 prop = of_find_property(dp, "upa-portid", NULL);
1256 if (prop)
1257 upa_portid = *(u32 *) prop->value;
1259 for(p = pci_controller_root; p; p = p->next) {
1260 if (p->pbm_A.portid == upa_portid) {
1261 is_pbm_a = (p->pbm_A.prom_node == NULL);
1262 psycho_pbm_init(p, dp, is_pbm_a);
1263 return;
1267 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1268 if (!p) {
1269 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1270 prom_halt();
1272 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1273 if (!iommu) {
1274 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1275 prom_halt();
1277 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1279 p->next = pci_controller_root;
1280 pci_controller_root = p;
1282 p->pbm_A.portid = upa_portid;
1283 p->pbm_B.portid = upa_portid;
1284 p->index = pci_num_controllers++;
1285 p->pbms_same_domain = 0;
1286 p->scan_bus = psycho_scan_bus;
1287 p->base_address_update = psycho_base_address_update;
1288 p->resource_adjust = psycho_resource_adjust;
1289 p->pci_ops = &psycho_ops;
1291 prop = of_find_property(dp, "reg", NULL);
1292 pr_regs = prop->value;
1294 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1295 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1297 p->pbm_A.config_space = p->pbm_B.config_space =
1298 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1300 /*
1301 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1302 * we need to adjust our MEM space mask.
1303 */
1304 pci_memspace_mask = 0x7fffffffUL;
1306 psycho_controller_hwinit(p);
1308 psycho_iommu_init(p);
1310 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1311 psycho_pbm_init(p, dp, is_pbm_a);