view arch/sparc64/kernel/pci_impl.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
line source
1 /* $Id: pci_impl.h,v 1.9 2001/06/13 06:34:30 davem Exp $
2 * pci_impl.h: Helper definitions for PCI controller support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
7 #ifndef PCI_IMPL_H
8 #define PCI_IMPL_H
10 #include <linux/types.h>
11 #include <linux/spinlock.h>
12 #include <asm/io.h>
13 #include <asm/prom.h>
15 extern struct pci_controller_info *pci_controller_root;
17 extern int pci_num_controllers;
19 /* PCI bus scanning and fixup support. */
20 extern void pci_fixup_host_bridge_self(struct pci_bus *pbus);
21 extern void pci_fill_in_pbm_cookies(struct pci_bus *pbus,
22 struct pci_pbm_info *pbm,
23 struct device_node *prom_node);
24 extern void pci_record_assignments(struct pci_pbm_info *pbm,
25 struct pci_bus *pbus);
26 extern void pci_assign_unassigned(struct pci_pbm_info *pbm,
27 struct pci_bus *pbus);
28 extern void pci_fixup_irq(struct pci_pbm_info *pbm,
29 struct pci_bus *pbus);
30 extern void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
31 struct pci_bus *pbus);
32 extern void pci_setup_busmastering(struct pci_pbm_info *pbm,
33 struct pci_bus *pbus);
34 extern void pci_register_legacy_regions(struct resource *io_res,
35 struct resource *mem_res);
37 /* Error reporting support. */
38 extern void pci_scan_for_target_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
39 extern void pci_scan_for_master_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
40 extern void pci_scan_for_parity_error(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
42 /* Configuration space access. */
43 extern void pci_config_read8(u8 *addr, u8 *ret);
44 extern void pci_config_read16(u16 *addr, u16 *ret);
45 extern void pci_config_read32(u32 *addr, u32 *ret);
46 extern void pci_config_write8(u8 *addr, u8 val);
47 extern void pci_config_write16(u16 *addr, u16 val);
48 extern void pci_config_write32(u32 *addr, u32 val);
50 #endif /* !(PCI_IMPL_H) */