ia64/linux-2.6.18-xen.hg

view arch/sparc64/kernel/cpu.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /* cpu.c: Dinky routines to look for the kind of Sparc cpu
2 * we are on.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/sched.h>
10 #include <linux/smp.h>
11 #include <asm/asi.h>
12 #include <asm/system.h>
13 #include <asm/fpumacro.h>
14 #include <asm/cpudata.h>
15 #include <asm/spitfire.h>
17 DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
19 struct cpu_iu_info {
20 short manuf;
21 short impl;
22 char* cpu_name; /* should be enough I hope... */
23 };
25 struct cpu_fp_info {
26 short manuf;
27 short impl;
28 char fpu_vers;
29 char* fp_name;
30 };
32 struct cpu_fp_info linux_sparc_fpu[] = {
33 { 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
34 { 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
35 { 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
36 { 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
37 { 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
38 { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
39 { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
40 { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
41 { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
42 { 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
43 { 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
44 };
46 #define NSPARCFPU ARRAY_SIZE(linux_sparc_fpu)
48 struct cpu_iu_info linux_sparc_chips[] = {
49 { 0x17, 0x10, "TI UltraSparc I (SpitFire)"},
50 { 0x22, 0x10, "TI UltraSparc I (SpitFire)"},
51 { 0x17, 0x11, "TI UltraSparc II (BlackBird)"},
52 { 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
53 { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
54 { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
55 { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
56 { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
57 { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
58 { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
59 { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
60 };
62 #define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips)
64 char *sparc_cpu_type = "cpu-oops";
65 char *sparc_fpu_type = "fpu-oops";
67 unsigned int fsr_storage;
69 void __init cpu_probe(void)
70 {
71 unsigned long ver, fpu_vers, manuf, impl, fprs;
72 int i;
74 if (tlb_type == hypervisor) {
75 sparc_cpu_type = "UltraSparc T1 (Niagara)";
76 sparc_fpu_type = "UltraSparc T1 integrated FPU";
77 return;
78 }
80 fprs = fprs_read();
81 fprs_write(FPRS_FEF);
82 __asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
83 : "=&r" (ver)
84 : "r" (&fpu_vers));
85 fprs_write(fprs);
87 manuf = ((ver >> 48) & 0xffff);
88 impl = ((ver >> 32) & 0xffff);
90 fpu_vers = ((fpu_vers >> 17) & 0x7);
92 retry:
93 for (i = 0; i < NSPARCCHIPS; i++) {
94 if (linux_sparc_chips[i].manuf == manuf) {
95 if (linux_sparc_chips[i].impl == impl) {
96 sparc_cpu_type =
97 linux_sparc_chips[i].cpu_name;
98 break;
99 }
100 }
101 }
103 if (i == NSPARCCHIPS) {
104 /* Maybe it is a cheetah+ derivative, report it as cheetah+
105 * in that case until we learn the real names.
106 */
107 if (manuf == 0x3e &&
108 impl > 0x15) {
109 impl = 0x15;
110 goto retry;
111 } else {
112 printk("DEBUG: manuf[%lx] impl[%lx]\n",
113 manuf, impl);
114 }
115 sparc_cpu_type = "Unknown CPU";
116 }
118 for (i = 0; i < NSPARCFPU; i++) {
119 if (linux_sparc_fpu[i].manuf == manuf &&
120 linux_sparc_fpu[i].impl == impl) {
121 if (linux_sparc_fpu[i].fpu_vers == fpu_vers) {
122 sparc_fpu_type =
123 linux_sparc_fpu[i].fp_name;
124 break;
125 }
126 }
127 }
129 if (i == NSPARCFPU) {
130 printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
131 manuf, impl, fpu_vers);
132 sparc_fpu_type = "Unknown FPU";
133 }
134 }