ia64/linux-2.6.18-xen.hg

view arch/mips/sni/setup.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Setup pointers to hardware-dependent routines.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org)
9 */
10 #include <linux/eisa.h>
11 #include <linux/hdreg.h>
12 #include <linux/ioport.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/pm.h>
18 #include <linux/pci.h>
19 #include <linux/console.h>
20 #include <linux/fb.h>
21 #include <linux/screen_info.h>
23 #ifdef CONFIG_ARC
24 #include <asm/arc/types.h>
25 #include <asm/sgialib.h>
26 #endif
28 #include <asm/bcache.h>
29 #include <asm/bootinfo.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/mc146818-time.h>
33 #include <asm/processor.h>
34 #include <asm/ptrace.h>
35 #include <asm/reboot.h>
36 #include <asm/sni.h>
37 #include <asm/time.h>
38 #include <asm/traps.h>
40 extern void sni_machine_restart(char *command);
41 extern void sni_machine_halt(void);
42 extern void sni_machine_power_off(void);
44 void __init plat_timer_setup(struct irqaction *irq)
45 {
46 /* set the clock to 100 Hz */
47 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
48 outb_p(LATCH & 0xff , 0x40); /* LSB */
49 outb(LATCH >> 8 , 0x40); /* MSB */
50 setup_irq(0, irq);
51 }
53 /*
54 * A bit more gossip about the iron we're running on ...
55 */
56 static inline void sni_pcimt_detect(void)
57 {
58 char boardtype[80];
59 unsigned char csmsr;
60 char *p = boardtype;
61 unsigned int asic;
63 csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
65 p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
66 if ((csmsr & 0x80) == 0)
67 p += sprintf(p, ", board revision %s",
68 (csmsr & 0x20) ? "D" : "C");
69 asic = csmsr & 0x80;
70 asic = (csmsr & 0x08) ? asic : !asic;
71 p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
72 printk("%s.\n", boardtype);
73 }
75 static void __init sni_display_setup(void)
76 {
77 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC)
78 struct screen_info *si = &screen_info;
79 DISPLAY_STATUS *di;
81 di = ArcGetDisplayStatus(1);
83 if (di) {
84 si->orig_x = di->CursorXPosition;
85 si->orig_y = di->CursorYPosition;
86 si->orig_video_cols = di->CursorMaxXPosition;
87 si->orig_video_lines = di->CursorMaxYPosition;
88 si->orig_video_isVGA = VIDEO_TYPE_VGAC;
89 si->orig_video_points = 16;
90 }
91 #endif
92 }
94 static struct resource sni_io_resource = {
95 .start = 0x00001000UL,
96 .end = 0x03bfffffUL,
97 .name = "PCIMT IO MEM",
98 .flags = IORESOURCE_IO,
99 };
101 static struct resource pcimt_io_resources[] = {
102 {
103 .start = 0x00,
104 .end = 0x1f,
105 .name = "dma1",
106 .flags = IORESOURCE_BUSY
107 }, {
108 .start = 0x40,
109 .end = 0x5f,
110 .name = "timer",
111 .flags = IORESOURCE_BUSY
112 }, {
113 .start = 0x60,
114 .end = 0x6f,
115 .name = "keyboard",
116 .flags = IORESOURCE_BUSY
117 }, {
118 .start = 0x80,
119 .end = 0x8f,
120 .name = "dma page reg",
121 .flags = IORESOURCE_BUSY
122 }, {
123 .start = 0xc0,
124 .end = 0xdf,
125 .name = "dma2",
126 .flags = IORESOURCE_BUSY
127 }, {
128 .start = 0xcfc,
129 .end = 0xcff,
130 .name = "PCI config data",
131 .flags = IORESOURCE_BUSY
132 }
133 };
135 static struct resource sni_mem_resource = {
136 .start = 0x10000000UL,
137 .end = 0xffffffffUL,
138 .name = "PCIMT PCI MEM",
139 .flags = IORESOURCE_MEM
140 };
142 /*
143 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
144 * for other purposes. Be paranoid and allocate all of the before the PCI
145 * code gets a chance to to map anything else there ...
146 *
147 * This leaves the following areas available:
148 *
149 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
150 * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
151 * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
152 * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
153 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
154 */
155 static struct resource pcimt_mem_resources[] = {
156 {
157 .start = 0x100a0000,
158 .end = 0x100bffff,
159 .name = "Video RAM area",
160 .flags = IORESOURCE_BUSY
161 }, {
162 .start = 0x100c0000,
163 .end = 0x100fffff,
164 .name = "ISA Reserved",
165 .flags = IORESOURCE_BUSY
166 }, {
167 .start = 0x14000000,
168 .end = 0x17bfffff,
169 .name = "PCI IO",
170 .flags = IORESOURCE_BUSY
171 }, {
172 .start = 0x17c00000,
173 .end = 0x17ffffff,
174 .name = "Cache Replacement Area",
175 .flags = IORESOURCE_BUSY
176 }, {
177 .start = 0x1a000000,
178 .end = 0x1a000003,
179 .name = "PCI INT Acknowledge",
180 .flags = IORESOURCE_BUSY
181 }, {
182 .start = 0x1fc00000,
183 .end = 0x1fc7ffff,
184 .name = "Boot PROM",
185 .flags = IORESOURCE_BUSY
186 }, {
187 .start = 0x1fc80000,
188 .end = 0x1fcfffff,
189 .name = "Diag PROM",
190 .flags = IORESOURCE_BUSY
191 }, {
192 .start = 0x1fd00000,
193 .end = 0x1fdfffff,
194 .name = "X-Bus",
195 .flags = IORESOURCE_BUSY
196 }, {
197 .start = 0x1fe00000,
198 .end = 0x1fefffff,
199 .name = "BIOS map",
200 .flags = IORESOURCE_BUSY
201 }, {
202 .start = 0x1ff00000,
203 .end = 0x1ff7ffff,
204 .name = "NVRAM / EEPROM",
205 .flags = IORESOURCE_BUSY
206 }, {
207 .start = 0x1fff0000,
208 .end = 0x1fffefff,
209 .name = "ASIC PCI",
210 .flags = IORESOURCE_BUSY
211 }, {
212 .start = 0x1ffff000,
213 .end = 0x1fffffff,
214 .name = "MP Agent",
215 .flags = IORESOURCE_BUSY
216 }, {
217 .start = 0x20000000,
218 .end = 0x9fffffff,
219 .name = "Main Memory",
220 .flags = IORESOURCE_BUSY
221 }
222 };
224 static void __init sni_resource_init(void)
225 {
226 int i;
228 /* request I/O space for devices used on all i[345]86 PCs */
229 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
230 request_resource(&ioport_resource, pcimt_io_resources + i);
232 /* request mem space for pcimt-specific devices */
233 for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
234 request_resource(&sni_mem_resource, pcimt_mem_resources + i);
236 ioport_resource.end = sni_io_resource.end;
237 }
239 extern struct pci_ops sni_pci_ops;
241 static struct pci_controller sni_controller = {
242 .pci_ops = &sni_pci_ops,
243 .mem_resource = &sni_mem_resource,
244 .mem_offset = 0x10000000UL,
245 .io_resource = &sni_io_resource,
246 .io_offset = 0x00000000UL
247 };
249 static inline void sni_pcimt_time_init(void)
250 {
251 rtc_mips_get_time = mc146818_get_cmos_time;
252 rtc_mips_set_time = mc146818_set_rtc_mmss;
253 }
255 void __init plat_mem_setup(void)
256 {
257 sni_pcimt_detect();
258 sni_pcimt_sc_init();
259 sni_pcimt_time_init();
261 set_io_port_base(SNI_PORT_BASE);
262 ioport_resource.end = sni_io_resource.end;
264 /*
265 * Setup (E)ISA I/O memory access stuff
266 */
267 isa_slot_offset = 0xb0000000;
268 #ifdef CONFIG_EISA
269 EISA_bus = 1;
270 #endif
272 sni_resource_init();
274 _machine_restart = sni_machine_restart;
275 _machine_halt = sni_machine_halt;
276 pm_power_off = sni_machine_power_off;
278 sni_display_setup();
280 #ifdef CONFIG_PCI
281 register_pci_controller(&sni_controller);
282 #endif
283 }