ia64/linux-2.6.18-xen.hg

view arch/mips/pci/pci-vr41xx.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
3 *
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #ifndef __PCI_VR41XX_H
23 #define __PCI_VR41XX_H
25 #define PCIU_BASE 0x0f000c00UL
26 #define PCIU_SIZE 0x200UL
28 #define PCIMMAW1REG 0x00
29 #define PCIMMAW2REG 0x04
30 #define PCITAW1REG 0x08
31 #define PCITAW2REG 0x0c
32 #define PCIMIOAWREG 0x10
33 #define IBA(addr) ((addr) & 0xff000000U)
34 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
35 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
36 #define TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U)
37 #define ITA(addr) (((addr) >> 24) & 0x000000ffU)
38 #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU)
39 #define WINEN 0x1000U
40 #define PCICONFDREG 0x14
41 #define PCICONFAREG 0x18
42 #define PCIMAILREG 0x1c
43 #define BUSERRADREG 0x24
44 #define EA(reg) ((reg) &0xfffffffc)
46 #define INTCNTSTAREG 0x28
47 #define MABTCLR 0x80000000U
48 #define TRDYCLR 0x40000000U
49 #define PARCLR 0x20000000U
50 #define MBCLR 0x10000000U
51 #define SERRCLR 0x08000000U
52 #define RTYCLR 0x04000000U
53 #define MABCLR 0x02000000U
54 #define TABCLR 0x01000000U
55 /* RFU */
56 #define MABTMSK 0x00008000U
57 #define TRDYMSK 0x00004000U
58 #define PARMSK 0x00002000U
59 #define MBMSK 0x00001000U
60 #define SERRMSK 0x00000800U
61 #define RTYMSK 0x00000400U
62 #define MABMSK 0x00000200U
63 #define TABMSK 0x00000100U
64 #define IBAMABT 0x00000080U
65 #define TRDYRCH 0x00000040U
66 #define PAR 0x00000020U
67 #define MB 0x00000010U
68 #define PCISERR 0x00000008U
69 #define RTYRCH 0x00000004U
70 #define MABORT 0x00000002U
71 #define TABORT 0x00000001U
73 #define PCIEXACCREG 0x2c
74 #define UNLOCK 0x2U
75 #define EAREQ 0x1U
76 #define PCIRECONTREG 0x30
77 #define RTRYCNT(reg) ((reg) & 0x000000ffU)
78 #define PCIENREG 0x34
79 #define PCIU_CONFIG_DONE 0x4U
80 #define PCICLKSELREG 0x38
81 #define EQUAL_VTCLOCK 0x2U
82 #define HALF_VTCLOCK 0x0U
83 #define ONE_THIRD_VTCLOCK 0x3U
84 #define QUARTER_VTCLOCK 0x1U
85 #define PCITRDYVREG 0x3c
86 #define TRDYV(val) ((uint32_t)(val) & 0xffU)
87 #define PCICLKRUNREG 0x60
89 #define VENDORIDREG 0x100
90 #define DEVICEIDREG 0x100
91 #define COMMANDREG 0x104
92 #define STATUSREG 0x104
93 #define REVIDREG 0x108
94 #define CLASSREG 0x108
95 #define CACHELSREG 0x10c
96 #define LATTIMEREG 0x10c
97 #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U)
98 #define MAILBAREG 0x110
99 #define PCIMBA1REG 0x114
100 #define PCIMBA2REG 0x118
101 #define MBADD(base) ((base) & 0xfffff800U)
102 #define PMBA(base) ((base) & 0xffe00000U)
103 #define PREF 0x8U
104 #define PREF_APPROVAL 0x8U
105 #define PREF_DISAPPROVAL 0x0U
106 #define TYPE 0x6U
107 #define TYPE_32BITSPACE 0x0U
108 #define MSI 0x1U
109 #define MSI_MEMORY 0x0U
110 #define INTLINEREG 0x13c
111 #define INTPINREG 0x13c
112 #define RETVALREG 0x140
113 #define PCIAPCNTREG 0x140
114 #define TKYGNT 0x04000000U
115 #define TKYGNT_ENABLE 0x04000000U
116 #define TKYGNT_DISABLE 0x00000000U
117 #define PAPC 0x03000000U
118 #define PAPC_ALTERNATE_B 0x02000000U
119 #define PAPC_ALTERNATE_0 0x01000000U
120 #define PAPC_FAIR 0x00000000U
121 #define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U)
122 #define RTYVAL_MASK 0xff00U
124 #define PCI_CLOCK_MAX 33333333U
126 /*
127 * Default setup
128 */
129 #define PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U
130 #define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U
131 #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U
133 #define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U
134 #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U
136 #define PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U
137 #define PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U
138 #define PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U
140 #define PCI_MAILBOX_BASE_ADDRESS 0x00000000U
142 #define PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U
144 #define IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS)
145 #define IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS
146 #define IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK)
148 #define PCI_IO_RESOURCE_START 0x01000000UL
149 #define PCI_IO_RESOURCE_END 0x01ffffffUL
151 #define PCI_MEM_RESOURCE_START 0x11000000UL
152 #define PCI_MEM_RESOURCE_END 0x13ffffffUL
154 #endif /* __PCI_VR41XX_H */