ia64/linux-2.6.18-xen.hg

view arch/mips/pci/pci-sb1250.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Copyright (C) 2001,2002,2003 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
20 /*
21 * BCM1250-specific PCI support
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 */
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/init.h>
37 #include <linux/mm.h>
38 #include <linux/console.h>
39 #include <linux/tty.h>
41 #include <asm/io.h>
43 #include <asm/sibyte/sb1250_defs.h>
44 #include <asm/sibyte/sb1250_regs.h>
45 #include <asm/sibyte/sb1250_scd.h>
46 #include <asm/sibyte/board.h>
48 /*
49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg
51 */
52 #define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where))
53 #define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
55 static void *cfg_space;
57 #define PCI_BUS_ENABLED 1
58 #define LDT_BUS_ENABLED 2
59 #define PCI_DEVICE_MODE 4
61 static int sb1250_bus_status = 0;
63 #define PCI_BRIDGE_DEVICE 0
64 #define LDT_BRIDGE_DEVICE 1
66 #ifdef CONFIG_SIBYTE_HAS_LDT
67 /*
68 * HT's level-sensitive interrupts require EOI, which is generated
69 * through a 4MB memory-mapped region
70 */
71 unsigned long ldt_eoi_space;
72 #endif
74 /*
75 * Read/write 32-bit values in config space.
76 */
77 static inline u32 READCFG32(u32 addr)
78 {
79 return *(u32 *) (cfg_space + (addr & ~3));
80 }
82 static inline void WRITECFG32(u32 addr, u32 data)
83 {
84 *(u32 *) (cfg_space + (addr & ~3)) = data;
85 }
87 int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
88 {
89 return dev->irq;
90 }
92 /* Do platform specific device initialization at pci_enable_device() time */
93 int pcibios_plat_dev_init(struct pci_dev *dev)
94 {
95 return 0;
96 }
98 /*
99 * Some checks before doing config cycles:
100 * In PCI Device Mode, hide everything on bus 0 except the LDT host
101 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
102 */
103 static int sb1250_pci_can_access(struct pci_bus *bus, int devfn)
104 {
105 u32 devno;
107 if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
108 return 0;
110 if (bus->number == 0) {
111 devno = PCI_SLOT(devfn);
112 if (devno == LDT_BRIDGE_DEVICE)
113 return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
114 else if (sb1250_bus_status & PCI_DEVICE_MODE)
115 return 0;
116 else
117 return 1;
118 } else
119 return 1;
120 }
122 /*
123 * Read/write access functions for various sizes of values
124 * in config space. Return all 1's for disallowed accesses
125 * for a kludgy but adequate simulation of master aborts.
126 */
128 static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn,
129 int where, int size, u32 * val)
130 {
131 u32 data = 0;
133 if ((size == 2) && (where & 1))
134 return PCIBIOS_BAD_REGISTER_NUMBER;
135 else if ((size == 4) && (where & 3))
136 return PCIBIOS_BAD_REGISTER_NUMBER;
138 if (sb1250_pci_can_access(bus, devfn))
139 data = READCFG32(CFGADDR(bus, devfn, where));
140 else
141 data = 0xFFFFFFFF;
143 if (size == 1)
144 *val = (data >> ((where & 3) << 3)) & 0xff;
145 else if (size == 2)
146 *val = (data >> ((where & 3) << 3)) & 0xffff;
147 else
148 *val = data;
150 return PCIBIOS_SUCCESSFUL;
151 }
153 static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
154 int where, int size, u32 val)
155 {
156 u32 cfgaddr = CFGADDR(bus, devfn, where);
157 u32 data = 0;
159 if ((size == 2) && (where & 1))
160 return PCIBIOS_BAD_REGISTER_NUMBER;
161 else if ((size == 4) && (where & 3))
162 return PCIBIOS_BAD_REGISTER_NUMBER;
164 if (!sb1250_pci_can_access(bus, devfn))
165 return PCIBIOS_BAD_REGISTER_NUMBER;
167 data = READCFG32(cfgaddr);
169 if (size == 1)
170 data = (data & ~(0xff << ((where & 3) << 3))) |
171 (val << ((where & 3) << 3));
172 else if (size == 2)
173 data = (data & ~(0xffff << ((where & 3) << 3))) |
174 (val << ((where & 3) << 3));
175 else
176 data = val;
178 WRITECFG32(cfgaddr, data);
180 return PCIBIOS_SUCCESSFUL;
181 }
183 struct pci_ops sb1250_pci_ops = {
184 .read = sb1250_pcibios_read,
185 .write = sb1250_pcibios_write,
186 };
188 static struct resource sb1250_mem_resource = {
189 .name = "SB1250 PCI MEM",
190 .start = 0x40000000UL,
191 .end = 0x5fffffffUL,
192 .flags = IORESOURCE_MEM,
193 };
195 static struct resource sb1250_io_resource = {
196 .name = "SB1250 PCI I/O",
197 .start = 0x00000000UL,
198 .end = 0x01ffffffUL,
199 .flags = IORESOURCE_IO,
200 };
202 struct pci_controller sb1250_controller = {
203 .pci_ops = &sb1250_pci_ops,
204 .mem_resource = &sb1250_mem_resource,
205 .io_resource = &sb1250_io_resource,
206 };
208 static int __init sb1250_pcibios_init(void)
209 {
210 uint32_t cmdreg;
211 uint64_t reg;
212 extern int pci_probe_only;
214 /* CFE will assign PCI resources */
215 pci_probe_only = 1;
217 /* Avoid ISA compat ranges. */
218 PCIBIOS_MIN_IO = 0x00008000UL;
219 PCIBIOS_MIN_MEM = 0x01000000UL;
221 /* Set I/O resource limits. */
222 ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by sb1250 */
223 iomem_resource.end = 0xffffffffUL; /* no HT support yet */
225 cfg_space =
226 ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);
228 /*
229 * See if the PCI bus has been configured by the firmware.
230 */
231 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
232 if (!(reg & M_SYS_PCI_HOST)) {
233 sb1250_bus_status |= PCI_DEVICE_MODE;
234 } else {
235 cmdreg =
236 READCFG32(CFGOFFSET
237 (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
238 PCI_COMMAND));
239 if (!(cmdreg & PCI_COMMAND_MASTER)) {
240 printk
241 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
242 iounmap(cfg_space);
243 return 0;
244 }
245 sb1250_bus_status |= PCI_BUS_ENABLED;
246 }
248 /*
249 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
250 * space. Use "match bytes" policy to make everything look
251 * little-endian. So, you need to also set
252 * CONFIG_SWAP_IO_SPACE, but this is the combination that
253 * works correctly with most of Linux's drivers.
254 * XXX ehs: Should this happen in PCI Device mode?
255 */
257 set_io_port_base((unsigned long)
258 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
259 isa_slot_offset = (unsigned long)
260 ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
262 #ifdef CONFIG_SIBYTE_HAS_LDT
263 /*
264 * Also check the LDT bridge's enable, just in case we didn't
265 * initialize that one.
266 */
268 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
269 PCI_COMMAND));
270 if (cmdreg & PCI_COMMAND_MASTER) {
271 sb1250_bus_status |= LDT_BUS_ENABLED;
273 /*
274 * Need bits 23:16 to convey vector number. Note that
275 * this consumes 4MB of kernel-mapped memory
276 * (Kseg2/Kseg3) for 32-bit kernel.
277 */
278 ldt_eoi_space = (unsigned long)
279 ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES,
280 4 * 1024 * 1024);
281 }
282 #endif
284 register_pci_controller(&sb1250_controller);
286 #ifdef CONFIG_VGA_CONSOLE
287 take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
288 #endif
289 return 0;
290 }
291 arch_initcall(sb1250_pcibios_init);