ia64/linux-2.6.18-xen.hg

view arch/mips/pci/pci-ddb5477.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * PCI code for DDB5477.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/pci.h>
19 #include <asm/bootinfo.h>
20 #include <asm/debug.h>
22 #include <asm/ddb5xxx/ddb5xxx.h>
24 static struct resource extpci_io_resource = {
25 .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
26 .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
27 .name = "ext pci IO space",
28 .flags = IORESOURCE_IO
29 };
31 static struct resource extpci_mem_resource = {
32 .start = DDB_PCI0_MEM_BASE + 0x100000,
33 .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
34 .name = "ext pci memory space",
35 .flags = IORESOURCE_MEM
36 };
38 static struct resource iopci_io_resource = {
39 .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
40 .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
41 .name = "io pci IO space",
42 .flags = IORESOURCE_IO
43 };
45 static struct resource iopci_mem_resource = {
46 .start = DDB_PCI1_MEM_BASE,
47 .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
48 .name = "ext pci memory space",
49 .flags = IORESOURCE_MEM
50 };
52 extern struct pci_ops ddb5477_ext_pci_ops;
53 extern struct pci_ops ddb5477_io_pci_ops;
55 struct pci_controller ddb5477_ext_controller = {
56 .pci_ops = &ddb5477_ext_pci_ops,
57 .io_resource = &extpci_io_resource,
58 .mem_resource = &extpci_mem_resource
59 };
61 struct pci_controller ddb5477_io_controller = {
62 .pci_ops = &ddb5477_io_pci_ops,
63 .io_resource = &iopci_io_resource,
64 .mem_resource = &iopci_mem_resource
65 };
69 /*
70 * we fix up irqs based on the slot number.
71 * The first entry is at AD:11.
72 * Fortunately this works because, although we have two pci buses,
73 * they all have different slot numbers (except for rockhopper slot 20
74 * which is handled below).
75 *
76 */
78 /*
79 * irq mapping : device -> pci int # -> vrc4377 irq# ,
80 * ddb5477 board manual page 4 and vrc5477 manual page 46
81 */
83 /*
84 * based on ddb5477 manual page 11
85 */
86 #define MAX_SLOT_NUM 21
87 static unsigned char irq_map[MAX_SLOT_NUM] = {
88 /* SLOT: 0, AD:11 */ 0xff,
89 /* SLOT: 1, AD:12 */ 0xff,
90 /* SLOT: 2, AD:13 */ 0xff,
91 /* SLOT: 3, AD:14 */ 0xff,
92 /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */
93 /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */
94 /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */
95 /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */
96 /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */
97 /* SLOT: 9, AD:20 */ 0xff,
98 /* SLOT: 10, AD:21 */ 0xff,
99 /* SLOT: 11, AD:22 */ 0xff,
100 /* SLOT: 12, AD:23 */ 0xff,
101 /* SLOT: 13, AD:24 */ 0xff,
102 /* SLOT: 14, AD:25 */ 0xff,
103 /* SLOT: 15, AD:26 */ 0xff,
104 /* SLOT: 16, AD:27 */ 0xff,
105 /* SLOT: 17, AD:28 */ 0xff,
106 /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
107 /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
108 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
109 };
110 static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
111 /* SLOT: 0, AD:11 */ 0xff,
112 /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */
113 /* SLOT: 2, AD:13 */ 0xff,
114 /* SLOT: 3, AD:14 */ 0xff,
115 /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */
116 /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */
117 /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */
118 /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */
119 /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */
120 /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */
121 /* SLOT: 10, AD:21 */ 0xff,
122 /* SLOT: 11, AD:22 */ 0xff,
123 /* SLOT: 12, AD:23 */ 0xff,
124 /* SLOT: 13, AD:24 */ 0xff,
125 /* SLOT: 14, AD:25 */ 0xff,
126 /* SLOT: 15, AD:26 */ 0xff,
127 /* SLOT: 16, AD:27 */ 0xff,
128 /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */
129 /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
130 /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
131 /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
132 };
134 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
135 {
136 int slot_num;
137 unsigned char *slot_irq_map;
138 unsigned char irq;
140 /*
141 * We ignore the swizzled slot and pin values. The original
142 * pci_fixup_irq() codes largely base irq number on the dev slot
143 * numbers because except for one case they are unique even
144 * though there are multiple pci buses.
145 */
147 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
148 slot_irq_map = rockhopperII_irq_map;
149 else
150 slot_irq_map = irq_map;
152 slot_num = PCI_SLOT(dev->devfn);
153 irq = slot_irq_map[slot_num];
155 db_assert(slot_num < MAX_SLOT_NUM);
157 db_assert(irq != 0xff);
159 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
161 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
162 /* hack to distinquish overlapping slot 20s, one
163 * on bus 0 (ALI USB on the M1535 on the backplane),
164 * and one on bus 2 (NEC USB controller on the CPU board)
165 * Make the M1535 USB - ISA IRQ number 9.
166 */
167 if (slot_num == 20 && dev->bus->number == 0) {
168 pci_write_config_byte(dev,
169 PCI_INTERRUPT_LINE,
170 9);
171 irq = 9;
172 }
174 }
176 return irq;
177 }
179 /* Do platform specific device initialization at pci_enable_device() time */
180 int pcibios_plat_dev_init(struct pci_dev *dev)
181 {
182 return 0;
183 }
185 void ddb_pci_reset_bus(void)
186 {
187 u32 temp;
189 /*
190 * I am not sure about the "official" procedure, the following
191 * steps work as far as I know:
192 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
193 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
194 * The same is true for both PCI channels.
195 */
196 temp = ddb_in32(DDB_PCICTL0_H);
197 temp |= 0x80000000;
198 ddb_out32(DDB_PCICTL0_H, temp);
199 temp &= ~0xc0000000;
200 ddb_out32(DDB_PCICTL0_H, temp);
202 temp = ddb_in32(DDB_PCICTL1_H);
203 temp |= 0x80000000;
204 ddb_out32(DDB_PCICTL1_H, temp);
205 temp &= ~0xc0000000;
206 ddb_out32(DDB_PCICTL1_H, temp);
207 }