ia64/linux-2.6.18-xen.hg

view arch/mips/pci/pci-bcm1480.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
20 /*
21 * BCM1x80/1x55-specific PCI support
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 *
33 * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
34 */
35 #include <linux/types.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/init.h>
39 #include <linux/mm.h>
40 #include <linux/console.h>
41 #include <linux/tty.h>
43 #include <asm/sibyte/bcm1480_regs.h>
44 #include <asm/sibyte/bcm1480_scd.h>
45 #include <asm/sibyte/board.h>
46 #include <asm/io.h>
48 /*
49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg
51 */
52 #define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
53 #define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
55 static void *cfg_space;
57 #define PCI_BUS_ENABLED 1
58 #define PCI_DEVICE_MODE 2
60 static int bcm1480_bus_status = 0;
62 #define PCI_BRIDGE_DEVICE 0
64 /*
65 * Read/write 32-bit values in config space.
66 */
67 static inline u32 READCFG32(u32 addr)
68 {
69 return *(u32 *)(cfg_space + (addr&~3));
70 }
72 static inline void WRITECFG32(u32 addr, u32 data)
73 {
74 *(u32 *)(cfg_space + (addr & ~3)) = data;
75 }
77 int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
78 {
79 return dev->irq;
80 }
82 /* Do platform specific device initialization at pci_enable_device() time */
83 int pcibios_plat_dev_init(struct pci_dev *dev)
84 {
85 return 0;
86 }
88 /*
89 * Some checks before doing config cycles:
90 * In PCI Device Mode, hide everything on bus 0 except the LDT host
91 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
92 */
93 static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
94 {
95 u32 devno;
97 if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
98 return 0;
100 if (bus->number == 0) {
101 devno = PCI_SLOT(devfn);
102 if (bcm1480_bus_status & PCI_DEVICE_MODE)
103 return 0;
104 else
105 return 1;
106 } else
107 return 1;
108 }
110 /*
111 * Read/write access functions for various sizes of values
112 * in config space. Return all 1's for disallowed accesses
113 * for a kludgy but adequate simulation of master aborts.
114 */
116 static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
117 int where, int size, u32 * val)
118 {
119 u32 data = 0;
121 if ((size == 2) && (where & 1))
122 return PCIBIOS_BAD_REGISTER_NUMBER;
123 else if ((size == 4) && (where & 3))
124 return PCIBIOS_BAD_REGISTER_NUMBER;
126 if (bcm1480_pci_can_access(bus, devfn))
127 data = READCFG32(CFGADDR(bus, devfn, where));
128 else
129 data = 0xFFFFFFFF;
131 if (size == 1)
132 *val = (data >> ((where & 3) << 3)) & 0xff;
133 else if (size == 2)
134 *val = (data >> ((where & 3) << 3)) & 0xffff;
135 else
136 *val = data;
138 return PCIBIOS_SUCCESSFUL;
139 }
141 static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
142 int where, int size, u32 val)
143 {
144 u32 cfgaddr = CFGADDR(bus, devfn, where);
145 u32 data = 0;
147 if ((size == 2) && (where & 1))
148 return PCIBIOS_BAD_REGISTER_NUMBER;
149 else if ((size == 4) && (where & 3))
150 return PCIBIOS_BAD_REGISTER_NUMBER;
152 if (!bcm1480_pci_can_access(bus, devfn))
153 return PCIBIOS_BAD_REGISTER_NUMBER;
155 data = READCFG32(cfgaddr);
157 if (size == 1)
158 data = (data & ~(0xff << ((where & 3) << 3))) |
159 (val << ((where & 3) << 3));
160 else if (size == 2)
161 data = (data & ~(0xffff << ((where & 3) << 3))) |
162 (val << ((where & 3) << 3));
163 else
164 data = val;
166 WRITECFG32(cfgaddr, data);
168 return PCIBIOS_SUCCESSFUL;
169 }
171 struct pci_ops bcm1480_pci_ops = {
172 bcm1480_pcibios_read,
173 bcm1480_pcibios_write,
174 };
176 static struct resource bcm1480_mem_resource = {
177 .name = "BCM1480 PCI MEM",
178 .start = 0x30000000UL,
179 .end = 0x3fffffffUL,
180 .flags = IORESOURCE_MEM,
181 };
183 static struct resource bcm1480_io_resource = {
184 .name = "BCM1480 PCI I/O",
185 .start = 0x2c000000UL,
186 .end = 0x2dffffffUL,
187 .flags = IORESOURCE_IO,
188 };
190 struct pci_controller bcm1480_controller = {
191 .pci_ops = &bcm1480_pci_ops,
192 .mem_resource = &bcm1480_mem_resource,
193 .io_resource = &bcm1480_io_resource,
194 };
197 static int __init bcm1480_pcibios_init(void)
198 {
199 uint32_t cmdreg;
200 uint64_t reg;
201 extern int pci_probe_only;
203 /* CFE will assign PCI resources */
204 pci_probe_only = 1;
206 /* Avoid ISA compat ranges. */
207 PCIBIOS_MIN_IO = 0x00008000UL;
208 PCIBIOS_MIN_MEM = 0x01000000UL;
210 /* Set I/O resource limits. - unlimited for now to accomodate HT */
211 ioport_resource.end = 0xffffffffUL;
212 iomem_resource.end = 0xffffffffUL;
214 cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);
216 /*
217 * See if the PCI bus has been configured by the firmware.
218 */
219 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
220 if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
221 bcm1480_bus_status |= PCI_DEVICE_MODE;
222 } else {
223 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
224 PCI_COMMAND));
225 if (!(cmdreg & PCI_COMMAND_MASTER)) {
226 printk
227 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
228 iounmap(cfg_space);
229 return 1; /* XXX */
230 }
231 bcm1480_bus_status |= PCI_BUS_ENABLED;
232 }
234 /* turn on ExpMemEn */
235 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
236 WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
237 cmdreg | 0x10);
238 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
240 /*
241 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
242 * space. Use "match bytes" policy to make everything look
243 * little-endian. So, you need to also set
244 * CONFIG_SWAP_IO_SPACE, but this is the combination that
245 * works correctly with most of Linux's drivers.
246 * XXX ehs: Should this happen in PCI Device mode?
247 */
249 set_io_port_base((unsigned long)
250 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
251 isa_slot_offset = (unsigned long)
252 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
254 register_pci_controller(&bcm1480_controller);
256 #ifdef CONFIG_VGA_CONSOLE
257 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
258 #endif
259 return 0;
260 }
262 arch_initcall(bcm1480_pcibios_init);