ia64/linux-2.6.18-xen.hg

view arch/mips/pci/ops-tx3927.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
10 *
11 * Define the pci_ops for JMR3927.
12 *
13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36 #include <linux/types.h>
37 #include <linux/pci.h>
38 #include <linux/kernel.h>
39 #include <linux/init.h>
41 #include <asm/addrspace.h>
42 #include <asm/jmr3927/jmr3927.h>
43 #include <asm/debug.h>
45 static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
46 unsigned char where)
47 {
48 if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
49 return PCIBIOS_DEVICE_NOT_FOUND;
51 tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) |
52 ((dev_fn & 0xff) << 0x08) |
53 (where & 0xfc);
55 /* clear M_ABORT and Disable M_ABORT Int. */
56 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
57 tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
59 return PCIBIOS_SUCCESSFUL;
60 }
62 static inline int check_abort(void)
63 {
64 if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
65 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
66 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
67 return PCIBIOS_DEVICE_NOT_FOUND;
69 return PCIBIOS_SUCCESSFUL;
70 }
72 static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
73 int where, int size, u32 * val)
74 {
75 int ret;
77 ret = mkaddr(bus->number, devfn, where);
78 if (ret)
79 return ret;
81 switch (size) {
82 case 1:
83 *val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
84 break;
86 case 2:
87 *val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
88 break;
90 case 4:
91 *val = le32_to_cpu(tx3927_pcicptr->icd);
92 break;
93 }
95 return check_abort();
96 }
98 static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
99 int where, int size, u32 val)
100 {
101 int ret;
103 ret = mkaddr(bus->number, devfn, where);
104 if (ret)
105 return ret;
107 switch (size) {
108 case 1:
109 *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
110 break;
112 case 2:
113 *(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
114 cpu_to_le16(val);
115 break;
117 case 4:
118 tx3927_pcicptr->icd = cpu_to_le32(val);
119 }
121 if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
122 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
123 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
124 return PCIBIOS_DEVICE_NOT_FOUND;
126 return check_abort();
127 }
129 struct pci_ops jmr3927_pci_ops = {
130 jmr3927_pci_read_config,
131 jmr3927_pci_write_config,
132 };
135 #ifndef JMR3927_INIT_INDIRECT_PCI
137 inline unsigned long tc_readl(volatile __u32 * addr)
138 {
139 return readl(addr);
140 }
142 inline void tc_writel(unsigned long data, volatile __u32 * addr)
143 {
144 writel(data, addr);
145 }
146 #else
148 unsigned long tc_readl(volatile __u32 * addr)
149 {
150 unsigned long val;
152 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
153 (unsigned long) CPHYSADDR(addr);
154 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
155 (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) |
156 PCI_IPCIBE_IBE_LONG;
157 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
158 val =
159 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
160 ipcidata);
161 /* clear by setting */
162 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
163 return val;
164 }
166 void tc_writel(unsigned long data, volatile __u32 * addr)
167 {
168 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
169 cpu_to_le32(data);
170 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
171 (unsigned long) CPHYSADDR(addr);
172 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
173 (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) |
174 PCI_IPCIBE_IBE_LONG;
175 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
176 /* clear by setting */
177 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
178 }
180 unsigned char tx_ioinb(unsigned char *addr)
181 {
182 unsigned long val;
183 __u32 ioaddr;
184 int offset;
185 int byte;
187 ioaddr = (unsigned long) addr;
188 offset = ioaddr & 0x3;
189 byte = 0xf & ~(8 >> offset);
191 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
192 (unsigned long) ioaddr;
193 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
194 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
195 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
196 val =
197 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
198 ipcidata);
199 val = val & 0xff;
200 /* clear by setting */
201 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
202 return val;
203 }
205 void tx_iooutb(unsigned long data, unsigned char *addr)
206 {
207 __u32 ioaddr;
208 int offset;
209 int byte;
211 data = data | (data << 8) | (data << 16) | (data << 24);
212 ioaddr = (unsigned long) addr;
213 offset = ioaddr & 0x3;
214 byte = 0xf & ~(8 >> offset);
216 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
217 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
218 (unsigned long) ioaddr;
219 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
220 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
221 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
222 /* clear by setting */
223 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
224 }
226 unsigned short tx_ioinw(unsigned short *addr)
227 {
228 unsigned long val;
229 __u32 ioaddr;
230 int offset;
231 int byte;
233 ioaddr = (unsigned long) addr;
234 offset = ioaddr & 0x2;
235 byte = 3 << offset;
237 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
238 (unsigned long) ioaddr;
239 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
240 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
241 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
242 val =
243 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
244 ipcidata);
245 val = val & 0xffff;
246 /* clear by setting */
247 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
248 return val;
250 }
252 void tx_iooutw(unsigned long data, unsigned short *addr)
253 {
254 __u32 ioaddr;
255 int offset;
256 int byte;
258 data = data | (data << 16);
259 ioaddr = (unsigned long) addr;
260 offset = ioaddr & 0x2;
261 byte = 3 << offset;
263 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
264 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
265 (unsigned long) ioaddr;
266 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
267 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
268 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
269 /* clear by setting */
270 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
271 }
273 unsigned long tx_ioinl(unsigned int *addr)
274 {
275 unsigned long val;
276 __u32 ioaddr;
278 ioaddr = (unsigned long) addr;
279 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
280 (unsigned long) ioaddr;
281 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
282 (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) |
283 PCI_IPCIBE_IBE_LONG;
284 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
285 val =
286 le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
287 ipcidata);
288 /* clear by setting */
289 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
290 return val;
291 }
293 void tx_iooutl(unsigned long data, unsigned int *addr)
294 {
295 __u32 ioaddr;
297 ioaddr = (unsigned long) addr;
298 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
299 cpu_to_le32(data);
300 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
301 (unsigned long) ioaddr;
302 *(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
303 (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) |
304 PCI_IPCIBE_IBE_LONG;
305 while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
306 /* clear by setting */
307 tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
308 }
310 void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count)
311 {
312 unsigned char *ptr = (unsigned char *) buffer;
314 while (count--) {
315 *ptr++ = tx_ioinb(addr);
316 }
317 }
319 void tx_insword(unsigned short *addr, void *buffer, unsigned int count)
320 {
321 unsigned short *ptr = (unsigned short *) buffer;
323 while (count--) {
324 *ptr++ = tx_ioinw(addr);
325 }
326 }
328 void tx_inslong(unsigned int *addr, void *buffer, unsigned int count)
329 {
330 unsigned long *ptr = (unsigned long *) buffer;
332 while (count--) {
333 *ptr++ = tx_ioinl(addr);
334 }
335 }
337 void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count)
338 {
339 unsigned char *ptr = (unsigned char *) buffer;
341 while (count--) {
342 tx_iooutb(*ptr++, addr);
343 }
344 }
346 void tx_outsword(unsigned short *addr, void *buffer, unsigned int count)
347 {
348 unsigned short *ptr = (unsigned short *) buffer;
350 while (count--) {
351 tx_iooutw(*ptr++, addr);
352 }
353 }
355 void tx_outslong(unsigned int *addr, void *buffer, unsigned int count)
356 {
357 unsigned long *ptr = (unsigned long *) buffer;
359 while (count--) {
360 tx_iooutl(*ptr++, addr);
361 }
362 }
363 #endif