ia64/linux-2.6.18-xen.hg

view arch/mips/pci/ops-it8172.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 system controller specific pci support.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/kernel.h>
35 #include <linux/init.h>
37 #include <asm/it8172/it8172.h>
38 #include <asm/it8172/it8172_pci.h>
40 #define PCI_ACCESS_READ 0
41 #define PCI_ACCESS_WRITE 1
43 #undef DEBUG
44 #ifdef DEBUG
45 #define DBG(x...) printk(x)
46 #else
47 #define DBG(x...)
48 #endif
50 static struct resource pci_mem_resource_1;
52 static struct resource pci_io_resource = {
53 .start = 0x14018000,
54 .end = 0x17FFFFFF,
55 .name = "io pci IO space",
56 .flags = IORESOURCE_IO
57 };
59 static struct resource pci_mem_resource_0 = {
60 .start = 0x10101000,
61 .end = 0x13FFFFFF,
62 .name = "ext pci memory space 0/1",
63 .flags = IORESOURCE_MEM,
64 .parent = &pci_mem_resource_0,
65 .sibling = NULL,
66 .child = &pci_mem_resource_1
67 };
69 static struct resource pci_mem_resource_1 = {
70 .start = 0x1A000000,
71 .end = 0x1FBFFFFF,
72 .name = "ext pci memory space 2/3",
73 .flags = IORESOURCE_MEM,
74 .parent = &pci_mem_resource_0
75 };
77 extern struct pci_ops it8172_pci_ops;
79 struct pci_controller it8172_controller = {
80 .pci_ops = &it8172_pci_ops,
81 .io_resource = &pci_io_resource,
82 .mem_resource = &pci_mem_resource_0,
83 };
85 static int it8172_pcibios_config_access(unsigned char access_type,
86 struct pci_bus *bus,
87 unsigned int devfn, int where,
88 u32 * data)
89 {
90 /*
91 * config cycles are on 4 byte boundary only
92 */
94 /* Setup address */
95 IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) |
96 (devfn << IT_FUNCNUM_SHF) | (where & ~0x3));
98 if (access_type == PCI_ACCESS_WRITE) {
99 IT_WRITE(IT_CONFDATA, *data);
100 } else {
101 IT_READ(IT_CONFDATA, *data);
102 }
104 /*
105 * Revisit: check for master or target abort.
106 */
107 return 0;
108 }
111 /*
112 * We can't address 8 and 16 bit words directly. Instead we have to
113 * read/write a 32bit word and mask/modify the data we actually want.
114 */
115 static write_config(struct pci_bus *bus, unsigned int devfn, int where,
116 int size, u32 val)
117 {
118 u32 data = 0;
120 switch (size) {
121 case 1:
122 if (it8172_pcibios_config_access
123 (PCI_ACCESS_READ, dev, where, &data))
124 return -1;
126 *val = (data >> ((where & 3) << 3)) & 0xff;
128 return PCIBIOS_SUCCESSFUL;
130 case 2:
132 if (where & 1)
133 return PCIBIOS_BAD_REGISTER_NUMBER;
135 if (it8172_pcibios_config_access
136 (PCI_ACCESS_READ, dev, where, &data))
137 return -1;
139 *val = (data >> ((where & 3) << 3)) & 0xffff;
140 DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
141 dev->bus->number, dev->devfn, where, *val);
143 return PCIBIOS_SUCCESSFUL;
145 case 4:
147 if (where & 3)
148 return PCIBIOS_BAD_REGISTER_NUMBER;
150 if (it8172_pcibios_config_access
151 (PCI_ACCESS_READ, dev, where, &data))
152 return -1;
154 *val = data;
156 return PCIBIOS_SUCCESSFUL;
157 }
158 }
161 static write_config(struct pci_bus *bus, unsigned int devfn, int where,
162 int size, u32 val)
163 {
164 u32 data = 0;
166 switch (size) {
167 case 1:
168 if (it8172_pcibios_config_access
169 (PCI_ACCESS_READ, dev, where, &data))
170 return -1;
172 data = (data & ~(0xff << ((where & 3) << 3))) |
173 (val << ((where & 3) << 3));
175 if (it8172_pcibios_config_access
176 (PCI_ACCESS_WRITE, dev, where, &data))
177 return -1;
179 return PCIBIOS_SUCCESSFUL;
181 case 2:
182 if (where & 1)
183 return PCIBIOS_BAD_REGISTER_NUMBER;
185 if (it8172_pcibios_config_access
186 (PCI_ACCESS_READ, dev, where, &data))
187 eturn - 1;
189 data = (data & ~(0xffff << ((where & 3) << 3))) |
190 (val << ((where & 3) << 3));
192 if (it8172_pcibios_config_access
193 (PCI_ACCESS_WRITE, dev, where, &data))
194 return -1;
196 return PCIBIOS_SUCCESSFUL;
198 case 4:
199 if (where & 3)
200 return PCIBIOS_BAD_REGISTER_NUMBER;
202 if (it8172_pcibios_config_access
203 (PCI_ACCESS_WRITE, dev, where, &val))
204 return -1;
206 return PCIBIOS_SUCCESSFUL;
207 }
208 }
210 struct pci_ops it8172_pci_ops = {
211 .read = read_config,
212 .write = write_config,
213 };