ia64/linux-2.6.18-xen.hg

view arch/mips/pci/ops-gt96100.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Galileo EV96100 board specific pci support.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This file was derived from Carsten Langgaard's
11 * arch/mips/mips-boards/generic/pci.c
12 *
13 * Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36 #include <linux/types.h>
37 #include <linux/pci.h>
38 #include <linux/kernel.h>
39 #include <linux/init.h>
41 #include <asm/delay.h>
42 #include <asm/gt64120.h>
43 #include <asm/galileo-boards/ev96100.h>
45 #define PCI_ACCESS_READ 0
46 #define PCI_ACCESS_WRITE 1
48 static int static gt96100_config_access(unsigned char access_type,
49 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
50 {
51 unsigned char bus = bus->number;
52 u32 intr;
54 /*
55 * Because of a bug in the galileo (for slot 31).
56 */
57 if (bus == 0 && devfn >= PCI_DEVFN(31, 0))
58 return PCIBIOS_DEVICE_NOT_FOUND;
60 /* Clear cause register bits */
61 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
62 GT_INTRCAUSE_TARABORT0_BIT));
64 /* Setup address */
65 GT_WRITE(GT_PCI0_CFGADDR_OFS,
66 (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
67 (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
68 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
69 GT_PCI0_CFGADDR_CONFIGEN_BIT);
70 udelay(2);
73 if (access_type == PCI_ACCESS_WRITE) {
74 if (devfn != 0)
75 *data = le32_to_cpu(*data);
76 GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
77 } else {
78 *data = GT_READ(GT_PCI0_CFGDATA_OFS);
79 if (devfn != 0)
80 *data = le32_to_cpu(*data);
81 }
83 udelay(2);
85 /* Check for master or target abort */
86 intr = GT_READ(GT_INTRCAUSE_OFS);
88 if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
89 /* Error occured */
91 /* Clear bits */
92 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
93 GT_INTRCAUSE_TARABORT0_BIT));
94 return -1;
95 }
96 return 0;
97 }
99 /*
100 * We can't address 8 and 16 bit words directly. Instead we have to
101 * read/write a 32bit word and mask/modify the data we actually want.
102 */
103 static int gt96100_pcibios_read(struct pci_bus *bus, unsigned int devfn,
104 int where, int size, u32 * val)
105 {
106 u32 data = 0;
108 if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
109 return PCIBIOS_DEVICE_NOT_FOUND;
111 switch (size) {
112 case 1:
113 *val = (data >> ((where & 3) << 3)) & 0xff;
114 break;
116 case 2:
117 *val = (data >> ((where & 3) << 3)) & 0xffff;
118 break;
120 case 4:
121 *val = data;
122 break;
123 }
124 return PCIBIOS_SUCCESSFUL;
125 }
127 static int gt96100_pcibios_write(struct pci_bus *bus, unsigned int devfn,
128 int where, int size, u32 val)
129 {
130 u32 data = 0;
132 switch (size) {
133 case 1:
134 if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
135 return -1;
137 data = (data & ~(0xff << ((where & 3) << 3))) |
138 (val << ((where & 3) << 3));
140 if (gt96100_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
141 return -1;
143 return PCIBIOS_SUCCESSFUL;
145 case 2:
146 if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
147 return -1;
149 data = (data & ~(0xffff << ((where & 3) << 3))) |
150 (val << ((where & 3) << 3));
152 if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
153 return -1;
156 return PCIBIOS_SUCCESSFUL;
158 case 4:
159 if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val))
160 return -1;
162 return PCIBIOS_SUCCESSFUL;
163 }
164 }
166 struct pci_ops gt96100_pci_ops = {
167 .read = gt96100_pcibios_read,
168 .write = gt96100_pcibios_write
169 };