ia64/linux-2.6.18-xen.hg

view arch/mips/pci/fixup-cobalt.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Cobalt Qube/Raq PCI support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10 */
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
16 #include <asm/pci.h>
17 #include <asm/io.h>
18 #include <asm/gt64120.h>
20 #include <asm/mach-cobalt/cobalt.h>
22 extern int cobalt_board_id;
24 static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
25 {
26 if (dev->devfn == PCI_DEVFN(0, 0) &&
27 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
29 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
31 printk(KERN_INFO "Galileo: fixed bridge class\n");
32 }
33 }
35 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
36 qube_raq_galileo_early_fixup);
38 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
39 {
40 unsigned short cfgword;
41 unsigned char lt;
43 /* Enable Bus Mastering and fast back to back. */
44 pci_read_config_word(dev, PCI_COMMAND, &cfgword);
45 cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
46 pci_write_config_word(dev, PCI_COMMAND, cfgword);
48 /* Enable both ide interfaces. ROM only enables primary one. */
49 pci_write_config_byte(dev, 0x40, 0xb);
51 /* Set latency timer to reasonable value. */
52 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
53 if (lt < 64)
54 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
55 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
56 }
58 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
59 qube_raq_via_bmIDE_fixup);
61 static void qube_raq_galileo_fixup(struct pci_dev *dev)
62 {
63 unsigned short galileo_id;
65 if (dev->devfn != PCI_DEVFN(0, 0))
66 return;
68 /* Fix PCI latency-timer and cache-line-size values in Galileo
69 * host bridge.
70 */
71 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
72 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
74 /*
75 * The code described by the comment below has been removed
76 * as it causes bus mastering by the Ethernet controllers
77 * to break under any kind of network load. We always set
78 * the retry timeouts to their maximum.
79 *
80 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
81 *
82 * On all machines prior to Q2, we had the STOP line disconnected
83 * from Galileo to VIA on PCI. The new Galileo does not function
84 * correctly unless we have it connected.
85 *
86 * Therefore we must set the disconnect/retry cycle values to
87 * something sensible when using the new Galileo.
88 */
89 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
90 galileo_id &= 0xff; /* mask off class info */
92 printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
94 #if 0
95 if (galileo_id >= 0x10) {
96 /* New Galileo, assumes PCI stop line to VIA is connected. */
97 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
98 } else if (galileo_id == 0x1 || galileo_id == 0x2)
99 #endif
100 {
101 signed int timeo;
102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
103 timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
105 GALILEO_OUTL(
106 (0xff << 16) | /* retry count */
107 (0xff << 8) | /* timeout 1 */
108 0xff, /* timeout 0 */
109 GT_PCI0_TOR_OFS);
111 /* enable PCI retry exceeded interrupt */
112 GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
113 }
114 }
116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
117 qube_raq_galileo_fixup);
119 static char irq_tab_qube1[] __initdata = {
120 [COBALT_PCICONF_CPU] = 0,
121 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
122 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
123 [COBALT_PCICONF_VIA] = 0,
124 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
125 [COBALT_PCICONF_ETH1] = 0
126 };
128 static char irq_tab_cobalt[] __initdata = {
129 [COBALT_PCICONF_CPU] = 0,
130 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
131 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
132 [COBALT_PCICONF_VIA] = 0,
133 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
134 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ
135 };
137 static char irq_tab_raq2[] __initdata = {
138 [COBALT_PCICONF_CPU] = 0,
139 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
140 [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ,
141 [COBALT_PCICONF_VIA] = 0,
142 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
143 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ
144 };
146 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
147 {
148 if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
149 return irq_tab_qube1[slot];
151 if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
152 return irq_tab_raq2[slot];
154 return irq_tab_cobalt[slot];
155 }
157 /* Do platform specific device initialization at pci_enable_device() time */
158 int pcibios_plat_dev_init(struct pci_dev *dev)
159 {
160 return 0;
161 }