ia64/linux-2.6.18-xen.hg

view arch/mips/basler/excite/excite_irq.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * Copyright (C) by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslereb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/module.h>
24 #include <linux/signal.h>
25 #include <linux/sched.h>
26 #include <linux/types.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/timex.h>
30 #include <linux/slab.h>
31 #include <linux/random.h>
32 #include <asm/bitops.h>
33 #include <asm/bootinfo.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/irq_cpu.h>
37 #include <asm/mipsregs.h>
38 #include <asm/system.h>
39 #include <asm/rm9k-ocd.h>
41 #include <excite.h>
43 extern asmlinkage void excite_handle_int(void);
45 /*
46 * Initialize the interrupt handler
47 */
48 void __init arch_init_irq(void)
49 {
50 mips_cpu_irq_init(0);
51 rm7k_cpu_irq_init(8);
52 rm9k_cpu_irq_init(12);
54 #ifdef CONFIG_KGDB
55 excite_kgdb_init();
56 #endif
57 }
59 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
60 {
61 const u32
62 interrupts = read_c0_cause() >> 8,
63 mask = ((read_c0_status() >> 8) & 0x000000ff) |
64 (read_c0_intcontrol() & 0x0000ff00),
65 pending = interrupts & mask;
66 u32 msgintflags, msgintmask, msgint;
68 /* process timer interrupt */
69 if (pending & (1 << TIMER_IRQ)) {
70 do_IRQ(TIMER_IRQ, regs);
71 return;
72 }
74 /* Process PCI interrupts */
75 #if USB_IRQ < 10
76 msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
77 msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
78 msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
79 if ((pending & (1 << USB_IRQ)) && msgint) {
80 #else
81 if (pending & (1 << USB_IRQ)) {
82 #endif
83 do_IRQ(USB_IRQ, regs);
84 return;
85 }
87 /* Process TITAN interrupts */
88 msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
89 msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
90 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
91 if ((pending & (1 << TITAN_IRQ)) && msgint) {
92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
93 #if defined(CONFIG_KGDB)
94 excite_kgdb_inthdl(regs);
95 #endif
96 do_IRQ(TITAN_IRQ, regs);
97 return;
98 }
100 /* Process FPGA line #0 interrupts */
101 msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
102 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
103 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
104 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
105 do_IRQ(FPGA0_IRQ, regs);
106 return;
107 }
109 /* Process FPGA line #1 interrupts */
110 msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
111 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
112 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
113 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
114 do_IRQ(FPGA1_IRQ, regs);
115 return;
116 }
118 /* Process PHY interrupts */
119 msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
120 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
121 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
122 if ((pending & (1 << PHY_IRQ)) && msgint) {
123 do_IRQ(PHY_IRQ, regs);
124 return;
125 }
127 /* Process spurious interrupts */
128 spurious_interrupt(regs);
129 }