ia64/linux-2.6.18-xen.hg

view arch/alpha/kernel/machvec_impl.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * linux/arch/alpha/kernel/machvec.h
3 *
4 * Copyright (C) 1997, 1998 Richard Henderson
5 *
6 * This file has goodies to help simplify instantiation of machine vectors.
7 */
9 #include <asm/pgalloc.h>
11 /* Whee. These systems don't have an HAE:
12 IRONGATE, MARVEL, POLARIS, TSUNAMI, TITAN, WILDFIRE
13 Fix things up for the GENERIC kernel by defining the HAE address
14 to be that of the cache. Now we can read and write it as we like. ;-) */
15 #define IRONGATE_HAE_ADDRESS (&alpha_mv.hae_cache)
16 #define MARVEL_HAE_ADDRESS (&alpha_mv.hae_cache)
17 #define POLARIS_HAE_ADDRESS (&alpha_mv.hae_cache)
18 #define TSUNAMI_HAE_ADDRESS (&alpha_mv.hae_cache)
19 #define TITAN_HAE_ADDRESS (&alpha_mv.hae_cache)
20 #define WILDFIRE_HAE_ADDRESS (&alpha_mv.hae_cache)
22 #ifdef CIA_ONE_HAE_WINDOW
23 #define CIA_HAE_ADDRESS (&alpha_mv.hae_cache)
24 #endif
25 #ifdef MCPCIA_ONE_HAE_WINDOW
26 #define MCPCIA_HAE_ADDRESS (&alpha_mv.hae_cache)
27 #endif
29 /* Only a few systems don't define IACK_SC, handling all interrupts through
30 the SRM console. But splitting out that one case from IO() below
31 seems like such a pain. Define this to get things to compile. */
32 #define JENSEN_IACK_SC 1
33 #define T2_IACK_SC 1
34 #define WILDFIRE_IACK_SC 1 /* FIXME */
36 /*
37 * Some helpful macros for filling in the blanks.
38 */
40 #define CAT1(x,y) x##y
41 #define CAT(x,y) CAT1(x,y)
43 #define DO_DEFAULT_RTC .rtc_port = 0x70
45 #define DO_EV4_MMU \
46 .max_asn = EV4_MAX_ASN, \
47 .mv_switch_mm = ev4_switch_mm, \
48 .mv_activate_mm = ev4_activate_mm, \
49 .mv_flush_tlb_current = ev4_flush_tlb_current, \
50 .mv_flush_tlb_current_page = ev4_flush_tlb_current_page
52 #define DO_EV5_MMU \
53 .max_asn = EV5_MAX_ASN, \
54 .mv_switch_mm = ev5_switch_mm, \
55 .mv_activate_mm = ev5_activate_mm, \
56 .mv_flush_tlb_current = ev5_flush_tlb_current, \
57 .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
59 #define DO_EV6_MMU \
60 .max_asn = EV6_MAX_ASN, \
61 .mv_switch_mm = ev5_switch_mm, \
62 .mv_activate_mm = ev5_activate_mm, \
63 .mv_flush_tlb_current = ev5_flush_tlb_current, \
64 .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
66 #define DO_EV7_MMU \
67 .max_asn = EV6_MAX_ASN, \
68 .mv_switch_mm = ev5_switch_mm, \
69 .mv_activate_mm = ev5_activate_mm, \
70 .mv_flush_tlb_current = ev5_flush_tlb_current, \
71 .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
73 #define IO_LITE(UP,low) \
74 .hae_register = (unsigned long *) CAT(UP,_HAE_ADDRESS), \
75 .iack_sc = CAT(UP,_IACK_SC), \
76 .mv_ioread8 = CAT(low,_ioread8), \
77 .mv_ioread16 = CAT(low,_ioread16), \
78 .mv_ioread32 = CAT(low,_ioread32), \
79 .mv_iowrite8 = CAT(low,_iowrite8), \
80 .mv_iowrite16 = CAT(low,_iowrite16), \
81 .mv_iowrite32 = CAT(low,_iowrite32), \
82 .mv_readb = CAT(low,_readb), \
83 .mv_readw = CAT(low,_readw), \
84 .mv_readl = CAT(low,_readl), \
85 .mv_readq = CAT(low,_readq), \
86 .mv_writeb = CAT(low,_writeb), \
87 .mv_writew = CAT(low,_writew), \
88 .mv_writel = CAT(low,_writel), \
89 .mv_writeq = CAT(low,_writeq), \
90 .mv_ioportmap = CAT(low,_ioportmap), \
91 .mv_ioremap = CAT(low,_ioremap), \
92 .mv_iounmap = CAT(low,_iounmap), \
93 .mv_is_ioaddr = CAT(low,_is_ioaddr), \
94 .mv_is_mmio = CAT(low,_is_mmio) \
96 #define IO(UP,low) \
97 IO_LITE(UP,low), \
98 .pci_ops = &CAT(low,_pci_ops), \
99 .mv_pci_tbi = CAT(low,_pci_tbi)
101 #define DO_APECS_IO IO(APECS,apecs)
102 #define DO_CIA_IO IO(CIA,cia)
103 #define DO_IRONGATE_IO IO(IRONGATE,irongate)
104 #define DO_LCA_IO IO(LCA,lca)
105 #define DO_MARVEL_IO IO(MARVEL,marvel)
106 #define DO_MCPCIA_IO IO(MCPCIA,mcpcia)
107 #define DO_POLARIS_IO IO(POLARIS,polaris)
108 #define DO_T2_IO IO(T2,t2)
109 #define DO_TSUNAMI_IO IO(TSUNAMI,tsunami)
110 #define DO_TITAN_IO IO(TITAN,titan)
111 #define DO_WILDFIRE_IO IO(WILDFIRE,wildfire)
113 #define DO_PYXIS_IO IO_LITE(CIA,cia_bwx), \
114 .pci_ops = &cia_pci_ops, \
115 .mv_pci_tbi = cia_pci_tbi
117 /*
118 * In a GENERIC kernel, we have lots of these vectors floating about,
119 * all but one of which we want to go away. In a non-GENERIC kernel,
120 * we want only one, ever.
121 *
122 * Accomplish this in the GENERIC kernel by putting all of the vectors
123 * in the .init.data section where they'll go away. We'll copy the
124 * one we want to the real alpha_mv vector in setup_arch.
125 *
126 * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
127 * one of the vectors, which will not reside in .init.data. We then
128 * alias this one vector to alpha_mv, so no copy is needed.
129 *
130 * Upshot: set __initdata to nothing for non-GENERIC kernels.
131 */
133 #ifdef CONFIG_ALPHA_GENERIC
134 #define __initmv __initdata
135 #define ALIAS_MV(x)
136 #else
137 #define __initmv
139 /* GCC actually has a syntax for defining aliases, but is under some
140 delusion that you shouldn't be able to declare it extern somewhere
141 else beforehand. Fine. We'll do it ourselves. */
142 #if 0
143 #define ALIAS_MV(system) \
144 struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv")));
145 #else
146 #define ALIAS_MV(system) \
147 asm(".global alpha_mv\nalpha_mv = " #system "_mv");
148 #endif
149 #endif /* GENERIC */