ia64/linux-2.6.18-xen.hg

view arch/alpha/kernel/core_t2.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 /*
2 * linux/arch/alpha/kernel/core_t2.c
3 *
4 * Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
5 * December 1996.
6 *
7 * based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
8 *
9 * Code common to all T2 core logic chips.
10 */
12 #define __EXTERN_INLINE
13 #include <asm/io.h>
14 #include <asm/core_t2.h>
15 #undef __EXTERN_INLINE
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/init.h>
22 #include <asm/ptrace.h>
23 #include <asm/delay.h>
25 #include "proto.h"
26 #include "pci_impl.h"
28 /* For dumping initial DMA window settings. */
29 #define DEBUG_PRINT_INITIAL_SETTINGS 0
31 /* For dumping final DMA window settings. */
32 #define DEBUG_PRINT_FINAL_SETTINGS 0
34 /*
35 * By default, we direct-map starting at 2GB, in order to allow the
36 * maximum size direct-map window (2GB) to match the maximum amount of
37 * memory (2GB) that can be present on SABLEs. But that limits the
38 * floppy to DMA only via the scatter/gather window set up for 8MB
39 * ISA DMA, since the maximum ISA DMA address is 2GB-1.
40 *
41 * For now, this seems a reasonable trade-off: even though most SABLEs
42 * have less than 1GB of memory, floppy usage/performance will not
43 * really be affected by forcing it to go via scatter/gather...
44 */
45 #define T2_DIRECTMAP_2G 1
47 #if T2_DIRECTMAP_2G
48 # define T2_DIRECTMAP_START 0x80000000UL
49 # define T2_DIRECTMAP_LENGTH 0x80000000UL
50 #else
51 # define T2_DIRECTMAP_START 0x40000000UL
52 # define T2_DIRECTMAP_LENGTH 0x40000000UL
53 #endif
55 /* The ISA scatter/gather window settings. */
56 #define T2_ISA_SG_START 0x00800000UL
57 #define T2_ISA_SG_LENGTH 0x00800000UL
59 /*
60 * NOTE: Herein lie back-to-back mb instructions. They are magic.
61 * One plausible explanation is that the i/o controller does not properly
62 * handle the system transaction. Another involves timing. Ho hum.
63 */
65 /*
66 * BIOS32-style PCI interface:
67 */
69 #define DEBUG_CONFIG 0
71 #if DEBUG_CONFIG
72 # define DBG(args) printk args
73 #else
74 # define DBG(args)
75 #endif
77 static volatile unsigned int t2_mcheck_any_expected;
78 static volatile unsigned int t2_mcheck_last_taken;
80 /* Place to save the DMA Window registers as set up by SRM
81 for restoration during shutdown. */
82 static struct
83 {
84 struct {
85 unsigned long wbase;
86 unsigned long wmask;
87 unsigned long tbase;
88 } window[2];
89 unsigned long hae_1;
90 unsigned long hae_2;
91 unsigned long hae_3;
92 unsigned long hae_4;
93 unsigned long hbase;
94 } t2_saved_config __attribute((common));
96 /*
97 * Given a bus, device, and function number, compute resulting
98 * configuration space address and setup the T2_HAXR2 register
99 * accordingly. It is therefore not safe to have concurrent
100 * invocations to configuration space access routines, but there
101 * really shouldn't be any need for this.
102 *
103 * Type 0:
104 *
105 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
106 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
107 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
108 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
110 *
111 * 31:11 Device select bit.
112 * 10:8 Function number
113 * 7:2 Register number
114 *
115 * Type 1:
116 *
117 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
118 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
119 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
120 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
121 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
122 *
123 * 31:24 reserved
124 * 23:16 bus number (8 bits = 128 possible buses)
125 * 15:11 Device number (5 bits)
126 * 10:8 function number
127 * 7:2 register number
128 *
129 * Notes:
130 * The function number selects which function of a multi-function device
131 * (e.g., SCSI and Ethernet).
132 *
133 * The register selects a DWORD (32 bit) register offset. Hence it
134 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
135 * bits.
136 */
138 static int
139 mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
140 unsigned long *pci_addr, unsigned char *type1)
141 {
142 unsigned long addr;
143 u8 bus = pbus->number;
145 DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
146 " addr=0x%lx, type1=0x%x)\n",
147 bus, device_fn, where, pci_addr, type1));
149 if (bus == 0) {
150 int device = device_fn >> 3;
152 /* Type 0 configuration cycle. */
154 if (device > 8) {
155 DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
156 device));
157 return -1;
158 }
160 *type1 = 0;
161 addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where);
162 } else {
163 /* Type 1 configuration cycle. */
164 *type1 = 1;
165 addr = (bus << 16) | (device_fn << 8) | (where);
166 }
167 *pci_addr = addr;
168 DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
169 return 0;
170 }
172 /*
173 * NOTE: both conf_read() and conf_write() may set HAE_3 when needing
174 * to do type1 access. This is protected by the use of spinlock IRQ
175 * primitives in the wrapper functions pci_{read,write}_config_*()
176 * defined in drivers/pci/pci.c.
177 */
178 static unsigned int
179 conf_read(unsigned long addr, unsigned char type1)
180 {
181 unsigned int value, cpu, taken;
182 unsigned long t2_cfg = 0;
184 cpu = smp_processor_id();
186 DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
188 /* If Type1 access, must set T2 CFG. */
189 if (type1) {
190 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
191 *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
192 mb();
193 }
194 mb();
195 draina();
197 mcheck_expected(cpu) = 1;
198 mcheck_taken(cpu) = 0;
199 t2_mcheck_any_expected |= (1 << cpu);
200 mb();
202 /* Access configuration space. */
203 value = *(vuip)addr;
204 mb();
205 mb(); /* magic */
207 /* Wait for possible mcheck. Also, this lets other CPUs clear
208 their mchecks as well, as they can reliably tell when
209 another CPU is in the midst of handling a real mcheck via
210 the "taken" function. */
211 udelay(100);
213 if ((taken = mcheck_taken(cpu))) {
214 mcheck_taken(cpu) = 0;
215 t2_mcheck_last_taken |= (1 << cpu);
216 value = 0xffffffffU;
217 mb();
218 }
219 mcheck_expected(cpu) = 0;
220 t2_mcheck_any_expected = 0;
221 mb();
223 /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
224 if (type1) {
225 *(vulp)T2_HAE_3 = t2_cfg;
226 mb();
227 }
229 return value;
230 }
232 static void
233 conf_write(unsigned long addr, unsigned int value, unsigned char type1)
234 {
235 unsigned int cpu, taken;
236 unsigned long t2_cfg = 0;
238 cpu = smp_processor_id();
240 /* If Type1 access, must set T2 CFG. */
241 if (type1) {
242 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
243 *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
244 mb();
245 }
246 mb();
247 draina();
249 mcheck_expected(cpu) = 1;
250 mcheck_taken(cpu) = 0;
251 t2_mcheck_any_expected |= (1 << cpu);
252 mb();
254 /* Access configuration space. */
255 *(vuip)addr = value;
256 mb();
257 mb(); /* magic */
259 /* Wait for possible mcheck. Also, this lets other CPUs clear
260 their mchecks as well, as they can reliably tell when
261 this CPU is in the midst of handling a real mcheck via
262 the "taken" function. */
263 udelay(100);
265 if ((taken = mcheck_taken(cpu))) {
266 mcheck_taken(cpu) = 0;
267 t2_mcheck_last_taken |= (1 << cpu);
268 mb();
269 }
270 mcheck_expected(cpu) = 0;
271 t2_mcheck_any_expected = 0;
272 mb();
274 /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
275 if (type1) {
276 *(vulp)T2_HAE_3 = t2_cfg;
277 mb();
278 }
279 }
281 static int
282 t2_read_config(struct pci_bus *bus, unsigned int devfn, int where,
283 int size, u32 *value)
284 {
285 unsigned long addr, pci_addr;
286 unsigned char type1;
287 int shift;
288 long mask;
290 if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
291 return PCIBIOS_DEVICE_NOT_FOUND;
293 mask = (size - 1) * 8;
294 shift = (where & 3) * 8;
295 addr = (pci_addr << 5) + mask + T2_CONF;
296 *value = conf_read(addr, type1) >> (shift);
297 return PCIBIOS_SUCCESSFUL;
298 }
300 static int
301 t2_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
302 u32 value)
303 {
304 unsigned long addr, pci_addr;
305 unsigned char type1;
306 long mask;
308 if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
309 return PCIBIOS_DEVICE_NOT_FOUND;
311 mask = (size - 1) * 8;
312 addr = (pci_addr << 5) + mask + T2_CONF;
313 conf_write(addr, value << ((where & 3) * 8), type1);
314 return PCIBIOS_SUCCESSFUL;
315 }
317 struct pci_ops t2_pci_ops =
318 {
319 .read = t2_read_config,
320 .write = t2_write_config,
321 };
323 static void __init
324 t2_direct_map_window1(unsigned long base, unsigned long length)
325 {
326 unsigned long temp;
328 __direct_map_base = base;
329 __direct_map_size = length;
331 temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
332 *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
333 temp = (length - 1) & 0xfff00000UL;
334 *(vulp)T2_WMASK1 = temp;
335 *(vulp)T2_TBASE1 = 0;
337 #if DEBUG_PRINT_FINAL_SETTINGS
338 printk("%s: setting WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",
339 __FUNCTION__,
340 *(vulp)T2_WBASE1,
341 *(vulp)T2_WMASK1,
342 *(vulp)T2_TBASE1);
343 #endif
344 }
346 static void __init
347 t2_sg_map_window2(struct pci_controller *hose,
348 unsigned long base,
349 unsigned long length)
350 {
351 unsigned long temp;
353 /* Note we can only do 1 SG window, as the other is for direct, so
354 do an ISA SG area, especially for the floppy. */
355 hose->sg_isa = iommu_arena_new(hose, base, length, 0);
356 hose->sg_pci = NULL;
358 temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
359 *(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */
360 temp = (length - 1) & 0xfff00000UL;
361 *(vulp)T2_WMASK2 = temp;
362 *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;
363 mb();
365 t2_pci_tbi(hose, 0, -1); /* flush TLB all */
367 #if DEBUG_PRINT_FINAL_SETTINGS
368 printk("%s: setting WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",
369 __FUNCTION__,
370 *(vulp)T2_WBASE2,
371 *(vulp)T2_WMASK2,
372 *(vulp)T2_TBASE2);
373 #endif
374 }
376 static void __init
377 t2_save_configuration(void)
378 {
379 #if DEBUG_PRINT_INITIAL_SETTINGS
380 printk("%s: HAE_1 was 0x%lx\n", __FUNCTION__, srm_hae); /* HW is 0 */
381 printk("%s: HAE_2 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_2);
382 printk("%s: HAE_3 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_3);
383 printk("%s: HAE_4 was 0x%lx\n", __FUNCTION__, *(vulp)T2_HAE_4);
384 printk("%s: HBASE was 0x%lx\n", __FUNCTION__, *(vulp)T2_HBASE);
386 printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __FUNCTION__,
387 *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
388 printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __FUNCTION__,
389 *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
390 #endif
392 /*
393 * Save the DMA Window registers.
394 */
395 t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;
396 t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;
397 t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;
398 t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;
399 t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;
400 t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;
402 t2_saved_config.hae_1 = srm_hae; /* HW is already set to 0 */
403 t2_saved_config.hae_2 = *(vulp)T2_HAE_2;
404 t2_saved_config.hae_3 = *(vulp)T2_HAE_3;
405 t2_saved_config.hae_4 = *(vulp)T2_HAE_4;
406 t2_saved_config.hbase = *(vulp)T2_HBASE;
407 }
409 void __init
410 t2_init_arch(void)
411 {
412 struct pci_controller *hose;
413 unsigned long temp;
414 unsigned int i;
416 for (i = 0; i < NR_CPUS; i++) {
417 mcheck_expected(i) = 0;
418 mcheck_taken(i) = 0;
419 }
420 t2_mcheck_any_expected = 0;
421 t2_mcheck_last_taken = 0;
423 /* Enable scatter/gather TLB use. */
424 temp = *(vulp)T2_IOCSR;
425 if (!(temp & (0x1UL << 26))) {
426 printk("t2_init_arch: enabling SG TLB, IOCSR was 0x%lx\n",
427 temp);
428 *(vulp)T2_IOCSR = temp | (0x1UL << 26);
429 mb();
430 *(vulp)T2_IOCSR; /* read it back to make sure */
431 }
433 t2_save_configuration();
435 /*
436 * Create our single hose.
437 */
438 pci_isa_hose = hose = alloc_pci_controller();
439 hose->io_space = &ioport_resource;
440 hose->mem_space = &iomem_resource;
441 hose->index = 0;
443 hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR;
444 hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR;
445 hose->sparse_io_base = T2_IO - IDENT_ADDR;
446 hose->dense_io_base = 0;
448 /*
449 * Set up the PCI->physical memory translation windows.
450 *
451 * Window 1 is direct mapped.
452 * Window 2 is scatter/gather (for ISA).
453 */
455 t2_direct_map_window1(T2_DIRECTMAP_START, T2_DIRECTMAP_LENGTH);
457 /* Always make an ISA DMA window. */
458 t2_sg_map_window2(hose, T2_ISA_SG_START, T2_ISA_SG_LENGTH);
460 *(vulp)T2_HBASE = 0x0; /* Disable HOLES. */
462 /* Zero HAE. */
463 *(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */
464 *(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */
465 *(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */
467 /*
468 * We also now zero out HAE_4, the dense memory HAE, so that
469 * we need not account for its "offset" when accessing dense
470 * memory resources which we allocated in our normal way. This
471 * HAE would need to stay untouched were we to keep the SRM
472 * resource settings.
473 *
474 * Thus we can now run standard X servers on SABLE/LYNX. :-)
475 */
476 *(vulp)T2_HAE_4 = 0; mb();
477 }
479 void
480 t2_kill_arch(int mode)
481 {
482 /*
483 * Restore the DMA Window registers.
484 */
485 *(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;
486 *(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;
487 *(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;
488 *(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;
489 *(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;
490 *(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;
491 mb();
493 *(vulp)T2_HAE_1 = srm_hae;
494 *(vulp)T2_HAE_2 = t2_saved_config.hae_2;
495 *(vulp)T2_HAE_3 = t2_saved_config.hae_3;
496 *(vulp)T2_HAE_4 = t2_saved_config.hae_4;
497 *(vulp)T2_HBASE = t2_saved_config.hbase;
498 mb();
499 *(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */
500 }
502 void
503 t2_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
504 {
505 unsigned long t2_iocsr;
507 t2_iocsr = *(vulp)T2_IOCSR;
509 /* set the TLB Clear bit */
510 *(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);
511 mb();
512 *(vulp)T2_IOCSR; /* read it back to make sure */
514 /* clear the TLB Clear bit */
515 *(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);
516 mb();
517 *(vulp)T2_IOCSR; /* read it back to make sure */
518 }
520 #define SIC_SEIC (1UL << 33) /* System Event Clear */
522 static void
523 t2_clear_errors(int cpu)
524 {
525 struct sable_cpu_csr *cpu_regs;
527 cpu_regs = (struct sable_cpu_csr *)T2_CPUn_BASE(cpu);
529 cpu_regs->sic &= ~SIC_SEIC;
531 /* Clear CPU errors. */
532 cpu_regs->bcce |= cpu_regs->bcce;
533 cpu_regs->cbe |= cpu_regs->cbe;
534 cpu_regs->bcue |= cpu_regs->bcue;
535 cpu_regs->dter |= cpu_regs->dter;
537 *(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
538 *(vulp)T2_PERR1 |= *(vulp)T2_PERR1;
540 mb();
541 mb(); /* magic */
542 }
544 /*
545 * SABLE seems to have a "broadcast" style machine check, in that all
546 * CPUs receive it. And, the issuing CPU, in the case of PCI Config
547 * space read/write faults, will also receive a second mcheck, upon
548 * lowering IPL during completion processing in pci_read_config_byte()
549 * et al.
550 *
551 * Hence all the taken/expected/any_expected/last_taken stuff...
552 */
553 void
554 t2_machine_check(unsigned long vector, unsigned long la_ptr,
555 struct pt_regs * regs)
556 {
557 int cpu = smp_processor_id();
558 #ifdef CONFIG_VERBOSE_MCHECK
559 struct el_common *mchk_header = (struct el_common *)la_ptr;
560 #endif
562 /* Clear the error before any reporting. */
563 mb();
564 mb(); /* magic */
565 draina();
566 t2_clear_errors(cpu);
568 /* This should not actually be done until the logout frame is
569 examined, but, since we don't do that, go on and do this... */
570 wrmces(0x7);
571 mb();
573 /* Now, do testing for the anomalous conditions. */
574 if (!mcheck_expected(cpu) && t2_mcheck_any_expected) {
575 /*
576 * FUNKY: Received mcheck on a CPU and not
577 * expecting it, but another CPU is expecting one.
578 *
579 * Just dismiss it for now on this CPU...
580 */
581 #ifdef CONFIG_VERBOSE_MCHECK
582 if (alpha_verbose_mcheck > 1) {
583 printk("t2_machine_check(cpu%d): any_expected 0x%x -"
584 " (assumed) spurious -"
585 " code 0x%x\n", cpu, t2_mcheck_any_expected,
586 (unsigned int)mchk_header->code);
587 }
588 #endif
589 return;
590 }
592 if (!mcheck_expected(cpu) && !t2_mcheck_any_expected) {
593 if (t2_mcheck_last_taken & (1 << cpu)) {
594 #ifdef CONFIG_VERBOSE_MCHECK
595 if (alpha_verbose_mcheck > 1) {
596 printk("t2_machine_check(cpu%d): last_taken 0x%x - "
597 "unexpected mcheck - code 0x%x\n",
598 cpu, t2_mcheck_last_taken,
599 (unsigned int)mchk_header->code);
600 }
601 #endif
602 t2_mcheck_last_taken = 0;
603 mb();
604 return;
605 } else {
606 t2_mcheck_last_taken = 0;
607 mb();
608 }
609 }
611 #ifdef CONFIG_VERBOSE_MCHECK
612 if (alpha_verbose_mcheck > 1) {
613 printk("%s t2_mcheck(cpu%d): last_taken 0x%x - "
614 "any_expected 0x%x - code 0x%x\n",
615 (mcheck_expected(cpu) ? "EX" : "UN"), cpu,
616 t2_mcheck_last_taken, t2_mcheck_any_expected,
617 (unsigned int)mchk_header->code);
618 }
619 #endif
621 process_mcheck_info(vector, la_ptr, regs, "T2", mcheck_expected(cpu));
622 }