ia64/linux-2.6.18-xen.hg

view Documentation/spi/pxa2xx @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
line source
1 PXA2xx SPI on SSP driver HOWTO
2 ===================================================
3 This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
4 synchronous serial port into a SPI master controller
5 (see Documentation/spi/spi_summary). The driver has the following features
7 - Support for any PXA2xx SSP
8 - SSP PIO and SSP DMA data transfers.
9 - External and Internal (SSPFRM) chip selects.
10 - Per slave device (chip) configuration.
11 - Full suspend, freeze, resume support.
13 The driver is built around a "spi_message" fifo serviced by workqueue and a
14 tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
15 (pump_transfer) is responsible for queuing SPI transactions and setting up and
16 launching the dma/interrupt driven transfers.
18 Declaring PXA2xx Master Controllers
19 -----------------------------------
20 Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
21 "platform device". The master configuration is passed to the driver via a table
22 found in include/asm-arm/arch-pxa/pxa2xx_spi.h:
24 struct pxa2xx_spi_master {
25 enum pxa_ssp_type ssp_type;
26 u32 clock_enable;
27 u16 num_chipselect;
28 u8 enable_dma;
29 };
31 The "pxa2xx_spi_master.ssp_type" field must have a value between 1 and 3 and
32 informs the driver which features a particular SSP supports.
34 The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the
35 corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See
36 the "PXA2xx Developer Manual" section "Clocks and Power Management".
38 The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of
39 slave device (chips) attached to this SPI master.
41 The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should
42 be used. This caused the driver to acquire two DMA channels: rx_channel and
43 tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
44 See the "PXA2xx Developer Manual" section "DMA Controller".
46 NSSP MASTER SAMPLE
47 ------------------
48 Below is a sample configuration using the PXA255 NSSP.
50 static struct resource pxa_spi_nssp_resources[] = {
51 [0] = {
52 .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
53 .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
54 .flags = IORESOURCE_MEM,
55 },
56 [1] = {
57 .start = IRQ_NSSP, /* NSSP IRQ */
58 .end = IRQ_NSSP,
59 .flags = IORESOURCE_IRQ,
60 },
61 };
63 static struct pxa2xx_spi_master pxa_nssp_master_info = {
64 .ssp_type = PXA25x_NSSP, /* Type of SSP */
65 .clock_enable = CKEN9_NSSP, /* NSSP Peripheral clock */
66 .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
67 .enable_dma = 1, /* Enables NSSP DMA */
68 };
70 static struct platform_device pxa_spi_nssp = {
71 .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
72 .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
73 .resource = pxa_spi_nssp_resources,
74 .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
75 .dev = {
76 .platform_data = &pxa_nssp_master_info, /* Passed to driver */
77 },
78 };
80 static struct platform_device *devices[] __initdata = {
81 &pxa_spi_nssp,
82 };
84 static void __init board_init(void)
85 {
86 (void)platform_add_device(devices, ARRAY_SIZE(devices));
87 }
89 Declaring Slave Devices
90 -----------------------
91 Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
92 using the "spi_board_info" structure found in "linux/spi/spi.h". See
93 "Documentation/spi/spi_summary" for additional information.
95 Each slave device attached to the PXA must provide slave specific configuration
96 information via the structure "pxa2xx_spi_chip" found in
97 "include/asm-arm/arch-pxa/pxa2xx_spi.h". The pxa2xx_spi master controller driver
98 will uses the configuration whenever the driver communicates with the slave
99 device.
101 struct pxa2xx_spi_chip {
102 u8 tx_threshold;
103 u8 rx_threshold;
104 u8 dma_burst_size;
105 u32 timeout_microsecs;
106 u8 enable_loopback;
107 void (*cs_control)(u32 command);
108 };
110 The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
111 used to configure the SSP hardware fifo. These fields are critical to the
112 performance of pxa2xx_spi driver and misconfiguration will result in rx
113 fifo overruns (especially in PIO mode transfers). Good default values are
115 .tx_threshold = 12,
116 .rx_threshold = 4,
118 The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
119 engine and is related the "spi_device.bits_per_word" field. Read and understand
120 the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
121 to determine the correct value. An SSP configured for byte-wide transfers would
122 use a value of 8.
124 The "pxa2xx_spi_chip.timeout_microsecs" fields is used to efficiently handle
125 trailing bytes in the SSP receiver fifo. The correct value for this field is
126 dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
127 slave device. Please note the the PXA2xx SSP 1 does not support trailing byte
128 timeouts and must busy-wait any trailing bytes.
130 The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
131 into internal loopback mode. In this mode the SSP controller internally
132 connects the SSPTX pin the the SSPRX pin. This is useful for initial setup
133 testing.
135 The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
136 function for asserting/deasserting a slave device chip select. If the field is
137 NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
138 configured to use SSPFRM instead.
140 NSSP SALVE SAMPLE
141 -----------------
142 The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
143 "spi_board_info.controller_data" field. Below is a sample configuration using
144 the PXA255 NSSP.
146 /* Chip Select control for the CS8415A SPI slave device */
147 static void cs8415a_cs_control(u32 command)
148 {
149 if (command & PXA2XX_CS_ASSERT)
150 GPCR(2) = GPIO_bit(2);
151 else
152 GPSR(2) = GPIO_bit(2);
153 }
155 /* Chip Select control for the CS8405A SPI slave device */
156 static void cs8405a_cs_control(u32 command)
157 {
158 if (command & PXA2XX_CS_ASSERT)
159 GPCR(3) = GPIO_bit(3);
160 else
161 GPSR(3) = GPIO_bit(3);
162 }
164 static struct pxa2xx_spi_chip cs8415a_chip_info = {
165 .tx_threshold = 12, /* SSP hardward FIFO threshold */
166 .rx_threshold = 4, /* SSP hardward FIFO threshold */
167 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
168 .timeout_microsecs = 64, /* Wait at least 64usec to handle trailing */
169 .cs_control = cs8415a_cs_control, /* Use external chip select */
170 };
172 static struct pxa2xx_spi_chip cs8405a_chip_info = {
173 .tx_threshold = 12, /* SSP hardward FIFO threshold */
174 .rx_threshold = 4, /* SSP hardward FIFO threshold */
175 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
176 .timeout_microsecs = 64, /* Wait at least 64usec to handle trailing */
177 .cs_control = cs8405a_cs_control, /* Use external chip select */
178 };
180 static struct spi_board_info streetracer_spi_board_info[] __initdata = {
181 {
182 .modalias = "cs8415a", /* Name of spi_driver for this device */
183 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
184 .bus_num = 2, /* Framework bus number */
185 .chip_select = 0, /* Framework chip select */
186 .platform_data = NULL; /* No spi_driver specific config */
187 .controller_data = &cs8415a_chip_info, /* Master chip config */
188 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
189 },
190 {
191 .modalias = "cs8405a", /* Name of spi_driver for this device */
192 .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
193 .bus_num = 2, /* Framework bus number */
194 .chip_select = 1, /* Framework chip select */
195 .controller_data = &cs8405a_chip_info, /* Master chip config */
196 .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
197 },
198 };
200 static void __init streetracer_init(void)
201 {
202 spi_register_board_info(streetracer_spi_board_info,
203 ARRAY_SIZE(streetracer_spi_board_info));
204 }
207 DMA and PIO I/O Support
208 -----------------------
209 The pxa2xx_spi driver support both DMA and interrupt driven PIO message
210 transfers. The driver defaults to PIO mode and DMA transfers must enabled by
211 setting the "enable_dma" flag in the "pxa2xx_spi_master" structure and and
212 ensuring that the "pxa2xx_spi_chip.dma_burst_size" field is non-zero. The DMA
213 mode support both coherent and stream based DMA mappings.
215 The following logic is used to determine the type of I/O to be used on
216 a per "spi_transfer" basis:
218 if !enable_dma or dma_burst_size == 0 then
219 always use PIO transfers
221 if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
222 use coherent DMA mode
224 if rx_buf and tx_buf are aligned on 8 byte boundary then
225 use streaming DMA mode
227 otherwise
228 use PIO transfer
230 THANKS TO
231 ---------
233 David Brownell and others for mentoring the development of this driver.