ia64/linux-2.6.18-xen.hg

view arch/cris/arch-v10/lib/dram_init.S @ 673:3161879fdf22

[IA64] xencomm: support XENMEM_add_to_physmap and XENMEM_remove_from_phsymap

support XENMEM_add_to_physmap and XENMEM_remove_from_phsymap.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Tue Sep 16 21:26:15 2008 +0900 (2008-09-16)
parents 831230e53067
children
line source
1 /* $Id: dram_init.S,v 1.4 2003/09/22 09:21:59 starvik Exp $
2 *
3 * DRAM/SDRAM initialization - alter with care
4 * This file is intended to be included from other assembler files
5 *
6 * Note: This file may not modify r9 because r9 is used to carry
7 * information from the decompresser to the kernel
8 *
9 * Copyright (C) 2000, 2001 Axis Communications AB
10 *
11 * Authors: Mikael Starvik (starvik@axis.com)
12 *
13 * $Log: dram_init.S,v $
14 * Revision 1.4 2003/09/22 09:21:59 starvik
15 * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
16 * so we need to mask off 12 bits.
17 *
18 * Revision 1.3 2003/03/31 09:38:37 starvik
19 * Corrected calculation of end of sdram init commands
20 *
21 * Revision 1.2 2002/11/19 13:33:29 starvik
22 * Changes from Linux 2.4
23 *
24 * Revision 1.13 2002/10/30 07:42:28 starvik
25 * Always read SDRAM command sequence from flash
26 *
27 * Revision 1.12 2002/08/09 11:37:37 orjanf
28 * Added double initialization work-around for Samsung SDRAMs.
29 *
30 * Revision 1.11 2002/06/04 11:43:21 starvik
31 * Check if mrs_data is specified in kernelconfig (necessary for MCM)
32 *
33 * Revision 1.10 2001/10/04 12:00:21 martinnn
34 * Added missing underscores.
35 *
36 * Revision 1.9 2001/10/01 14:47:35 bjornw
37 * Added register prefixes and removed underscores
38 *
39 * Revision 1.8 2001/05/15 07:12:45 hp
40 * Copy warning from head.S about r8 and r9
41 *
42 * Revision 1.7 2001/04/18 12:05:39 bjornw
43 * Fixed comments, and explicitely include config.h to be sure its there
44 *
45 * Revision 1.6 2001/04/10 06:20:16 starvik
46 * Delay should be 200us, not 200ns
47 *
48 * Revision 1.5 2001/04/09 06:01:13 starvik
49 * Added support for 100 MHz SDRAMs
50 *
51 * Revision 1.4 2001/03/26 14:24:01 bjornw
52 * Namechange of some config options
53 *
54 * Revision 1.3 2001/03/23 08:29:41 starvik
55 * Corrected calculation of mrs_data
56 *
57 * Revision 1.2 2001/02/08 15:20:00 starvik
58 * Corrected SDRAM initialization
59 * Should now be included as inline
60 *
61 * Revision 1.1 2001/01/29 13:08:02 starvik
62 * Initial version
63 * This file should be included from all assembler files that needs to
64 * initialize DRAM/SDRAM.
65 *
66 */
68 /* Just to be certain the config file is included, we include it here
69 * explicitely instead of depending on it being included in the file that
70 * uses this code.
71 */
74 ;; WARNING! The registers r8 and r9 are used as parameters carrying
75 ;; information from the decompressor (if the kernel was compressed).
76 ;; They should not be used in the code below.
78 #ifndef CONFIG_SVINTO_SIM
79 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
80 move.d $r0, [R_WAITSTATES]
82 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
83 move.d $r0, [R_BUS_CONFIG]
85 #ifndef CONFIG_ETRAX_SDRAM
86 move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
87 move.d $r0, [R_DRAM_CONFIG]
89 move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
90 move.d $r0, [R_DRAM_TIMING]
91 #else
92 ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
93 moveq 2, $r6
94 _sdram_init:
96 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
98 ; Bank configuration
99 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
100 move.d $r0, [R_SDRAM_CONFIG]
102 ; Calculate value of mrs_data
103 ; CAS latency = 2 && bus_width = 32 => 0x40
104 ; CAS latency = 3 && bus_width = 32 => 0x60
105 ; CAS latency = 2 && bus_width = 16 => 0x20
106 ; CAS latency = 3 && bus_width = 16 => 0x30
108 ; Check if value is already supplied in kernel config
109 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
110 and.d 0x00ff0000, $r2
111 bne _set_timing
112 lsrq 16, $r2
114 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
115 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
116 move.d $r1, $r3
117 and.d 0x03, $r1 ; Get CAS latency
118 and.d 0x1000, $r3 ; 50 or 100 MHz?
119 beq _speed_50
120 nop
121 _speed_100:
122 cmp.d 0x00, $r1 ; CAS latency = 2?
123 beq _bw_check
124 nop
125 or.d 0x20, $r2 ; CAS latency = 3
126 ba _bw_check
127 nop
128 _speed_50:
129 cmp.d 0x01, $r1 ; CAS latency = 2?
130 beq _bw_check
131 nop
132 or.d 0x20, $r2 ; CAS latency = 3
133 _bw_check:
134 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
135 and.d 0x800000, $r1 ; DRAM width is bit 23
136 bne _set_timing
137 nop
138 lsrq 1, $r2 ; 16 bits. Shift down value.
140 ; Set timing parameters. Starts master clock
141 _set_timing:
142 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
143 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
144 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
145 move.d $r1, $r5
146 or.d 0x0000c000, $r1 ; ref = disable
147 lslq 16, $r2 ; mrs data starts at bit 16
148 or.d $r2, $r1
149 move.d $r1, [R_SDRAM_TIMING]
151 ; Wait 200us
152 move.d 10000, $r2
153 1: bne 1b
154 subq 1, $r2
156 ; Issue initialization command sequence
157 move.d _sdram_commands_start, $r2
158 and.d 0x000fffff, $r2 ; Make sure commands are read from flash
159 move.d _sdram_commands_end, $r3
160 and.d 0x000fffff, $r3
161 1: clear.d $r4
162 move.b [$r2+], $r4
163 lslq 9, $r4 ; Command starts at bit 9
164 or.d $r1, $r4
165 move.d $r4, [R_SDRAM_TIMING]
166 nop ; Wait five nop cycles between each command
167 nop
168 nop
169 nop
170 nop
171 cmp.d $r2, $r3
172 bne 1b
173 nop
174 move.d $r5, [R_SDRAM_TIMING]
175 subq 1, $r6
176 bne _sdram_init
177 nop
178 ba _sdram_commands_end
179 nop
181 _sdram_commands_start:
182 .byte 3 ; Precharge
183 .byte 0 ; nop
184 .byte 2 ; refresh
185 .byte 0 ; nop
186 .byte 2 ; refresh
187 .byte 0 ; nop
188 .byte 2 ; refresh
189 .byte 0 ; nop
190 .byte 2 ; refresh
191 .byte 0 ; nop
192 .byte 2 ; refresh
193 .byte 0 ; nop
194 .byte 2 ; refresh
195 .byte 0 ; nop
196 .byte 2 ; refresh
197 .byte 0 ; nop
198 .byte 2 ; refresh
199 .byte 0 ; nop
200 .byte 1 ; mrs
201 .byte 0 ; nop
202 _sdram_commands_end:
203 #endif
204 #endif