ia64/linux-2.6.18-xen.hg

view drivers/pci/quirks.c @ 696:2b5cc22ab406

xen/dom0: Reassign memory resources to device for pci passthrough.

This patch adds the function that reassign page-aligned memory
resources, to dom0 linux. The function is useful when we assign I/O
device to HVM domain using pci passthrough.

When we assign a device to HVM domain using pci passthrough,
the device needs to be assigned page-aligned memory resources. If the
memory resource is not page-aligned, following error occurs.

Error: pci: 0000:00:1d.7: non-page-aligned MMIO BAR found.

On many system, BIOS assigns memory resources to the device and
enables it. So my patch disables the device, and releases resources,
Then it assigns page-aligned memory resource to the device.

To reassign resources, please add boot parameters of dom0 linux as
follows.

reassign_resources reassigndev=00:1d.7,01:00.0

reassign_resources
Enables reassigning resources.

reassigndev= Specifies devices include I/O device and
PCI-PCI
bridge to reassign resources. PCI-PCI bridge
can be specified, if resource windows need to
be expanded.

Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Oct 09 11:10:43 2008 +0100 (2008-10-09)
parents 1e8c3287b395
children 8fbf8e2fd087
line source
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include "pci.h"
26 /* A global flag which signals if we should page-align PCI mem windows. */
27 int pci_mem_align = 0;
29 static int __init set_pci_mem_align(char *str)
30 {
31 pci_mem_align = 1;
32 return 1;
33 }
34 __setup("pci-mem-align", set_pci_mem_align);
37 int reassign_resources = 0;
39 static int __init set_reassign_resources(char *str)
40 {
41 /* resources reassign on */
42 reassign_resources = 1;
43 printk(KERN_DEBUG "PCI: resource reassign ON.\n");
45 return 1;
46 }
47 __setup("reassign_resources", set_reassign_resources);
49 /* This quirk function enables us to force all memory resources which are
50 * assigned to PCI devices, to be page-aligned.
51 */
52 static void __devinit quirk_align_mem_resources(struct pci_dev *dev)
53 {
54 int i;
55 struct resource *r;
56 resource_size_t old_start;
58 if (reassign_resources) {
59 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
60 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
61 /* PCI Host Bridge isn't a target device */
62 return;
63 }
64 if (is_reassigndev(dev)) {
65 printk(KERN_INFO
66 "PCI: Disable device and release resources"
67 " [%s].\n", pci_name(dev));
68 pci_disable_device(dev);
70 for (i=0; i < PCI_NUM_RESOURCES; i++) {
71 r = &dev->resource[i];
72 if ((r == NULL) ||
73 !(r->flags & IORESOURCE_MEM))
74 continue;
76 r->end = r->end - r->start;
77 r->start = 0;
79 if (i < PCI_BRIDGE_RESOURCES) {
80 pci_update_resource(dev, r, i);
81 } else if (i == 8 || i == 9) {
82 /* need to update(clear) the Base/Limit
83 * register also, because PCI bridge is
84 * disabled and the resource is
85 * released.
86 */
87 pci_update_bridge(dev, i);
88 }
89 }
90 }
91 return;
92 }
94 if (!pci_mem_align)
95 return;
97 for (i=0; i < DEVICE_COUNT_RESOURCE; i++) {
98 r = &dev->resource[i];
99 if ((r == NULL) || !(r->flags & IORESOURCE_MEM))
100 continue;
102 old_start = r->start;
103 r->start = (r->start + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
104 r->end = r->end - (old_start - r->start);
105 }
106 }
107 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_align_mem_resources);
109 /* The Mellanox Tavor device gives false positive parity errors
110 * Mark this device with a broken_parity_status, to allow
111 * PCI scanning code to "skip" this now blacklisted device.
112 */
113 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
114 {
115 dev->broken_parity_status = 1; /* This device gives false positives */
116 }
117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
120 /* Deal with broken BIOS'es that neglect to enable passive release,
121 which can cause problems in combination with the 82441FX/PPro MTRRs */
122 static void __devinit quirk_passive_release(struct pci_dev *dev)
123 {
124 struct pci_dev *d = NULL;
125 unsigned char dlc;
127 /* We have to make sure a particular bit is set in the PIIX3
128 ISA bridge, so we have to go out and find it. */
129 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
130 pci_read_config_byte(d, 0x82, &dlc);
131 if (!(dlc & 1<<1)) {
132 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
133 dlc |= 1<<1;
134 pci_write_config_byte(d, 0x82, dlc);
135 }
136 }
137 }
138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
140 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
141 but VIA don't answer queries. If you happen to have good contacts at VIA
142 ask them for me please -- Alan
144 This appears to be BIOS not version dependent. So presumably there is a
145 chipset level fix */
146 int isa_dma_bridge_buggy; /* Exported */
148 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
149 {
150 if (!isa_dma_bridge_buggy) {
151 isa_dma_bridge_buggy=1;
152 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
153 }
154 }
155 /*
156 * Its not totally clear which chipsets are the problematic ones
157 * We know 82C586 and 82C596 variants are affected.
158 */
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
167 int pci_pci_problems;
169 /*
170 * Chipsets where PCI->PCI transfers vanish or hang
171 */
172 static void __devinit quirk_nopcipci(struct pci_dev *dev)
173 {
174 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
175 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
176 pci_pci_problems |= PCIPCI_FAIL;
177 }
178 }
179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
182 /*
183 * Triton requires workarounds to be used by the drivers
184 */
185 static void __devinit quirk_triton(struct pci_dev *dev)
186 {
187 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
188 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
189 pci_pci_problems |= PCIPCI_TRITON;
190 }
191 }
192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
197 /*
198 * VIA Apollo KT133 needs PCI latency patch
199 * Made according to a windows driver based patch by George E. Breese
200 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
201 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
202 * the info on which Mr Breese based his work.
203 *
204 * Updated based on further information from the site and also on
205 * information provided by VIA
206 */
207 static void __devinit quirk_vialatency(struct pci_dev *dev)
208 {
209 struct pci_dev *p;
210 u8 rev;
211 u8 busarb;
212 /* Ok we have a potential problem chipset here. Now see if we have
213 a buggy southbridge */
215 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
216 if (p!=NULL) {
217 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
218 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
219 /* Check for buggy part revisions */
220 if (rev < 0x40 || rev > 0x42)
221 goto exit;
222 } else {
223 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
224 if (p==NULL) /* No problem parts */
225 goto exit;
226 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
227 /* Check for buggy part revisions */
228 if (rev < 0x10 || rev > 0x12)
229 goto exit;
230 }
232 /*
233 * Ok we have the problem. Now set the PCI master grant to
234 * occur every master grant. The apparent bug is that under high
235 * PCI load (quite common in Linux of course) you can get data
236 * loss when the CPU is held off the bus for 3 bus master requests
237 * This happens to include the IDE controllers....
238 *
239 * VIA only apply this fix when an SB Live! is present but under
240 * both Linux and Windows this isnt enough, and we have seen
241 * corruption without SB Live! but with things like 3 UDMA IDE
242 * controllers. So we ignore that bit of the VIA recommendation..
243 */
245 pci_read_config_byte(dev, 0x76, &busarb);
246 /* Set bit 4 and bi 5 of byte 76 to 0x01
247 "Master priority rotation on every PCI master grant */
248 busarb &= ~(1<<5);
249 busarb |= (1<<4);
250 pci_write_config_byte(dev, 0x76, busarb);
251 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
252 exit:
253 pci_dev_put(p);
254 }
255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
259 /*
260 * VIA Apollo VP3 needs ETBF on BT848/878
261 */
262 static void __devinit quirk_viaetbf(struct pci_dev *dev)
263 {
264 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
265 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
266 pci_pci_problems |= PCIPCI_VIAETBF;
267 }
268 }
269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
271 static void __devinit quirk_vsfx(struct pci_dev *dev)
272 {
273 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
274 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
275 pci_pci_problems |= PCIPCI_VSFX;
276 }
277 }
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
280 /*
281 * Ali Magik requires workarounds to be used by the drivers
282 * that DMA to AGP space. Latency must be set to 0xA and triton
283 * workaround applied too
284 * [Info kindly provided by ALi]
285 */
286 static void __init quirk_alimagik(struct pci_dev *dev)
287 {
288 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
289 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
290 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
291 }
292 }
293 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
296 /*
297 * Natoma has some interesting boundary conditions with Zoran stuff
298 * at least
299 */
300 static void __devinit quirk_natoma(struct pci_dev *dev)
301 {
302 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
303 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
304 pci_pci_problems |= PCIPCI_NATOMA;
305 }
306 }
307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
314 /*
315 * This chip can cause PCI parity errors if config register 0xA0 is read
316 * while DMAs are occurring.
317 */
318 static void __devinit quirk_citrine(struct pci_dev *dev)
319 {
320 dev->cfg_size = 0xA0;
321 }
322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
324 /*
325 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
326 * If it's needed, re-allocate the region.
327 */
328 static void __devinit quirk_s3_64M(struct pci_dev *dev)
329 {
330 struct resource *r = &dev->resource[0];
332 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
333 r->start = 0;
334 r->end = 0x3ffffff;
335 }
336 }
337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
340 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
341 unsigned size, int nr, const char *name)
342 {
343 region &= ~(size-1);
344 if (region) {
345 struct pci_bus_region bus_region;
346 struct resource *res = dev->resource + nr;
348 res->name = pci_name(dev);
349 res->start = region;
350 res->end = region + size - 1;
351 res->flags = IORESOURCE_IO;
353 /* Convert from PCI bus to resource space. */
354 bus_region.start = res->start;
355 bus_region.end = res->end;
356 pcibios_bus_to_resource(dev, res, &bus_region);
358 pci_claim_resource(dev, nr);
359 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
360 }
361 }
363 /*
364 * ATI Northbridge setups MCE the processor if you even
365 * read somewhere between 0x3b0->0x3bb or read 0x3d3
366 */
367 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
368 {
369 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
370 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
371 request_region(0x3b0, 0x0C, "RadeonIGP");
372 request_region(0x3d3, 0x01, "RadeonIGP");
373 }
374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
376 /*
377 * Let's make the southbridge information explicit instead
378 * of having to worry about people probing the ACPI areas,
379 * for example.. (Yes, it happens, and if you read the wrong
380 * ACPI register it will put the machine to sleep with no
381 * way of waking it up again. Bummer).
382 *
383 * ALI M7101: Two IO regions pointed to by words at
384 * 0xE0 (64 bytes of ACPI registers)
385 * 0xE2 (32 bytes of SMB registers)
386 */
387 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
388 {
389 u16 region;
391 pci_read_config_word(dev, 0xE0, &region);
392 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
393 pci_read_config_word(dev, 0xE2, &region);
394 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
395 }
396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
398 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
399 {
400 u32 devres;
401 u32 mask, size, base;
403 pci_read_config_dword(dev, port, &devres);
404 if ((devres & enable) != enable)
405 return;
406 mask = (devres >> 16) & 15;
407 base = devres & 0xffff;
408 size = 16;
409 for (;;) {
410 unsigned bit = size >> 1;
411 if ((bit & mask) == bit)
412 break;
413 size = bit;
414 }
415 /*
416 * For now we only print it out. Eventually we'll want to
417 * reserve it (at least if it's in the 0x1000+ range), but
418 * let's get enough confirmation reports first.
419 */
420 base &= -size;
421 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
422 }
424 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
425 {
426 u32 devres;
427 u32 mask, size, base;
429 pci_read_config_dword(dev, port, &devres);
430 if ((devres & enable) != enable)
431 return;
432 base = devres & 0xffff0000;
433 mask = (devres & 0x3f) << 16;
434 size = 128 << 16;
435 for (;;) {
436 unsigned bit = size >> 1;
437 if ((bit & mask) == bit)
438 break;
439 size = bit;
440 }
441 /*
442 * For now we only print it out. Eventually we'll want to
443 * reserve it, but let's get enough confirmation reports first.
444 */
445 base &= -size;
446 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
447 }
449 /*
450 * PIIX4 ACPI: Two IO regions pointed to by longwords at
451 * 0x40 (64 bytes of ACPI registers)
452 * 0x90 (16 bytes of SMB registers)
453 * and a few strange programmable PIIX4 device resources.
454 */
455 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
456 {
457 u32 region, res_a;
459 pci_read_config_dword(dev, 0x40, &region);
460 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
461 pci_read_config_dword(dev, 0x90, &region);
462 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
464 /* Device resource A has enables for some of the other ones */
465 pci_read_config_dword(dev, 0x5c, &res_a);
467 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
468 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
470 /* Device resource D is just bitfields for static resources */
472 /* Device 12 enabled? */
473 if (res_a & (1 << 29)) {
474 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
475 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
476 }
477 /* Device 13 enabled? */
478 if (res_a & (1 << 30)) {
479 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
480 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
481 }
482 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
483 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
484 }
485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
488 /*
489 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
490 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
491 * 0x58 (64 bytes of GPIO I/O space)
492 */
493 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
494 {
495 u32 region;
497 pci_read_config_dword(dev, 0x40, &region);
498 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
500 pci_read_config_dword(dev, 0x58, &region);
501 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
502 }
503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
514 static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
515 {
516 u32 region;
518 pci_read_config_dword(dev, 0x40, &region);
519 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
521 pci_read_config_dword(dev, 0x48, &region);
522 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
523 }
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
527 /*
528 * VIA ACPI: One IO region pointed to by longword at
529 * 0x48 or 0x20 (256 bytes of ACPI registers)
530 */
531 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
532 {
533 u8 rev;
534 u32 region;
536 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
537 if (rev & 0x10) {
538 pci_read_config_dword(dev, 0x48, &region);
539 region &= PCI_BASE_ADDRESS_IO_MASK;
540 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
541 }
542 }
543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
545 /*
546 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
547 * 0x48 (256 bytes of ACPI registers)
548 * 0x70 (128 bytes of hardware monitoring register)
549 * 0x90 (16 bytes of SMB registers)
550 */
551 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
552 {
553 u16 hm;
554 u32 smb;
556 quirk_vt82c586_acpi(dev);
558 pci_read_config_word(dev, 0x70, &hm);
559 hm &= PCI_BASE_ADDRESS_IO_MASK;
560 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
562 pci_read_config_dword(dev, 0x90, &smb);
563 smb &= PCI_BASE_ADDRESS_IO_MASK;
564 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
565 }
566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
568 /*
569 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
570 * 0x88 (128 bytes of power management registers)
571 * 0xd0 (16 bytes of SMB registers)
572 */
573 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
574 {
575 u16 pm, smb;
577 pci_read_config_word(dev, 0x88, &pm);
578 pm &= PCI_BASE_ADDRESS_IO_MASK;
579 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
581 pci_read_config_word(dev, 0xd0, &smb);
582 smb &= PCI_BASE_ADDRESS_IO_MASK;
583 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
584 }
585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
588 #ifdef CONFIG_X86_IO_APIC
590 #include <asm/io_apic.h>
592 /*
593 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
594 * devices to the external APIC.
595 *
596 * TODO: When we have device-specific interrupt routers,
597 * this code will go away from quirks.
598 */
599 static void __devinit quirk_via_ioapic(struct pci_dev *dev)
600 {
601 u8 tmp;
603 if (nr_ioapics < 1)
604 tmp = 0; /* nothing routed to external APIC */
605 else
606 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
608 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
609 tmp == 0 ? "Disa" : "Ena");
611 /* Offset 0x58: External APIC IRQ output control */
612 pci_write_config_byte (dev, 0x58, tmp);
613 }
614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
616 /*
617 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
618 * This leads to doubled level interrupt rates.
619 * Set this bit to get rid of cycle wastage.
620 * Otherwise uncritical.
621 */
622 static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
623 {
624 u8 misc_control2;
625 #define BYPASS_APIC_DEASSERT 8
627 pci_read_config_byte(dev, 0x5B, &misc_control2);
628 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
629 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
630 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
631 }
632 }
633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
635 /*
636 * The AMD io apic can hang the box when an apic irq is masked.
637 * We check all revs >= B0 (yet not in the pre production!) as the bug
638 * is currently marked NoFix
639 *
640 * We have multiple reports of hangs with this chipset that went away with
641 * noapic specified. For the moment we assume its the errata. We may be wrong
642 * of course. However the advice is demonstrably good even if so..
643 */
644 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
645 {
646 u8 rev;
648 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
649 if (rev >= 0x02) {
650 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
651 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
652 }
653 }
654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
656 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
657 {
658 if (dev->devfn == 0 && dev->bus->number == 0)
659 sis_apic_bug = 1;
660 }
661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
663 int pci_msi_quirk;
665 #define AMD8131_revA0 0x01
666 #define AMD8131_revB0 0x11
667 #define AMD8131_MISC 0x40
668 #define AMD8131_NIOAMODE_BIT 0
669 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
670 {
671 unsigned char revid, tmp;
673 if (dev->subordinate) {
674 printk(KERN_WARNING "PCI: MSI quirk detected. "
675 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n");
676 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
677 }
679 if (nr_ioapics == 0)
680 return;
682 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
683 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
684 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
685 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
686 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
687 pci_write_config_byte( dev, AMD8131_MISC, tmp);
688 }
689 }
690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
692 static void __init quirk_svw_msi(struct pci_dev *dev)
693 {
694 pci_msi_quirk = 1;
695 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
696 }
697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
698 #endif /* CONFIG_X86_IO_APIC */
701 /*
702 * FIXME: it is questionable that quirk_via_acpi
703 * is needed. It shows up as an ISA bridge, and does not
704 * support the PCI_INTERRUPT_LINE register at all. Therefore
705 * it seems like setting the pci_dev's 'irq' to the
706 * value of the ACPI SCI interrupt is only done for convenience.
707 * -jgarzik
708 */
709 static void __devinit quirk_via_acpi(struct pci_dev *d)
710 {
711 /*
712 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
713 */
714 u8 irq;
715 pci_read_config_byte(d, 0x42, &irq);
716 irq &= 0xf;
717 if (irq && (irq != 2))
718 d->irq = irq;
719 }
720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
723 /*
724 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
725 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
726 * when written, it makes an internal connection to the PIC.
727 * For these devices, this register is defined to be 4 bits wide.
728 * Normally this is fine. However for IO-APIC motherboards, or
729 * non-x86 architectures (yes Via exists on PPC among other places),
730 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
731 * interrupts delivered properly.
732 *
733 * Some of the on-chip devices are actually '586 devices' so they are
734 * listed here.
735 */
736 static void quirk_via_irq(struct pci_dev *dev)
737 {
738 u8 irq, new_irq;
740 new_irq = dev->irq & 0xf;
741 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
742 if (new_irq != irq) {
743 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
744 pci_name(dev), irq, new_irq);
745 udelay(15); /* unknown if delay really needed */
746 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
747 }
748 }
749 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq);
750 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq);
751 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq);
752 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq);
753 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, quirk_via_irq);
754 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
755 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
756 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
758 /*
759 * VIA VT82C598 has its device ID settable and many BIOSes
760 * set it to the ID of VT82C597 for backward compatibility.
761 * We need to switch it off to be able to recognize the real
762 * type of the chip.
763 */
764 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
765 {
766 pci_write_config_byte(dev, 0xfc, 0);
767 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
768 }
769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
771 /*
772 * CardBus controllers have a legacy base address that enables them
773 * to respond as i82365 pcmcia controllers. We don't want them to
774 * do this even if the Linux CardBus driver is not loaded, because
775 * the Linux i82365 driver does not (and should not) handle CardBus.
776 */
777 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
778 {
779 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
780 return;
781 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
782 }
783 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
785 /*
786 * Following the PCI ordering rules is optional on the AMD762. I'm not
787 * sure what the designers were smoking but let's not inhale...
788 *
789 * To be fair to AMD, it follows the spec by default, its BIOS people
790 * who turn it off!
791 */
792 static void __devinit quirk_amd_ordering(struct pci_dev *dev)
793 {
794 u32 pcic;
795 pci_read_config_dword(dev, 0x4C, &pcic);
796 if ((pcic&6)!=6) {
797 pcic |= 6;
798 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
799 pci_write_config_dword(dev, 0x4C, pcic);
800 pci_read_config_dword(dev, 0x84, &pcic);
801 pcic |= (1<<23); /* Required in this mode */
802 pci_write_config_dword(dev, 0x84, pcic);
803 }
804 }
805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
807 /*
808 * DreamWorks provided workaround for Dunord I-3000 problem
809 *
810 * This card decodes and responds to addresses not apparently
811 * assigned to it. We force a larger allocation to ensure that
812 * nothing gets put too close to it.
813 */
814 static void __devinit quirk_dunord ( struct pci_dev * dev )
815 {
816 struct resource *r = &dev->resource [1];
817 r->start = 0;
818 r->end = 0xffffff;
819 }
820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
822 /*
823 * i82380FB mobile docking controller: its PCI-to-PCI bridge
824 * is subtractive decoding (transparent), and does indicate this
825 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
826 * instead of 0x01.
827 */
828 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
829 {
830 dev->transparent = 1;
831 }
832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
835 /*
836 * Common misconfiguration of the MediaGX/Geode PCI master that will
837 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
838 * datasheets found at http://www.national.com/ds/GX for info on what
839 * these bits do. <christer@weinigel.se>
840 */
841 static void __init quirk_mediagx_master(struct pci_dev *dev)
842 {
843 u8 reg;
844 pci_read_config_byte(dev, 0x41, &reg);
845 if (reg & 2) {
846 reg &= ~2;
847 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
848 pci_write_config_byte(dev, 0x41, reg);
849 }
850 }
851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
853 /*
854 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
855 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
856 * secondary channels respectively). If the device reports Compatible mode
857 * but does use BAR0-3 for address decoding, we assume that firmware has
858 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
859 * Exceptions (if they exist) must be handled in chip/architecture specific
860 * fixups.
861 *
862 * Note: for non x86 people. You may need an arch specific quirk to handle
863 * moving IDE devices to native mode as well. Some plug in card devices power
864 * up in compatible mode and assume the BIOS will adjust them.
865 *
866 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
867 * we do now ? We don't want is pci_enable_device to come along
868 * and assign new resources. Both approaches work for that.
869 */
870 static void __devinit quirk_ide_bases(struct pci_dev *dev)
871 {
872 struct resource *res;
873 int first_bar = 2, last_bar = 0;
875 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
876 return;
878 res = &dev->resource[0];
880 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
881 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
882 res[0].start = res[0].end = res[0].flags = 0;
883 res[1].start = res[1].end = res[1].flags = 0;
884 first_bar = 0;
885 last_bar = 1;
886 }
888 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
889 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
890 res[2].start = res[2].end = res[2].flags = 0;
891 res[3].start = res[3].end = res[3].flags = 0;
892 last_bar = 3;
893 }
895 if (!last_bar)
896 return;
898 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
899 first_bar, last_bar, pci_name(dev));
900 }
901 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
903 /*
904 * Ensure C0 rev restreaming is off. This is normally done by
905 * the BIOS but in the odd case it is not the results are corruption
906 * hence the presence of a Linux check
907 */
908 static void __init quirk_disable_pxb(struct pci_dev *pdev)
909 {
910 u16 config;
911 u8 rev;
913 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
914 if (rev != 0x04) /* Only C0 requires this */
915 return;
916 pci_read_config_word(pdev, 0x40, &config);
917 if (config & (1<<6)) {
918 config &= ~(1<<6);
919 pci_write_config_word(pdev, 0x40, config);
920 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
921 }
922 }
923 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
925 static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
926 {
927 /* set sb600/sb700/sb800 sata to ahci mode */
928 u8 tmp;
930 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
931 if (tmp == 0x01) {
932 pci_read_config_byte(pdev, 0x40, &tmp);
933 pci_write_config_byte(pdev, 0x40, tmp|1);
934 pci_write_config_byte(pdev, 0x9, 1);
935 pci_write_config_byte(pdev, 0xa, 6);
936 pci_write_config_byte(pdev, 0x40, tmp);
938 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
939 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
940 }
941 }
942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata);
943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata);
945 /*
946 * Serverworks CSB5 IDE does not fully support native mode
947 */
948 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
949 {
950 u8 prog;
951 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
952 if (prog & 5) {
953 prog &= ~5;
954 pdev->class &= ~5;
955 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
956 /* need to re-assign BARs for compat mode */
957 quirk_ide_bases(pdev);
958 }
959 }
960 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
962 /*
963 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
964 */
965 static void __init quirk_ide_samemode(struct pci_dev *pdev)
966 {
967 u8 prog;
969 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
971 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
972 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
973 prog &= ~5;
974 pdev->class &= ~5;
975 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
976 /* need to re-assign BARs for compat mode */
977 quirk_ide_bases(pdev);
978 }
979 }
980 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
982 /* This was originally an Alpha specific thing, but it really fits here.
983 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
984 */
985 static void __init quirk_eisa_bridge(struct pci_dev *dev)
986 {
987 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
988 }
989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
991 /*
992 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
993 * when a PCI-Soundcard is added. The BIOS only gives Options
994 * "Disabled" and "AUTO". This Quirk Sets the corresponding
995 * Register-Value to enable the Soundcard.
996 *
997 * FIXME: Presently this quirk will run on anything that has an 8237
998 * which isn't correct, we need to check DMI tables or something in
999 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
1000 * runs everywhere at present we suppress the printk output in most
1001 * irrelevant cases.
1002 */
1003 static void __init k8t_sound_hostbridge(struct pci_dev *dev)
1005 unsigned char val;
1007 pci_read_config_byte(dev, 0x50, &val);
1008 if (val == 0x88 || val == 0xc8) {
1009 /* Assume it's probably a MSI-K8T-Neo2Fir */
1010 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
1011 pci_write_config_byte(dev, 0x50, val & (~0x40));
1013 /* Verify the Change for Status output */
1014 pci_read_config_byte(dev, 0x50, &val);
1015 if (val & 0x40)
1016 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
1017 else
1018 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
1023 #ifndef CONFIG_ACPI_SLEEP
1024 /*
1025 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1026 * is not activated. The myth is that Asus said that they do not want the
1027 * users to be irritated by just another PCI Device in the Win98 device
1028 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1029 * package 2.7.0 for details)
1031 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1032 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1033 * becomes necessary to do this tweak in two steps -- I've chosen the Host
1034 * bridge as trigger.
1036 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
1037 * will cause thermal management to break down, and causing machine to
1038 * overheat.
1039 */
1040 static int __initdata asus_hides_smbus;
1042 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1044 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1045 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1046 switch(dev->subsystem_device) {
1047 case 0x8025: /* P4B-LX */
1048 case 0x8070: /* P4B */
1049 case 0x8088: /* P4B533 */
1050 case 0x1626: /* L3C notebook */
1051 asus_hides_smbus = 1;
1053 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1054 switch(dev->subsystem_device) {
1055 case 0x80b1: /* P4GE-V */
1056 case 0x80b2: /* P4PE */
1057 case 0x8093: /* P4B533-V */
1058 asus_hides_smbus = 1;
1060 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1061 switch(dev->subsystem_device) {
1062 case 0x8030: /* P4T533 */
1063 asus_hides_smbus = 1;
1065 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1066 switch (dev->subsystem_device) {
1067 case 0x8070: /* P4G8X Deluxe */
1068 asus_hides_smbus = 1;
1070 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1071 switch (dev->subsystem_device) {
1072 case 0x80c9: /* PU-DLS */
1073 asus_hides_smbus = 1;
1075 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1076 switch (dev->subsystem_device) {
1077 case 0x1751: /* M2N notebook */
1078 case 0x1821: /* M5N notebook */
1079 asus_hides_smbus = 1;
1081 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1082 switch (dev->subsystem_device) {
1083 case 0x184b: /* W1N notebook */
1084 case 0x186a: /* M6Ne notebook */
1085 asus_hides_smbus = 1;
1087 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1088 switch (dev->subsystem_device) {
1089 case 0x1882: /* M6V notebook */
1090 case 0x1977: /* A6VA notebook */
1091 asus_hides_smbus = 1;
1094 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1095 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1096 switch(dev->subsystem_device) {
1097 case 0x088C: /* HP Compaq nc8000 */
1098 case 0x0890: /* HP Compaq nc6000 */
1099 asus_hides_smbus = 1;
1101 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1102 switch (dev->subsystem_device) {
1103 case 0x12bc: /* HP D330L */
1104 case 0x12bd: /* HP D530 */
1105 asus_hides_smbus = 1;
1107 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1108 switch (dev->subsystem_device) {
1109 case 0x099c: /* HP Compaq nx6110 */
1110 asus_hides_smbus = 1;
1113 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1114 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1115 switch(dev->subsystem_device) {
1116 case 0x0001: /* Toshiba Satellite A40 */
1117 asus_hides_smbus = 1;
1119 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1120 switch(dev->subsystem_device) {
1121 case 0x0001: /* Toshiba Tecra M2 */
1122 asus_hides_smbus = 1;
1124 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1125 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1126 switch(dev->subsystem_device) {
1127 case 0xC00C: /* Samsung P35 notebook */
1128 asus_hides_smbus = 1;
1130 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1131 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1132 switch(dev->subsystem_device) {
1133 case 0x0058: /* Compaq Evo N620c */
1134 asus_hides_smbus = 1;
1138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
1146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1148 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1150 u16 val;
1152 if (likely(!asus_hides_smbus))
1153 return;
1155 pci_read_config_word(dev, 0xF2, &val);
1156 if (val & 0x8) {
1157 pci_write_config_word(dev, 0xF2, val & (~0x8));
1158 pci_read_config_word(dev, 0xF2, &val);
1159 if (val & 0x8)
1160 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1161 else
1162 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1172 static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1174 u32 val, rcba;
1175 void __iomem *base;
1177 if (likely(!asus_hides_smbus))
1178 return;
1179 pci_read_config_dword(dev, 0xF0, &rcba);
1180 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1181 if (base == NULL) return;
1182 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1183 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1184 iounmap(base);
1185 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1189 #endif
1191 /*
1192 * SiS 96x south bridge: BIOS typically hides SMBus device...
1193 */
1194 static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1196 u8 val = 0;
1197 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1198 pci_read_config_byte(dev, 0x77, &val);
1199 pci_write_config_byte(dev, 0x77, val & ~0x10);
1200 pci_read_config_byte(dev, 0x77, &val);
1203 /*
1204 * ... This is further complicated by the fact that some SiS96x south
1205 * bridges pretend to be 85C503/5513 instead. In that case see if we
1206 * spotted a compatible north bridge to make sure.
1207 * (pci_find_device doesn't work yet)
1209 * We can also enable the sis96x bit in the discovery register..
1210 */
1211 static int __devinitdata sis_96x_compatible = 0;
1213 #define SIS_DETECT_REGISTER 0x40
1215 static void __init quirk_sis_503(struct pci_dev *dev)
1217 u8 reg;
1218 u16 devid;
1220 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1221 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1222 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1223 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1224 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1225 return;
1228 /* Make people aware that we changed the config.. */
1229 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1231 /*
1232 * Ok, it now shows up as a 96x.. The 96x quirks are after
1233 * the 503 quirk in the quirk table, so they'll automatically
1234 * run and enable things like the SMBus device
1235 */
1236 dev->device = devid;
1239 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1241 sis_96x_compatible = 1;
1243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1251 /*
1252 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1253 * and MC97 modem controller are disabled when a second PCI soundcard is
1254 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1255 * -- bjd
1256 */
1257 static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1259 u8 val;
1260 int asus_hides_ac97 = 0;
1262 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1263 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1264 asus_hides_ac97 = 1;
1267 if (!asus_hides_ac97)
1268 return;
1270 pci_read_config_byte(dev, 0x50, &val);
1271 if (val & 0xc0) {
1272 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1273 pci_read_config_byte(dev, 0x50, &val);
1274 if (val & 0xc0)
1275 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1276 else
1277 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1288 #if defined(CONFIG_SCSI_SATA) || defined(CONFIG_SCSI_SATA_MODULE)
1290 /*
1291 * If we are using libata we can drive this chip properly but must
1292 * do this early on to make the additional device appear during
1293 * the PCI scanning.
1294 */
1296 static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev)
1298 u32 conf;
1299 u8 hdr;
1301 /* Only poke fn 0 */
1302 if (PCI_FUNC(pdev->devfn))
1303 return;
1305 switch(pdev->device) {
1306 case PCI_DEVICE_ID_JMICRON_JMB365:
1307 case PCI_DEVICE_ID_JMICRON_JMB366:
1308 /* Redirect IDE second PATA port to the right spot */
1309 pci_read_config_dword(pdev, 0x80, &conf);
1310 conf |= (1 << 24);
1311 /* Fall through */
1312 pci_write_config_dword(pdev, 0x80, conf);
1313 case PCI_DEVICE_ID_JMICRON_JMB361:
1314 case PCI_DEVICE_ID_JMICRON_JMB363:
1315 pci_read_config_dword(pdev, 0x40, &conf);
1316 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1317 /* Set the class codes correctly and then direct IDE 0 */
1318 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */
1319 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1320 pci_write_config_dword(pdev, 0x40, conf);
1322 /* Reconfigure so that the PCI scanner discovers the
1323 device is now multifunction */
1325 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1326 pdev->hdr_type = hdr & 0x7f;
1327 pdev->multifunction = !!(hdr & 0x80);
1329 break;
1333 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1335 #endif
1337 #ifdef CONFIG_X86_IO_APIC
1338 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1340 int i;
1342 if ((pdev->class >> 8) != 0xff00)
1343 return;
1345 /* the first BAR is the location of the IO APIC...we must
1346 * not touch this (and it's already covered by the fixmap), so
1347 * forcibly insert it into the resource tree */
1348 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1349 insert_resource(&iomem_resource, &pdev->resource[0]);
1351 /* The next five BARs all seem to be rubbish, so just clean
1352 * them out */
1353 for (i=1; i < 6; i++) {
1354 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1359 #endif
1361 enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1362 /* Defaults to combined */
1363 static enum ide_combined_type combined_mode;
1365 static int __init combined_setup(char *str)
1367 if (!strncmp(str, "ide", 3))
1368 combined_mode = IDE;
1369 else if (!strncmp(str, "libata", 6))
1370 combined_mode = LIBATA;
1371 else /* "combined" or anything else defaults to old behavior */
1372 combined_mode = COMBINED;
1374 return 1;
1376 __setup("combined_mode=", combined_setup);
1378 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1379 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1381 u8 prog, comb, tmp;
1382 int ich = 0;
1384 /*
1385 * Narrow down to Intel SATA PCI devices.
1386 */
1387 switch (pdev->device) {
1388 /* PCI ids taken from drivers/scsi/ata_piix.c */
1389 case 0x24d1:
1390 case 0x24df:
1391 case 0x25a3:
1392 case 0x25b0:
1393 ich = 5;
1394 break;
1395 case 0x2651:
1396 case 0x2652:
1397 case 0x2653:
1398 case 0x2680: /* ESB2 */
1399 ich = 6;
1400 break;
1401 case 0x27c0:
1402 case 0x27c4:
1403 ich = 7;
1404 break;
1405 case 0x2828: /* ICH8M */
1406 ich = 8;
1407 break;
1408 default:
1409 /* we do not handle this PCI device */
1410 return;
1413 /*
1414 * Read combined mode register.
1415 */
1416 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1418 if (ich == 5) {
1419 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1420 if (tmp == 0x4) /* bits 10x */
1421 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1422 else if (tmp == 0x6) /* bits 11x */
1423 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1424 else
1425 return; /* not in combined mode */
1426 } else {
1427 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1428 tmp &= 0x3; /* interesting bits 1:0 */
1429 if (tmp & (1 << 0))
1430 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1431 else if (tmp & (1 << 1))
1432 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1433 else
1434 return; /* not in combined mode */
1437 /*
1438 * Read programming interface register.
1439 * (Tells us if it's legacy or native mode)
1440 */
1441 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1443 /* if SATA port is in native mode, we're ok. */
1444 if (prog & comb)
1445 return;
1447 /* Don't reserve any so the IDE driver can get them (but only if
1448 * combined_mode=ide).
1449 */
1450 if (combined_mode == IDE)
1451 return;
1453 /* Grab them both for libata if combined_mode=libata. */
1454 if (combined_mode == LIBATA) {
1455 request_region(0x1f0, 8, "libata"); /* port 0 */
1456 request_region(0x170, 8, "libata"); /* port 1 */
1457 return;
1460 /* SATA port is in legacy mode. Reserve port so that
1461 * IDE driver does not attempt to use it. If request_region
1462 * fails, it will be obvious at boot time, so we don't bother
1463 * checking return values.
1464 */
1465 if (comb == (1 << 0))
1466 request_region(0x1f0, 8, "libata"); /* port 0 */
1467 else
1468 request_region(0x170, 8, "libata"); /* port 1 */
1470 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1471 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1474 int pcie_mch_quirk;
1476 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1478 pcie_mch_quirk = 1;
1480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1485 /*
1486 * It's possible for the MSI to get corrupted if shpc and acpi
1487 * are used together on certain PXH-based systems.
1488 */
1489 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1491 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1492 PCI_CAP_ID_MSI);
1493 dev->no_msi = 1;
1495 printk(KERN_WARNING "PCI: PXH quirk detected, "
1496 "disabling MSI for SHPC device\n");
1498 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1500 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1502 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1504 /*
1505 * Some Intel PCI Express chipsets have trouble with downstream
1506 * device power management.
1507 */
1508 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1510 pci_pm_d3_delay = 120;
1511 dev->no_d1d2 = 1;
1514 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1516 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1517 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1521 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1522 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1523 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1524 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1526 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1527 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1533 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1536 /*
1537 * Fixup the cardbus bridges on the IBM Dock II docking station
1538 */
1539 static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1541 u32 val;
1543 /*
1544 * tie the 2 interrupt pins to INTA, and configure the
1545 * multifunction routing register to handle this.
1546 */
1547 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1548 (dev->subsystem_device == 0x0148)) {
1549 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1550 "applying quirk\n");
1551 pci_read_config_dword(dev, 0x8c, &val);
1552 val = ((val & 0xffffff00) | 0x1002);
1553 pci_write_config_dword(dev, 0x8c, val);
1554 pci_read_config_dword(dev, 0x80, &val);
1555 val = ((val & 0x00ffff00) | 0x2864c077);
1556 pci_write_config_dword(dev, 0x80, val);
1560 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1561 quirk_ibm_dock2_cardbus);
1563 static void __devinit quirk_netmos(struct pci_dev *dev)
1565 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1566 unsigned int num_serial = dev->subsystem_device & 0xf;
1568 /*
1569 * These Netmos parts are multiport serial devices with optional
1570 * parallel ports. Even when parallel ports are present, they
1571 * are identified as class SERIAL, which means the serial driver
1572 * will claim them. To prevent this, mark them as class OTHER.
1573 * These combo devices should be claimed by parport_serial.
1575 * The subdevice ID is of the form 0x00PS, where <P> is the number
1576 * of parallel ports and <S> is the number of serial ports.
1577 */
1578 switch (dev->device) {
1579 case PCI_DEVICE_ID_NETMOS_9735:
1580 case PCI_DEVICE_ID_NETMOS_9745:
1581 case PCI_DEVICE_ID_NETMOS_9835:
1582 case PCI_DEVICE_ID_NETMOS_9845:
1583 case PCI_DEVICE_ID_NETMOS_9855:
1584 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1585 num_parallel) {
1586 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1587 "%u serial); changing class SERIAL to OTHER "
1588 "(use parport_serial)\n",
1589 dev->device, num_parallel, num_serial);
1590 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1591 (dev->class & 0xff);
1595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1597 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1599 u16 command, pmcsr;
1600 u32 bar;
1601 u8 __iomem *csr;
1602 u8 cmd_hi;
1603 int pm;
1605 switch (dev->device) {
1606 /* PCI IDs taken from drivers/net/e100.c */
1607 case 0x1029:
1608 case 0x1030 ... 0x1034:
1609 case 0x1038 ... 0x103E:
1610 case 0x1050 ... 0x1057:
1611 case 0x1059:
1612 case 0x1064 ... 0x106B:
1613 case 0x1091 ... 0x1095:
1614 case 0x1209:
1615 case 0x1229:
1616 case 0x2449:
1617 case 0x2459:
1618 case 0x245D:
1619 case 0x27DC:
1620 break;
1621 default:
1622 return;
1625 /*
1626 * Some firmware hands off the e100 with interrupts enabled,
1627 * which can cause a flood of interrupts if packets are
1628 * received before the driver attaches to the device. So
1629 * disable all e100 interrupts here. The driver will
1630 * re-enable them when it's ready.
1631 */
1632 pci_read_config_word(dev, PCI_COMMAND, &command);
1633 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1635 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1636 return;
1638 /*
1639 * Check that the device is in the D0 power state. If it's not,
1640 * there is no point to look any further.
1641 */
1642 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1643 if (pm) {
1644 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1645 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1646 return;
1649 csr = ioremap(bar, 8);
1650 if (!csr) {
1651 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1652 pci_name(dev));
1653 return;
1656 cmd_hi = readb(csr + 3);
1657 if (cmd_hi == 0) {
1658 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1659 "enabled, disabling\n", pci_name(dev));
1660 writeb(1, csr + 3);
1663 iounmap(csr);
1665 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1667 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1669 /* rev 1 ncr53c810 chips don't set the class at all which means
1670 * they don't get their resources remapped. Fix that here.
1671 */
1673 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1674 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1675 dev->class = PCI_CLASS_STORAGE_SCSI;
1678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1681 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1683 while (f < end) {
1684 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1685 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1686 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1687 f->hook(dev);
1689 f++;
1693 extern struct pci_fixup __start_pci_fixups_early[];
1694 extern struct pci_fixup __end_pci_fixups_early[];
1695 extern struct pci_fixup __start_pci_fixups_header[];
1696 extern struct pci_fixup __end_pci_fixups_header[];
1697 extern struct pci_fixup __start_pci_fixups_final[];
1698 extern struct pci_fixup __end_pci_fixups_final[];
1699 extern struct pci_fixup __start_pci_fixups_enable[];
1700 extern struct pci_fixup __end_pci_fixups_enable[];
1703 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1705 struct pci_fixup *start, *end;
1707 switch(pass) {
1708 case pci_fixup_early:
1709 start = __start_pci_fixups_early;
1710 end = __end_pci_fixups_early;
1711 break;
1713 case pci_fixup_header:
1714 start = __start_pci_fixups_header;
1715 end = __end_pci_fixups_header;
1716 break;
1718 case pci_fixup_final:
1719 start = __start_pci_fixups_final;
1720 end = __end_pci_fixups_final;
1721 break;
1723 case pci_fixup_enable:
1724 start = __start_pci_fixups_enable;
1725 end = __end_pci_fixups_enable;
1726 break;
1728 default:
1729 /* stupid compiler warning, you would think with an enum... */
1730 return;
1732 pci_do_fixups(dev, start, end);
1735 /* Enable 1k I/O space granularity on the Intel P64H2 */
1736 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1738 u16 en1k;
1739 u8 io_base_lo, io_limit_lo;
1740 unsigned long base, limit;
1741 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1743 pci_read_config_word(dev, 0x40, &en1k);
1745 if (en1k & 0x200) {
1746 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1748 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1749 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1750 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1751 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1753 if (base <= limit) {
1754 res->start = base;
1755 res->end = limit + 0x3ff;
1759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1761 /* Under some circumstances, AER is not linked with extended capabilities.
1762 * Force it to be linked by setting the corresponding control bit in the
1763 * config space.
1764 */
1765 static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1767 uint8_t b;
1768 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1769 if (!(b & 0x20)) {
1770 pci_write_config_byte(dev, 0xf41, b | 0x20);
1771 printk(KERN_INFO
1772 "PCI: Linking AER extended capability on %s\n",
1773 pci_name(dev));
1777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1778 quirk_nvidia_ck804_pcie_aer_ext_cap);
1780 EXPORT_SYMBOL(pcie_mch_quirk);
1781 #ifdef CONFIG_HOTPLUG
1782 EXPORT_SYMBOL(pci_fixup_device);
1783 #endif