ia64/linux-2.6.18-xen.hg

view arch/x86_64/kernel/io_apic-xen.c @ 749:2892ca2b9c17

linux/x86: cleanup IO-APIC code

- get 32-bit code in sync with 64-bit wrt ExtINT pin detection being
unnecessary
- eliminate build warnings resulting from c/s 725

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Nov 28 13:31:21 2008 +0000 (2008-11-28)
parents 69694615aebb
children 2f1b770d84e5
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #ifdef CONFIG_ACPI
33 #include <acpi/acpi_bus.h>
34 #endif
36 #include <asm/io.h>
37 #include <asm/smp.h>
38 #include <asm/desc.h>
39 #include <asm/proto.h>
40 #include <asm/mach_apic.h>
41 #include <asm/acpi.h>
42 #include <asm/dma.h>
43 #include <asm/nmi.h>
45 #define __apicdebuginit __init
47 int sis_apic_bug; /* not actually supported, dummy for compile */
49 static int no_timer_check;
51 int disable_timer_pin_1 __initdata;
53 #ifndef CONFIG_XEN
54 int timer_over_8254 __initdata = 0;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 #endif
60 static DEFINE_SPINLOCK(ioapic_lock);
61 static DEFINE_SPINLOCK(vector_lock);
63 /*
64 * # of IRQ routing registers
65 */
66 int nr_ioapic_registers[MAX_IO_APICS];
68 /*
69 * Rough estimation of how many shared IRQs there are, can
70 * be changed anytime.
71 */
72 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
73 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
75 /*
76 * This is performance-critical, we want to do it O(1)
77 *
78 * the indexing order of this array favors 1:1 mappings
79 * between pins and IRQs.
80 */
82 static struct irq_pin_list {
83 short apic, pin, next;
84 } irq_2_pin[PIN_MAP_SIZE];
86 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
87 #ifdef CONFIG_PCI_MSI
88 #define vector_to_irq(vector) \
89 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
90 #else
91 #define vector_to_irq(vector) (vector)
92 #endif
94 #ifdef CONFIG_XEN
96 #include <xen/interface/xen.h>
97 #include <xen/interface/physdev.h>
98 #include <xen/evtchn.h>
100 /* Fake i8259 */
101 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
102 #define disable_8259A_irq(_irq) ((void)0)
103 #define i8259A_irq_pending(_irq) (0)
105 unsigned long io_apic_irqs;
107 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
108 {
109 struct physdev_apic apic_op;
110 int ret;
112 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
113 apic_op.reg = reg;
114 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
115 if (ret)
116 return ret;
117 return apic_op.value;
118 }
120 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
121 {
122 struct physdev_apic apic_op;
124 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
125 apic_op.reg = reg;
126 apic_op.value = value;
127 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
128 }
130 #define io_apic_read(a,r) xen_io_apic_read(a,r)
131 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
133 #define clear_IO_APIC() ((void)0)
135 #else
137 #ifdef CONFIG_SMP
138 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
139 {
140 unsigned long flags;
141 unsigned int dest;
142 cpumask_t tmp;
144 cpus_and(tmp, mask, cpu_online_map);
145 if (cpus_empty(tmp))
146 tmp = TARGET_CPUS;
148 cpus_and(mask, tmp, CPU_MASK_ALL);
150 dest = cpu_mask_to_apicid(mask);
152 /*
153 * Only the high 8 bits are valid.
154 */
155 dest = SET_APIC_LOGICAL_ID(dest);
157 spin_lock_irqsave(&ioapic_lock, flags);
158 __DO_ACTION(1, = dest, )
159 set_irq_info(irq, mask);
160 spin_unlock_irqrestore(&ioapic_lock, flags);
161 }
162 #endif
164 #endif /* !CONFIG_XEN */
166 /*
167 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
168 * shared ISA-space IRQs, so we have to support them. We are super
169 * fast in the common case, and fast for shared ISA-space IRQs.
170 */
171 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
172 {
173 static int first_free_entry = NR_IRQS;
174 struct irq_pin_list *entry = irq_2_pin + irq;
176 BUG_ON(irq >= NR_IRQS);
177 while (entry->next)
178 entry = irq_2_pin + entry->next;
180 if (entry->pin != -1) {
181 entry->next = first_free_entry;
182 entry = irq_2_pin + entry->next;
183 if (++first_free_entry >= PIN_MAP_SIZE)
184 panic("io_apic.c: ran out of irq_2_pin entries!");
185 }
186 entry->apic = apic;
187 entry->pin = pin;
188 }
190 #ifndef CONFIG_XEN
191 #define __DO_ACTION(R, ACTION, FINAL) \
192 \
193 { \
194 int pin; \
195 struct irq_pin_list *entry = irq_2_pin + irq; \
196 \
197 BUG_ON(irq >= NR_IRQS); \
198 for (;;) { \
199 unsigned int reg; \
200 pin = entry->pin; \
201 if (pin == -1) \
202 break; \
203 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
204 reg ACTION; \
205 io_apic_modify(entry->apic, reg); \
206 if (!entry->next) \
207 break; \
208 entry = irq_2_pin + entry->next; \
209 } \
210 FINAL; \
211 }
213 #define DO_ACTION(name,R,ACTION, FINAL) \
214 \
215 static void name##_IO_APIC_irq (unsigned int irq) \
216 __DO_ACTION(R, ACTION, FINAL)
218 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
219 /* mask = 1 */
220 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
221 /* mask = 0 */
223 static void mask_IO_APIC_irq (unsigned int irq)
224 {
225 unsigned long flags;
227 spin_lock_irqsave(&ioapic_lock, flags);
228 __mask_IO_APIC_irq(irq);
229 spin_unlock_irqrestore(&ioapic_lock, flags);
230 }
232 static void unmask_IO_APIC_irq (unsigned int irq)
233 {
234 unsigned long flags;
236 spin_lock_irqsave(&ioapic_lock, flags);
237 __unmask_IO_APIC_irq(irq);
238 spin_unlock_irqrestore(&ioapic_lock, flags);
239 }
241 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
242 {
243 struct IO_APIC_route_entry entry;
244 unsigned long flags;
246 /* Check delivery_mode to be sure we're not clearing an SMI pin */
247 spin_lock_irqsave(&ioapic_lock, flags);
248 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
249 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
250 spin_unlock_irqrestore(&ioapic_lock, flags);
251 if (entry.delivery_mode == dest_SMI)
252 return;
253 /*
254 * Disable it in the IO-APIC irq-routing table:
255 */
256 memset(&entry, 0, sizeof(entry));
257 entry.mask = 1;
258 spin_lock_irqsave(&ioapic_lock, flags);
259 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
260 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
261 spin_unlock_irqrestore(&ioapic_lock, flags);
262 }
264 static void clear_IO_APIC (void)
265 {
266 int apic, pin;
268 for (apic = 0; apic < nr_ioapics; apic++)
269 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
270 clear_IO_APIC_pin(apic, pin);
271 }
273 #endif /* !CONFIG_XEN */
275 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
277 /*
278 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
279 * specific CPU-side IRQs.
280 */
282 #define MAX_PIRQS 8
283 static int pirq_entries [MAX_PIRQS];
284 static int pirqs_enabled;
285 int skip_ioapic_setup;
286 int ioapic_force;
288 /* dummy parsing: see setup.c */
290 static int __init disable_ioapic_setup(char *str)
291 {
292 skip_ioapic_setup = 1;
293 return 1;
294 }
296 static int __init enable_ioapic_setup(char *str)
297 {
298 ioapic_force = 1;
299 skip_ioapic_setup = 0;
300 return 1;
301 }
303 __setup("noapic", disable_ioapic_setup);
304 __setup("apic", enable_ioapic_setup);
306 #ifndef CONFIG_XEN
307 static int __init setup_disable_8254_timer(char *s)
308 {
309 timer_over_8254 = -1;
310 return 1;
311 }
312 static int __init setup_enable_8254_timer(char *s)
313 {
314 timer_over_8254 = 2;
315 return 1;
316 }
318 __setup("disable_8254_timer", setup_disable_8254_timer);
319 __setup("enable_8254_timer", setup_enable_8254_timer);
320 #endif /* !CONFIG_XEN */
322 #include <asm/pci-direct.h>
323 #include <linux/pci_ids.h>
324 #include <linux/pci.h>
327 #ifdef CONFIG_ACPI
329 static int nvidia_hpet_detected __initdata;
331 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
332 {
333 nvidia_hpet_detected = 1;
334 return 0;
335 }
336 #endif
338 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
339 off. Check for an Nvidia or VIA PCI bridge and turn it off.
340 Use pci direct infrastructure because this runs before the PCI subsystem.
342 Can be overwritten with "apic"
344 And another hack to disable the IOMMU on VIA chipsets.
346 ... and others. Really should move this somewhere else.
348 Kludge-O-Rama. */
349 void __init check_ioapic(void)
350 {
351 int num,slot,func;
352 /* Poor man's PCI discovery */
353 for (num = 0; num < 32; num++) {
354 for (slot = 0; slot < 32; slot++) {
355 for (func = 0; func < 8; func++) {
356 u32 class;
357 u32 vendor;
358 u8 type;
359 class = read_pci_config(num,slot,func,
360 PCI_CLASS_REVISION);
361 if (class == 0xffffffff)
362 break;
364 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
365 continue;
367 vendor = read_pci_config(num, slot, func,
368 PCI_VENDOR_ID);
369 vendor &= 0xffff;
370 switch (vendor) {
371 case PCI_VENDOR_ID_VIA:
372 #ifdef CONFIG_IOMMU
373 if ((end_pfn > MAX_DMA32_PFN ||
374 force_iommu) &&
375 !iommu_aperture_allowed) {
376 printk(KERN_INFO
377 "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
378 iommu_aperture_disabled = 1;
379 }
380 #endif
381 return;
382 case PCI_VENDOR_ID_NVIDIA:
383 #ifdef CONFIG_ACPI
384 /*
385 * All timer overrides on Nvidia are
386 * wrong unless HPET is enabled.
387 */
388 nvidia_hpet_detected = 0;
389 acpi_table_parse(ACPI_HPET,
390 nvidia_hpet_check);
391 if (nvidia_hpet_detected == 0) {
392 acpi_skip_timer_override = 1;
393 printk(KERN_INFO "Nvidia board "
394 "detected. Ignoring ACPI "
395 "timer override.\n");
396 }
397 #endif
398 /* RED-PEN skip them on mptables too? */
399 return;
400 case PCI_VENDOR_ID_ATI:
402 /* This should be actually default, but
403 for 2.6.16 let's do it for ATI only where
404 it's really needed. */
405 #ifndef CONFIG_XEN
406 if (timer_over_8254 == 1) {
407 timer_over_8254 = 0;
408 printk(KERN_INFO
409 "ATI board detected. Disabling timer routing over 8254.\n");
410 }
411 #endif
412 return;
413 }
416 /* No multi-function device? */
417 type = read_pci_config_byte(num,slot,func,
418 PCI_HEADER_TYPE);
419 if (!(type & 0x80))
420 break;
421 }
422 }
423 }
424 }
426 static int __init ioapic_pirq_setup(char *str)
427 {
428 int i, max;
429 int ints[MAX_PIRQS+1];
431 get_options(str, ARRAY_SIZE(ints), ints);
433 for (i = 0; i < MAX_PIRQS; i++)
434 pirq_entries[i] = -1;
436 pirqs_enabled = 1;
437 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
438 max = MAX_PIRQS;
439 if (ints[0] < MAX_PIRQS)
440 max = ints[0];
442 for (i = 0; i < max; i++) {
443 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
444 /*
445 * PIRQs are mapped upside down, usually.
446 */
447 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
448 }
449 return 1;
450 }
452 __setup("pirq=", ioapic_pirq_setup);
454 /*
455 * Find the IRQ entry number of a certain pin.
456 */
457 static int find_irq_entry(int apic, int pin, int type)
458 {
459 int i;
461 for (i = 0; i < mp_irq_entries; i++)
462 if (mp_irqs[i].mpc_irqtype == type &&
463 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
464 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
465 mp_irqs[i].mpc_dstirq == pin)
466 return i;
468 return -1;
469 }
471 #ifndef CONFIG_XEN
472 /*
473 * Find the pin to which IRQ[irq] (ISA) is connected
474 */
475 static int __init find_isa_irq_pin(int irq, int type)
476 {
477 int i;
479 for (i = 0; i < mp_irq_entries; i++) {
480 int lbus = mp_irqs[i].mpc_srcbus;
482 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
483 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
484 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
485 (mp_irqs[i].mpc_irqtype == type) &&
486 (mp_irqs[i].mpc_srcbusirq == irq))
488 return mp_irqs[i].mpc_dstirq;
489 }
490 return -1;
491 }
493 static int __init find_isa_irq_apic(int irq, int type)
494 {
495 int i;
497 for (i = 0; i < mp_irq_entries; i++) {
498 int lbus = mp_irqs[i].mpc_srcbus;
500 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
501 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
502 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
503 (mp_irqs[i].mpc_irqtype == type) &&
504 (mp_irqs[i].mpc_srcbusirq == irq))
505 break;
506 }
507 if (i < mp_irq_entries) {
508 int apic;
509 for(apic = 0; apic < nr_ioapics; apic++) {
510 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
511 return apic;
512 }
513 }
515 return -1;
516 }
517 #endif
519 /*
520 * Find a specific PCI IRQ entry.
521 * Not an __init, possibly needed by modules
522 */
523 static int pin_2_irq(int idx, int apic, int pin);
525 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
526 {
527 int apic, i, best_guess = -1;
529 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
530 bus, slot, pin);
531 if (mp_bus_id_to_pci_bus[bus] == -1) {
532 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
533 return -1;
534 }
535 for (i = 0; i < mp_irq_entries; i++) {
536 int lbus = mp_irqs[i].mpc_srcbus;
538 for (apic = 0; apic < nr_ioapics; apic++)
539 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
540 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
541 break;
543 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
544 !mp_irqs[i].mpc_irqtype &&
545 (bus == lbus) &&
546 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
547 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
549 if (!(apic || IO_APIC_IRQ(irq)))
550 continue;
552 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
553 return irq;
554 /*
555 * Use the first all-but-pin matching entry as a
556 * best-guess fuzzy result for broken mptables.
557 */
558 if (best_guess < 0)
559 best_guess = irq;
560 }
561 }
562 BUG_ON(best_guess >= NR_IRQS);
563 return best_guess;
564 }
566 /*
567 * EISA Edge/Level control register, ELCR
568 */
569 static int EISA_ELCR(unsigned int irq)
570 {
571 if (irq < 16) {
572 unsigned int port = 0x4d0 + (irq >> 3);
573 return (inb(port) >> (irq & 7)) & 1;
574 }
575 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
576 return 0;
577 }
579 /* EISA interrupts are always polarity zero and can be edge or level
580 * trigger depending on the ELCR value. If an interrupt is listed as
581 * EISA conforming in the MP table, that means its trigger type must
582 * be read in from the ELCR */
584 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
585 #define default_EISA_polarity(idx) (0)
587 /* ISA interrupts are always polarity zero edge triggered,
588 * when listed as conforming in the MP table. */
590 #define default_ISA_trigger(idx) (0)
591 #define default_ISA_polarity(idx) (0)
593 /* PCI interrupts are always polarity one level triggered,
594 * when listed as conforming in the MP table. */
596 #define default_PCI_trigger(idx) (1)
597 #define default_PCI_polarity(idx) (1)
599 /* MCA interrupts are always polarity zero level triggered,
600 * when listed as conforming in the MP table. */
602 #define default_MCA_trigger(idx) (1)
603 #define default_MCA_polarity(idx) (0)
605 static int __init MPBIOS_polarity(int idx)
606 {
607 int bus = mp_irqs[idx].mpc_srcbus;
608 int polarity;
610 /*
611 * Determine IRQ line polarity (high active or low active):
612 */
613 switch (mp_irqs[idx].mpc_irqflag & 3)
614 {
615 case 0: /* conforms, ie. bus-type dependent polarity */
616 {
617 switch (mp_bus_id_to_type[bus])
618 {
619 case MP_BUS_ISA: /* ISA pin */
620 {
621 polarity = default_ISA_polarity(idx);
622 break;
623 }
624 case MP_BUS_EISA: /* EISA pin */
625 {
626 polarity = default_EISA_polarity(idx);
627 break;
628 }
629 case MP_BUS_PCI: /* PCI pin */
630 {
631 polarity = default_PCI_polarity(idx);
632 break;
633 }
634 case MP_BUS_MCA: /* MCA pin */
635 {
636 polarity = default_MCA_polarity(idx);
637 break;
638 }
639 default:
640 {
641 printk(KERN_WARNING "broken BIOS!!\n");
642 polarity = 1;
643 break;
644 }
645 }
646 break;
647 }
648 case 1: /* high active */
649 {
650 polarity = 0;
651 break;
652 }
653 case 2: /* reserved */
654 {
655 printk(KERN_WARNING "broken BIOS!!\n");
656 polarity = 1;
657 break;
658 }
659 case 3: /* low active */
660 {
661 polarity = 1;
662 break;
663 }
664 default: /* invalid */
665 {
666 printk(KERN_WARNING "broken BIOS!!\n");
667 polarity = 1;
668 break;
669 }
670 }
671 return polarity;
672 }
674 static int MPBIOS_trigger(int idx)
675 {
676 int bus = mp_irqs[idx].mpc_srcbus;
677 int trigger;
679 /*
680 * Determine IRQ trigger mode (edge or level sensitive):
681 */
682 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
683 {
684 case 0: /* conforms, ie. bus-type dependent */
685 {
686 switch (mp_bus_id_to_type[bus])
687 {
688 case MP_BUS_ISA: /* ISA pin */
689 {
690 trigger = default_ISA_trigger(idx);
691 break;
692 }
693 case MP_BUS_EISA: /* EISA pin */
694 {
695 trigger = default_EISA_trigger(idx);
696 break;
697 }
698 case MP_BUS_PCI: /* PCI pin */
699 {
700 trigger = default_PCI_trigger(idx);
701 break;
702 }
703 case MP_BUS_MCA: /* MCA pin */
704 {
705 trigger = default_MCA_trigger(idx);
706 break;
707 }
708 default:
709 {
710 printk(KERN_WARNING "broken BIOS!!\n");
711 trigger = 1;
712 break;
713 }
714 }
715 break;
716 }
717 case 1: /* edge */
718 {
719 trigger = 0;
720 break;
721 }
722 case 2: /* reserved */
723 {
724 printk(KERN_WARNING "broken BIOS!!\n");
725 trigger = 1;
726 break;
727 }
728 case 3: /* level */
729 {
730 trigger = 1;
731 break;
732 }
733 default: /* invalid */
734 {
735 printk(KERN_WARNING "broken BIOS!!\n");
736 trigger = 0;
737 break;
738 }
739 }
740 return trigger;
741 }
743 static inline int irq_polarity(int idx)
744 {
745 return MPBIOS_polarity(idx);
746 }
748 static inline int irq_trigger(int idx)
749 {
750 return MPBIOS_trigger(idx);
751 }
753 static int next_irq = 16;
755 /*
756 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
757 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
758 * from ACPI, which can reach 800 in large boxen.
759 *
760 * Compact the sparse GSI space into a sequential IRQ series and reuse
761 * vectors if possible.
762 */
763 int gsi_irq_sharing(int gsi)
764 {
765 int i, tries, vector;
767 BUG_ON(gsi >= NR_IRQ_VECTORS);
769 if (platform_legacy_irq(gsi))
770 return gsi;
772 if (gsi_2_irq[gsi] != 0xFF)
773 return (int)gsi_2_irq[gsi];
775 tries = NR_IRQS;
776 try_again:
777 vector = assign_irq_vector(gsi);
779 /*
780 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
781 * use of vector and if found, return that IRQ. However, we never want
782 * to share legacy IRQs, which usually have a different trigger mode
783 * than PCI.
784 */
785 for (i = 0; i < NR_IRQS; i++)
786 if (IO_APIC_VECTOR(i) == vector)
787 break;
788 if (platform_legacy_irq(i)) {
789 if (--tries >= 0) {
790 IO_APIC_VECTOR(i) = 0;
791 goto try_again;
792 }
793 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
794 }
795 if (i < NR_IRQS) {
796 gsi_2_irq[gsi] = i;
797 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
798 gsi, vector, i);
799 return i;
800 }
802 i = next_irq++;
803 BUG_ON(i >= NR_IRQS);
804 gsi_2_irq[gsi] = i;
805 IO_APIC_VECTOR(i) = vector;
806 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
807 gsi, vector, i);
808 return i;
809 }
811 static int pin_2_irq(int idx, int apic, int pin)
812 {
813 int irq, i;
814 int bus = mp_irqs[idx].mpc_srcbus;
816 /*
817 * Debugging check, we are in big trouble if this message pops up!
818 */
819 if (mp_irqs[idx].mpc_dstirq != pin)
820 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
822 switch (mp_bus_id_to_type[bus])
823 {
824 case MP_BUS_ISA: /* ISA pin */
825 case MP_BUS_EISA:
826 case MP_BUS_MCA:
827 {
828 irq = mp_irqs[idx].mpc_srcbusirq;
829 break;
830 }
831 case MP_BUS_PCI: /* PCI pin */
832 {
833 /*
834 * PCI IRQs are mapped in order
835 */
836 i = irq = 0;
837 while (i < apic)
838 irq += nr_ioapic_registers[i++];
839 irq += pin;
840 irq = gsi_irq_sharing(irq);
841 break;
842 }
843 default:
844 {
845 printk(KERN_ERR "unknown bus type %d.\n",bus);
846 irq = 0;
847 break;
848 }
849 }
850 BUG_ON(irq >= NR_IRQS);
852 /*
853 * PCI IRQ command line redirection. Yes, limits are hardcoded.
854 */
855 if ((pin >= 16) && (pin <= 23)) {
856 if (pirq_entries[pin-16] != -1) {
857 if (!pirq_entries[pin-16]) {
858 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
859 } else {
860 irq = pirq_entries[pin-16];
861 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
862 pin-16, irq);
863 }
864 }
865 }
866 BUG_ON(irq >= NR_IRQS);
867 return irq;
868 }
870 static inline int IO_APIC_irq_trigger(int irq)
871 {
872 int apic, idx, pin;
874 for (apic = 0; apic < nr_ioapics; apic++) {
875 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
876 idx = find_irq_entry(apic,pin,mp_INT);
877 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
878 return irq_trigger(idx);
879 }
880 }
881 /*
882 * nonexistent IRQs are edge default
883 */
884 return 0;
885 }
887 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
888 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
890 int assign_irq_vector(int irq)
891 {
892 unsigned long flags;
893 int vector;
894 struct physdev_irq irq_op;
896 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
898 if (irq < PIRQ_BASE || irq - PIRQ_BASE > NR_PIRQS)
899 return -EINVAL;
901 spin_lock_irqsave(&vector_lock, flags);
903 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
904 spin_unlock_irqrestore(&vector_lock, flags);
905 return IO_APIC_VECTOR(irq);
906 }
908 irq_op.irq = irq;
909 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
910 spin_unlock_irqrestore(&vector_lock, flags);
911 return -ENOSPC;
912 }
914 vector = irq_op.vector;
915 vector_irq[vector] = irq;
916 if (irq != AUTO_ASSIGN)
917 IO_APIC_VECTOR(irq) = vector;
919 spin_unlock_irqrestore(&vector_lock, flags);
921 return vector;
922 }
924 extern void (*interrupt[NR_IRQS])(void);
925 #ifndef CONFIG_XEN
926 static struct hw_interrupt_type ioapic_level_type;
927 static struct hw_interrupt_type ioapic_edge_type;
929 #define IOAPIC_AUTO -1
930 #define IOAPIC_EDGE 0
931 #define IOAPIC_LEVEL 1
933 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
934 {
935 unsigned idx;
937 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
939 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
940 trigger == IOAPIC_LEVEL)
941 irq_desc[idx].chip = &ioapic_level_type;
942 else
943 irq_desc[idx].chip = &ioapic_edge_type;
944 set_intr_gate(vector, interrupt[idx]);
945 }
946 #else
947 #define ioapic_register_intr(irq, vector, trigger) evtchn_register_pirq(irq)
948 #endif /* !CONFIG_XEN */
950 static void __init setup_IO_APIC_irqs(void)
951 {
952 struct IO_APIC_route_entry entry;
953 int apic, pin, idx, irq, first_notcon = 1, vector;
954 unsigned long flags;
956 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
958 for (apic = 0; apic < nr_ioapics; apic++) {
959 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
961 /*
962 * add it to the IO-APIC irq-routing table:
963 */
964 memset(&entry,0,sizeof(entry));
966 entry.delivery_mode = INT_DELIVERY_MODE;
967 entry.dest_mode = INT_DEST_MODE;
968 entry.mask = 0; /* enable IRQ */
969 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
971 idx = find_irq_entry(apic,pin,mp_INT);
972 if (idx == -1) {
973 if (first_notcon) {
974 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
975 first_notcon = 0;
976 } else
977 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
978 continue;
979 }
981 entry.trigger = irq_trigger(idx);
982 entry.polarity = irq_polarity(idx);
984 if (irq_trigger(idx)) {
985 entry.trigger = 1;
986 entry.mask = 1;
987 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
988 }
990 irq = pin_2_irq(idx, apic, pin);
991 add_pin_to_irq(irq, apic, pin);
993 if (/* !apic && */ !IO_APIC_IRQ(irq))
994 continue;
996 if (IO_APIC_IRQ(irq)) {
997 vector = assign_irq_vector(irq);
998 entry.vector = vector;
1000 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1001 if (!apic && (irq < 16))
1002 disable_8259A_irq(irq);
1004 spin_lock_irqsave(&ioapic_lock, flags);
1005 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1006 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1007 set_native_irq_info(irq, TARGET_CPUS);
1008 spin_unlock_irqrestore(&ioapic_lock, flags);
1012 if (!first_notcon)
1013 apic_printk(APIC_VERBOSE," not connected.\n");
1016 #ifndef CONFIG_XEN
1017 /*
1018 * Set up the 8259A-master output pin as broadcast to all
1019 * CPUs.
1020 */
1021 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1023 struct IO_APIC_route_entry entry;
1024 unsigned long flags;
1026 memset(&entry,0,sizeof(entry));
1028 disable_8259A_irq(0);
1030 /* mask LVT0 */
1031 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1033 /*
1034 * We use logical delivery to get the timer IRQ
1035 * to the first CPU.
1036 */
1037 entry.dest_mode = INT_DEST_MODE;
1038 entry.mask = 0; /* unmask IRQ now */
1039 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1040 entry.delivery_mode = INT_DELIVERY_MODE;
1041 entry.polarity = 0;
1042 entry.trigger = 0;
1043 entry.vector = vector;
1045 /*
1046 * The timer IRQ doesn't have to know that behind the
1047 * scene we have a 8259A-master in AEOI mode ...
1048 */
1049 irq_desc[0].chip = &ioapic_edge_type;
1051 /*
1052 * Add it to the IO-APIC irq-routing table:
1053 */
1054 spin_lock_irqsave(&ioapic_lock, flags);
1055 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1056 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1057 spin_unlock_irqrestore(&ioapic_lock, flags);
1059 enable_8259A_irq(0);
1062 void __init UNEXPECTED_IO_APIC(void)
1066 void __apicdebuginit print_IO_APIC(void)
1068 int apic, i;
1069 union IO_APIC_reg_00 reg_00;
1070 union IO_APIC_reg_01 reg_01;
1071 union IO_APIC_reg_02 reg_02;
1072 unsigned long flags;
1074 if (apic_verbosity == APIC_QUIET)
1075 return;
1077 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1078 for (i = 0; i < nr_ioapics; i++)
1079 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1080 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1082 /*
1083 * We are a bit conservative about what we expect. We have to
1084 * know about every hardware change ASAP.
1085 */
1086 printk(KERN_INFO "testing the IO APIC.......................\n");
1088 for (apic = 0; apic < nr_ioapics; apic++) {
1090 spin_lock_irqsave(&ioapic_lock, flags);
1091 reg_00.raw = io_apic_read(apic, 0);
1092 reg_01.raw = io_apic_read(apic, 1);
1093 if (reg_01.bits.version >= 0x10)
1094 reg_02.raw = io_apic_read(apic, 2);
1095 spin_unlock_irqrestore(&ioapic_lock, flags);
1097 printk("\n");
1098 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1099 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1100 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1101 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1102 UNEXPECTED_IO_APIC();
1104 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1105 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1106 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1107 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1108 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1109 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1110 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1111 (reg_01.bits.entries != 0x2E) &&
1112 (reg_01.bits.entries != 0x3F) &&
1113 (reg_01.bits.entries != 0x03)
1115 UNEXPECTED_IO_APIC();
1117 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1118 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1119 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1120 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1121 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1122 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1123 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1124 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1126 UNEXPECTED_IO_APIC();
1127 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1128 UNEXPECTED_IO_APIC();
1130 if (reg_01.bits.version >= 0x10) {
1131 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1132 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1133 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1134 UNEXPECTED_IO_APIC();
1137 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1139 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1140 " Stat Dest Deli Vect: \n");
1142 for (i = 0; i <= reg_01.bits.entries; i++) {
1143 struct IO_APIC_route_entry entry;
1145 spin_lock_irqsave(&ioapic_lock, flags);
1146 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1147 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1148 spin_unlock_irqrestore(&ioapic_lock, flags);
1150 printk(KERN_DEBUG " %02x %03X %02X ",
1151 i,
1152 entry.dest.logical.logical_dest,
1153 entry.dest.physical.physical_dest
1154 );
1156 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1157 entry.mask,
1158 entry.trigger,
1159 entry.irr,
1160 entry.polarity,
1161 entry.delivery_status,
1162 entry.dest_mode,
1163 entry.delivery_mode,
1164 entry.vector
1165 );
1168 if (use_pci_vector())
1169 printk(KERN_INFO "Using vector-based indexing\n");
1170 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1171 for (i = 0; i < NR_IRQS; i++) {
1172 struct irq_pin_list *entry = irq_2_pin + i;
1173 if (entry->pin < 0)
1174 continue;
1175 if (use_pci_vector() && !platform_legacy_irq(i))
1176 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1177 else
1178 printk(KERN_DEBUG "IRQ%d ", i);
1179 for (;;) {
1180 printk("-> %d:%d", entry->apic, entry->pin);
1181 if (!entry->next)
1182 break;
1183 entry = irq_2_pin + entry->next;
1185 printk("\n");
1188 printk(KERN_INFO ".................................... done.\n");
1190 return;
1193 static __apicdebuginit void print_APIC_bitfield (int base)
1195 unsigned int v;
1196 int i, j;
1198 if (apic_verbosity == APIC_QUIET)
1199 return;
1201 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1202 for (i = 0; i < 8; i++) {
1203 v = apic_read(base + i*0x10);
1204 for (j = 0; j < 32; j++) {
1205 if (v & (1<<j))
1206 printk("1");
1207 else
1208 printk("0");
1210 printk("\n");
1214 void __apicdebuginit print_local_APIC(void * dummy)
1216 unsigned int v, ver, maxlvt;
1218 if (apic_verbosity == APIC_QUIET)
1219 return;
1221 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1222 smp_processor_id(), hard_smp_processor_id());
1223 v = apic_read(APIC_ID);
1224 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1225 v = apic_read(APIC_LVR);
1226 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1227 ver = GET_APIC_VERSION(v);
1228 maxlvt = get_maxlvt();
1230 v = apic_read(APIC_TASKPRI);
1231 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1233 v = apic_read(APIC_ARBPRI);
1234 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1235 v & APIC_ARBPRI_MASK);
1236 v = apic_read(APIC_PROCPRI);
1237 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1239 v = apic_read(APIC_EOI);
1240 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1241 v = apic_read(APIC_RRR);
1242 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1243 v = apic_read(APIC_LDR);
1244 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1245 v = apic_read(APIC_DFR);
1246 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1247 v = apic_read(APIC_SPIV);
1248 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1250 printk(KERN_DEBUG "... APIC ISR field:\n");
1251 print_APIC_bitfield(APIC_ISR);
1252 printk(KERN_DEBUG "... APIC TMR field:\n");
1253 print_APIC_bitfield(APIC_TMR);
1254 printk(KERN_DEBUG "... APIC IRR field:\n");
1255 print_APIC_bitfield(APIC_IRR);
1257 v = apic_read(APIC_ESR);
1258 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1260 v = apic_read(APIC_ICR);
1261 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1262 v = apic_read(APIC_ICR2);
1263 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1265 v = apic_read(APIC_LVTT);
1266 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1268 if (maxlvt > 3) { /* PC is LVT#4. */
1269 v = apic_read(APIC_LVTPC);
1270 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1272 v = apic_read(APIC_LVT0);
1273 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1274 v = apic_read(APIC_LVT1);
1275 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1277 if (maxlvt > 2) { /* ERR is LVT#3. */
1278 v = apic_read(APIC_LVTERR);
1279 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1282 v = apic_read(APIC_TMICT);
1283 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1284 v = apic_read(APIC_TMCCT);
1285 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1286 v = apic_read(APIC_TDCR);
1287 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1288 printk("\n");
1291 void print_all_local_APICs (void)
1293 on_each_cpu(print_local_APIC, NULL, 1, 1);
1296 void __apicdebuginit print_PIC(void)
1298 unsigned int v;
1299 unsigned long flags;
1301 if (apic_verbosity == APIC_QUIET)
1302 return;
1304 printk(KERN_DEBUG "\nprinting PIC contents\n");
1306 spin_lock_irqsave(&i8259A_lock, flags);
1308 v = inb(0xa1) << 8 | inb(0x21);
1309 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1311 v = inb(0xa0) << 8 | inb(0x20);
1312 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1314 outb(0x0b,0xa0);
1315 outb(0x0b,0x20);
1316 v = inb(0xa0) << 8 | inb(0x20);
1317 outb(0x0a,0xa0);
1318 outb(0x0a,0x20);
1320 spin_unlock_irqrestore(&i8259A_lock, flags);
1322 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1324 v = inb(0x4d1) << 8 | inb(0x4d0);
1325 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1327 #endif /* !CONFIG_XEN */
1329 static void __init enable_IO_APIC(void)
1331 union IO_APIC_reg_01 reg_01;
1332 #ifndef CONFIG_XEN
1333 int i8259_apic, i8259_pin;
1334 #endif
1335 int i, apic;
1336 unsigned long flags;
1338 for (i = 0; i < PIN_MAP_SIZE; i++) {
1339 irq_2_pin[i].pin = -1;
1340 irq_2_pin[i].next = 0;
1342 if (!pirqs_enabled)
1343 for (i = 0; i < MAX_PIRQS; i++)
1344 pirq_entries[i] = -1;
1346 /*
1347 * The number of IO-APIC IRQ registers (== #pins):
1348 */
1349 for (apic = 0; apic < nr_ioapics; apic++) {
1350 spin_lock_irqsave(&ioapic_lock, flags);
1351 reg_01.raw = io_apic_read(apic, 1);
1352 spin_unlock_irqrestore(&ioapic_lock, flags);
1353 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1355 #ifndef CONFIG_XEN
1356 for(apic = 0; apic < nr_ioapics; apic++) {
1357 int pin;
1358 /* See if any of the pins is in ExtINT mode */
1359 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1360 struct IO_APIC_route_entry entry;
1361 spin_lock_irqsave(&ioapic_lock, flags);
1362 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1363 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1364 spin_unlock_irqrestore(&ioapic_lock, flags);
1367 /* If the interrupt line is enabled and in ExtInt mode
1368 * I have found the pin where the i8259 is connected.
1369 */
1370 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1371 ioapic_i8259.apic = apic;
1372 ioapic_i8259.pin = pin;
1373 goto found_i8259;
1377 found_i8259:
1378 /* Look to see what if the MP table has reported the ExtINT */
1379 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1380 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1381 /* Trust the MP table if nothing is setup in the hardware */
1382 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1383 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1384 ioapic_i8259.pin = i8259_pin;
1385 ioapic_i8259.apic = i8259_apic;
1387 /* Complain if the MP table and the hardware disagree */
1388 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1389 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1391 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1393 #endif
1395 /*
1396 * Do not trust the IO-APIC being empty at bootup
1397 */
1398 clear_IO_APIC();
1401 /*
1402 * Not an __init, needed by the reboot code
1403 */
1404 void disable_IO_APIC(void)
1406 /*
1407 * Clear the IO-APIC before rebooting:
1408 */
1409 clear_IO_APIC();
1411 #ifndef CONFIG_XEN
1412 /*
1413 * If the i8259 is routed through an IOAPIC
1414 * Put that IOAPIC in virtual wire mode
1415 * so legacy interrupts can be delivered.
1416 */
1417 if (ioapic_i8259.pin != -1) {
1418 struct IO_APIC_route_entry entry;
1419 unsigned long flags;
1421 memset(&entry, 0, sizeof(entry));
1422 entry.mask = 0; /* Enabled */
1423 entry.trigger = 0; /* Edge */
1424 entry.irr = 0;
1425 entry.polarity = 0; /* High */
1426 entry.delivery_status = 0;
1427 entry.dest_mode = 0; /* Physical */
1428 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1429 entry.vector = 0;
1430 entry.dest.physical.physical_dest =
1431 GET_APIC_ID(apic_read(APIC_ID));
1433 /*
1434 * Add it to the IO-APIC irq-routing table:
1435 */
1436 spin_lock_irqsave(&ioapic_lock, flags);
1437 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1438 *(((int *)&entry)+1));
1439 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1440 *(((int *)&entry)+0));
1441 spin_unlock_irqrestore(&ioapic_lock, flags);
1444 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1445 #endif
1448 /*
1449 * function to set the IO-APIC physical IDs based on the
1450 * values stored in the MPC table.
1452 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1453 */
1455 #ifndef CONFIG_XEN
1456 static void __init setup_ioapic_ids_from_mpc (void)
1458 union IO_APIC_reg_00 reg_00;
1459 int apic;
1460 int i;
1461 unsigned char old_id;
1462 unsigned long flags;
1464 /*
1465 * Set the IOAPIC ID to the value stored in the MPC table.
1466 */
1467 for (apic = 0; apic < nr_ioapics; apic++) {
1469 /* Read the register 0 value */
1470 spin_lock_irqsave(&ioapic_lock, flags);
1471 reg_00.raw = io_apic_read(apic, 0);
1472 spin_unlock_irqrestore(&ioapic_lock, flags);
1474 old_id = mp_ioapics[apic].mpc_apicid;
1477 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1480 /*
1481 * We need to adjust the IRQ routing table
1482 * if the ID changed.
1483 */
1484 if (old_id != mp_ioapics[apic].mpc_apicid)
1485 for (i = 0; i < mp_irq_entries; i++)
1486 if (mp_irqs[i].mpc_dstapic == old_id)
1487 mp_irqs[i].mpc_dstapic
1488 = mp_ioapics[apic].mpc_apicid;
1490 /*
1491 * Read the right value from the MPC table and
1492 * write it into the ID register.
1493 */
1494 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1495 mp_ioapics[apic].mpc_apicid);
1497 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1498 spin_lock_irqsave(&ioapic_lock, flags);
1499 io_apic_write(apic, 0, reg_00.raw);
1500 spin_unlock_irqrestore(&ioapic_lock, flags);
1502 /*
1503 * Sanity check
1504 */
1505 spin_lock_irqsave(&ioapic_lock, flags);
1506 reg_00.raw = io_apic_read(apic, 0);
1507 spin_unlock_irqrestore(&ioapic_lock, flags);
1508 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1509 printk("could not set ID!\n");
1510 else
1511 apic_printk(APIC_VERBOSE," ok.\n");
1514 #else
1515 static void __init setup_ioapic_ids_from_mpc(void) { }
1516 #endif
1518 /*
1519 * There is a nasty bug in some older SMP boards, their mptable lies
1520 * about the timer IRQ. We do the following to work around the situation:
1522 * - timer IRQ defaults to IO-APIC IRQ
1523 * - if this function detects that timer IRQs are defunct, then we fall
1524 * back to ISA timer IRQs
1525 */
1526 #ifndef CONFIG_XEN
1527 static int __init timer_irq_works(void)
1529 unsigned long t1 = jiffies;
1531 local_irq_enable();
1532 /* Let ten ticks pass... */
1533 mdelay((10 * 1000) / HZ);
1535 /*
1536 * Expect a few ticks at least, to be sure some possible
1537 * glue logic does not lock up after one or two first
1538 * ticks in a non-ExtINT mode. Also the local APIC
1539 * might have cached one ExtINT interrupt. Finally, at
1540 * least one tick may be lost due to delays.
1541 */
1543 /* jiffies wrap? */
1544 if (jiffies - t1 > 4)
1545 return 1;
1546 return 0;
1549 /*
1550 * In the SMP+IOAPIC case it might happen that there are an unspecified
1551 * number of pending IRQ events unhandled. These cases are very rare,
1552 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1553 * better to do it this way as thus we do not have to be aware of
1554 * 'pending' interrupts in the IRQ path, except at this point.
1555 */
1556 /*
1557 * Edge triggered needs to resend any interrupt
1558 * that was delayed but this is now handled in the device
1559 * independent code.
1560 */
1562 /*
1563 * Starting up a edge-triggered IO-APIC interrupt is
1564 * nasty - we need to make sure that we get the edge.
1565 * If it is already asserted for some reason, we need
1566 * return 1 to indicate that is was pending.
1568 * This is not complete - we should be able to fake
1569 * an edge even if it isn't on the 8259A...
1570 */
1572 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1574 int was_pending = 0;
1575 unsigned long flags;
1577 spin_lock_irqsave(&ioapic_lock, flags);
1578 if (irq < 16) {
1579 disable_8259A_irq(irq);
1580 if (i8259A_irq_pending(irq))
1581 was_pending = 1;
1583 __unmask_IO_APIC_irq(irq);
1584 spin_unlock_irqrestore(&ioapic_lock, flags);
1586 return was_pending;
1589 /*
1590 * Once we have recorded IRQ_PENDING already, we can mask the
1591 * interrupt for real. This prevents IRQ storms from unhandled
1592 * devices.
1593 */
1594 static void ack_edge_ioapic_irq(unsigned int irq)
1596 move_irq(irq);
1597 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1598 == (IRQ_PENDING | IRQ_DISABLED))
1599 mask_IO_APIC_irq(irq);
1600 ack_APIC_irq();
1603 /*
1604 * Level triggered interrupts can just be masked,
1605 * and shutting down and starting up the interrupt
1606 * is the same as enabling and disabling them -- except
1607 * with a startup need to return a "was pending" value.
1609 * Level triggered interrupts are special because we
1610 * do not touch any IO-APIC register while handling
1611 * them. We ack the APIC in the end-IRQ handler, not
1612 * in the start-IRQ-handler. Protection against reentrance
1613 * from the same interrupt is still provided, both by the
1614 * generic IRQ layer and by the fact that an unacked local
1615 * APIC does not accept IRQs.
1616 */
1617 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1619 unmask_IO_APIC_irq(irq);
1621 return 0; /* don't check for pending */
1624 static void end_level_ioapic_irq (unsigned int irq)
1626 move_irq(irq);
1627 ack_APIC_irq();
1630 #ifdef CONFIG_PCI_MSI
1631 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1633 int irq = vector_to_irq(vector);
1635 return startup_edge_ioapic_irq(irq);
1638 static void ack_edge_ioapic_vector(unsigned int vector)
1640 int irq = vector_to_irq(vector);
1642 move_native_irq(vector);
1643 ack_edge_ioapic_irq(irq);
1646 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1648 int irq = vector_to_irq(vector);
1650 return startup_level_ioapic_irq (irq);
1653 static void end_level_ioapic_vector (unsigned int vector)
1655 int irq = vector_to_irq(vector);
1657 move_native_irq(vector);
1658 end_level_ioapic_irq(irq);
1661 static void mask_IO_APIC_vector (unsigned int vector)
1663 int irq = vector_to_irq(vector);
1665 mask_IO_APIC_irq(irq);
1668 static void unmask_IO_APIC_vector (unsigned int vector)
1670 int irq = vector_to_irq(vector);
1672 unmask_IO_APIC_irq(irq);
1675 #ifdef CONFIG_SMP
1676 static void set_ioapic_affinity_vector (unsigned int vector,
1677 cpumask_t cpu_mask)
1679 int irq = vector_to_irq(vector);
1681 set_native_irq_info(vector, cpu_mask);
1682 set_ioapic_affinity_irq(irq, cpu_mask);
1684 #endif // CONFIG_SMP
1685 #endif // CONFIG_PCI_MSI
1687 static int ioapic_retrigger(unsigned int irq)
1689 send_IPI_self(IO_APIC_VECTOR(irq));
1691 return 1;
1694 /*
1695 * Level and edge triggered IO-APIC interrupts need different handling,
1696 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1697 * handled with the level-triggered descriptor, but that one has slightly
1698 * more overhead. Level-triggered interrupts cannot be handled with the
1699 * edge-triggered handler, without risking IRQ storms and other ugly
1700 * races.
1701 */
1703 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1704 .typename = "IO-APIC-edge",
1705 .startup = startup_edge_ioapic,
1706 .shutdown = shutdown_edge_ioapic,
1707 .enable = enable_edge_ioapic,
1708 .disable = disable_edge_ioapic,
1709 .ack = ack_edge_ioapic,
1710 .end = end_edge_ioapic,
1711 #ifdef CONFIG_SMP
1712 .set_affinity = set_ioapic_affinity,
1713 #endif
1714 .retrigger = ioapic_retrigger,
1715 };
1717 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1718 .typename = "IO-APIC-level",
1719 .startup = startup_level_ioapic,
1720 .shutdown = shutdown_level_ioapic,
1721 .enable = enable_level_ioapic,
1722 .disable = disable_level_ioapic,
1723 .ack = mask_and_ack_level_ioapic,
1724 .end = end_level_ioapic,
1725 #ifdef CONFIG_SMP
1726 .set_affinity = set_ioapic_affinity,
1727 #endif
1728 .retrigger = ioapic_retrigger,
1729 };
1730 #endif /* !CONFIG_XEN */
1732 static inline void init_IO_APIC_traps(void)
1734 int irq;
1736 /*
1737 * NOTE! The local APIC isn't very good at handling
1738 * multiple interrupts at the same interrupt level.
1739 * As the interrupt level is determined by taking the
1740 * vector number and shifting that right by 4, we
1741 * want to spread these out a bit so that they don't
1742 * all fall in the same interrupt level.
1744 * Also, we've got to be careful not to trash gate
1745 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1746 */
1747 for (irq = 0; irq < NR_IRQS ; irq++) {
1748 int tmp = irq;
1749 if (use_pci_vector()) {
1750 if (!platform_legacy_irq(tmp))
1751 if ((tmp = vector_to_irq(tmp)) == -1)
1752 continue;
1754 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1755 /*
1756 * Hmm.. We don't have an entry for this,
1757 * so default to an old-fashioned 8259
1758 * interrupt if we can..
1759 */
1760 if (irq < 16)
1761 make_8259A_irq(irq);
1762 #ifndef CONFIG_XEN
1763 else
1764 /* Strange. Oh, well.. */
1765 irq_desc[irq].chip = &no_irq_type;
1766 #endif
1771 #ifndef CONFIG_XEN
1772 static void enable_lapic_irq (unsigned int irq)
1774 unsigned long v;
1776 v = apic_read(APIC_LVT0);
1777 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1780 static void disable_lapic_irq (unsigned int irq)
1782 unsigned long v;
1784 v = apic_read(APIC_LVT0);
1785 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1788 static void ack_lapic_irq (unsigned int irq)
1790 ack_APIC_irq();
1793 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1795 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1796 .typename = "local-APIC-edge",
1797 .startup = NULL, /* startup_irq() not used for IRQ0 */
1798 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1799 .enable = enable_lapic_irq,
1800 .disable = disable_lapic_irq,
1801 .ack = ack_lapic_irq,
1802 .end = end_lapic_irq,
1803 };
1805 static void setup_nmi (void)
1807 /*
1808 * Dirty trick to enable the NMI watchdog ...
1809 * We put the 8259A master into AEOI mode and
1810 * unmask on all local APICs LVT0 as NMI.
1812 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1813 * is from Maciej W. Rozycki - so we do not have to EOI from
1814 * the NMI handler or the timer interrupt.
1815 */
1816 printk(KERN_INFO "activating NMI Watchdog ...");
1818 enable_NMI_through_LVT0(NULL);
1820 printk(" done.\n");
1823 /*
1824 * This looks a bit hackish but it's about the only one way of sending
1825 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1826 * not support the ExtINT mode, unfortunately. We need to send these
1827 * cycles as some i82489DX-based boards have glue logic that keeps the
1828 * 8259A interrupt line asserted until INTA. --macro
1829 */
1830 static inline void unlock_ExtINT_logic(void)
1832 int apic, pin, i;
1833 struct IO_APIC_route_entry entry0, entry1;
1834 unsigned char save_control, save_freq_select;
1835 unsigned long flags;
1837 pin = find_isa_irq_pin(8, mp_INT);
1838 apic = find_isa_irq_apic(8, mp_INT);
1839 if (pin == -1)
1840 return;
1842 spin_lock_irqsave(&ioapic_lock, flags);
1843 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1844 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1845 spin_unlock_irqrestore(&ioapic_lock, flags);
1846 clear_IO_APIC_pin(apic, pin);
1848 memset(&entry1, 0, sizeof(entry1));
1850 entry1.dest_mode = 0; /* physical delivery */
1851 entry1.mask = 0; /* unmask IRQ now */
1852 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1853 entry1.delivery_mode = dest_ExtINT;
1854 entry1.polarity = entry0.polarity;
1855 entry1.trigger = 0;
1856 entry1.vector = 0;
1858 spin_lock_irqsave(&ioapic_lock, flags);
1859 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1860 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1861 spin_unlock_irqrestore(&ioapic_lock, flags);
1863 save_control = CMOS_READ(RTC_CONTROL);
1864 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1865 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1866 RTC_FREQ_SELECT);
1867 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1869 i = 100;
1870 while (i-- > 0) {
1871 mdelay(10);
1872 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1873 i -= 10;
1876 CMOS_WRITE(save_control, RTC_CONTROL);
1877 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1878 clear_IO_APIC_pin(apic, pin);
1880 spin_lock_irqsave(&ioapic_lock, flags);
1881 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1882 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1883 spin_unlock_irqrestore(&ioapic_lock, flags);
1886 int timer_uses_ioapic_pin_0;
1888 /*
1889 * This code may look a bit paranoid, but it's supposed to cooperate with
1890 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1891 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1892 * fanatically on his truly buggy board.
1894 * FIXME: really need to revamp this for modern platforms only.
1895 */
1896 static inline void check_timer(void)
1898 int apic1, pin1, apic2, pin2;
1899 int vector;
1901 /*
1902 * get/set the timer IRQ vector:
1903 */
1904 disable_8259A_irq(0);
1905 vector = assign_irq_vector(0);
1906 set_intr_gate(vector, interrupt[0]);
1908 /*
1909 * Subtle, code in do_timer_interrupt() expects an AEOI
1910 * mode for the 8259A whenever interrupts are routed
1911 * through I/O APICs. Also IRQ0 has to be enabled in
1912 * the 8259A which implies the virtual wire has to be
1913 * disabled in the local APIC.
1914 */
1915 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1916 init_8259A(1);
1917 if (timer_over_8254 > 0)
1918 enable_8259A_irq(0);
1920 pin1 = find_isa_irq_pin(0, mp_INT);
1921 apic1 = find_isa_irq_apic(0, mp_INT);
1922 pin2 = ioapic_i8259.pin;
1923 apic2 = ioapic_i8259.apic;
1925 if (pin1 == 0)
1926 timer_uses_ioapic_pin_0 = 1;
1928 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1929 vector, apic1, pin1, apic2, pin2);
1931 if (pin1 != -1) {
1932 /*
1933 * Ok, does IRQ0 through the IOAPIC work?
1934 */
1935 unmask_IO_APIC_irq(0);
1936 if (!no_timer_check && timer_irq_works()) {
1937 nmi_watchdog_default();
1938 if (nmi_watchdog == NMI_IO_APIC) {
1939 disable_8259A_irq(0);
1940 setup_nmi();
1941 enable_8259A_irq(0);
1943 if (disable_timer_pin_1 > 0)
1944 clear_IO_APIC_pin(0, pin1);
1945 return;
1947 clear_IO_APIC_pin(apic1, pin1);
1948 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1949 "connected to IO-APIC\n");
1952 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1953 "through the 8259A ... ");
1954 if (pin2 != -1) {
1955 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1956 apic2, pin2);
1957 /*
1958 * legacy devices should be connected to IO APIC #0
1959 */
1960 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1961 if (timer_irq_works()) {
1962 apic_printk(APIC_VERBOSE," works.\n");
1963 nmi_watchdog_default();
1964 if (nmi_watchdog == NMI_IO_APIC) {
1965 setup_nmi();
1967 return;
1969 /*
1970 * Cleanup, just in case ...
1971 */
1972 clear_IO_APIC_pin(apic2, pin2);
1974 apic_printk(APIC_VERBOSE," failed.\n");
1976 if (nmi_watchdog == NMI_IO_APIC) {
1977 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1978 nmi_watchdog = 0;
1981 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1983 disable_8259A_irq(0);
1984 irq_desc[0].chip = &lapic_irq_type;
1985 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1986 enable_8259A_irq(0);
1988 if (timer_irq_works()) {
1989 apic_printk(APIC_VERBOSE," works.\n");
1990 return;
1992 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1993 apic_printk(APIC_VERBOSE," failed.\n");
1995 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1997 init_8259A(0);
1998 make_8259A_irq(0);
1999 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2001 unlock_ExtINT_logic();
2003 if (timer_irq_works()) {
2004 apic_printk(APIC_VERBOSE," works.\n");
2005 return;
2007 apic_printk(APIC_VERBOSE," failed :(.\n");
2008 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
2010 #else
2011 #define check_timer() ((void)0)
2012 int timer_uses_ioapic_pin_0 = 0;
2013 #endif /* !CONFIG_XEN */
2015 static int __init notimercheck(char *s)
2017 no_timer_check = 1;
2018 return 1;
2020 __setup("no_timer_check", notimercheck);
2022 /*
2024 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2025 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2026 * Linux doesn't really care, as it's not actually used
2027 * for any interrupt handling anyway.
2028 */
2029 #define PIC_IRQS (1<<2)
2031 void __init setup_IO_APIC(void)
2033 enable_IO_APIC();
2035 if (acpi_ioapic)
2036 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2037 else
2038 io_apic_irqs = ~PIC_IRQS;
2040 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2042 /*
2043 * Set up the IO-APIC IRQ routing table.
2044 */
2045 if (!acpi_ioapic)
2046 setup_ioapic_ids_from_mpc();
2047 #ifndef CONFIG_XEN
2048 sync_Arb_IDs();
2049 #endif /* !CONFIG_XEN */
2050 setup_IO_APIC_irqs();
2051 init_IO_APIC_traps();
2052 check_timer();
2053 if (!acpi_ioapic)
2054 print_IO_APIC();
2057 #ifndef CONFIG_XEN
2059 struct sysfs_ioapic_data {
2060 struct sys_device dev;
2061 struct IO_APIC_route_entry entry[0];
2062 };
2063 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2065 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2067 struct IO_APIC_route_entry *entry;
2068 struct sysfs_ioapic_data *data;
2069 unsigned long flags;
2070 int i;
2072 data = container_of(dev, struct sysfs_ioapic_data, dev);
2073 entry = data->entry;
2074 spin_lock_irqsave(&ioapic_lock, flags);
2075 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2076 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2077 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2079 spin_unlock_irqrestore(&ioapic_lock, flags);
2081 return 0;
2084 static int ioapic_resume(struct sys_device *dev)
2086 struct IO_APIC_route_entry *entry;
2087 struct sysfs_ioapic_data *data;
2088 unsigned long flags;
2089 union IO_APIC_reg_00 reg_00;
2090 int i;
2092 data = container_of(dev, struct sysfs_ioapic_data, dev);
2093 entry = data->entry;
2095 spin_lock_irqsave(&ioapic_lock, flags);
2096 reg_00.raw = io_apic_read(dev->id, 0);
2097 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2098 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2099 io_apic_write(dev->id, 0, reg_00.raw);
2101 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2102 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2103 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2105 spin_unlock_irqrestore(&ioapic_lock, flags);
2107 return 0;
2110 static struct sysdev_class ioapic_sysdev_class = {
2111 set_kset_name("ioapic"),
2112 .suspend = ioapic_suspend,
2113 .resume = ioapic_resume,
2114 };
2116 static int __init ioapic_init_sysfs(void)
2118 struct sys_device * dev;
2119 int i, size, error = 0;
2121 error = sysdev_class_register(&ioapic_sysdev_class);
2122 if (error)
2123 return error;
2125 for (i = 0; i < nr_ioapics; i++ ) {
2126 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2127 * sizeof(struct IO_APIC_route_entry);
2128 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2129 if (!mp_ioapic_data[i]) {
2130 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2131 continue;
2133 memset(mp_ioapic_data[i], 0, size);
2134 dev = &mp_ioapic_data[i]->dev;
2135 dev->id = i;
2136 dev->cls = &ioapic_sysdev_class;
2137 error = sysdev_register(dev);
2138 if (error) {
2139 kfree(mp_ioapic_data[i]);
2140 mp_ioapic_data[i] = NULL;
2141 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2142 continue;
2146 return 0;
2149 device_initcall(ioapic_init_sysfs);
2151 #endif /* CONFIG_XEN */
2153 /* --------------------------------------------------------------------------
2154 ACPI-based IOAPIC Configuration
2155 -------------------------------------------------------------------------- */
2157 #ifdef CONFIG_ACPI
2159 #define IO_APIC_MAX_ID 0xFE
2161 int __init io_apic_get_version (int ioapic)
2163 union IO_APIC_reg_01 reg_01;
2164 unsigned long flags;
2166 spin_lock_irqsave(&ioapic_lock, flags);
2167 reg_01.raw = io_apic_read(ioapic, 1);
2168 spin_unlock_irqrestore(&ioapic_lock, flags);
2170 return reg_01.bits.version;
2174 int __init io_apic_get_redir_entries (int ioapic)
2176 union IO_APIC_reg_01 reg_01;
2177 unsigned long flags;
2179 spin_lock_irqsave(&ioapic_lock, flags);
2180 reg_01.raw = io_apic_read(ioapic, 1);
2181 spin_unlock_irqrestore(&ioapic_lock, flags);
2183 return reg_01.bits.entries;
2187 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2189 struct IO_APIC_route_entry entry;
2190 unsigned long flags;
2192 if (!IO_APIC_IRQ(irq)) {
2193 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2194 ioapic);
2195 return -EINVAL;
2198 /*
2199 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2200 * Note that we mask (disable) IRQs now -- these get enabled when the
2201 * corresponding device driver registers for this IRQ.
2202 */
2204 memset(&entry,0,sizeof(entry));
2206 entry.delivery_mode = INT_DELIVERY_MODE;
2207 entry.dest_mode = INT_DEST_MODE;
2208 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2209 entry.trigger = edge_level;
2210 entry.polarity = active_high_low;
2211 entry.mask = 1; /* Disabled (masked) */
2213 irq = gsi_irq_sharing(irq);
2214 /*
2215 * IRQs < 16 are already in the irq_2_pin[] map
2216 */
2217 if (irq >= 16)
2218 add_pin_to_irq(irq, ioapic, pin);
2220 entry.vector = assign_irq_vector(irq);
2222 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2223 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2224 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2225 edge_level, active_high_low);
2227 ioapic_register_intr(irq, entry.vector, edge_level);
2229 if (!ioapic && (irq < 16))
2230 disable_8259A_irq(irq);
2232 spin_lock_irqsave(&ioapic_lock, flags);
2233 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2234 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2235 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2236 spin_unlock_irqrestore(&ioapic_lock, flags);
2238 return 0;
2241 #endif /* CONFIG_ACPI */
2244 #ifndef CONFIG_XEN
2245 /*
2246 * This function currently is only a helper for the i386 smp boot process where
2247 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2248 * so mask in all cases should simply be TARGET_CPUS
2249 */
2250 #ifdef CONFIG_SMP
2251 void __init setup_ioapic_dest(void)
2253 int pin, ioapic, irq, irq_entry;
2255 if (skip_ioapic_setup == 1)
2256 return;
2258 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2259 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2260 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2261 if (irq_entry == -1)
2262 continue;
2263 irq = pin_2_irq(irq_entry, ioapic, pin);
2264 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2269 #endif
2270 #endif /* !CONFIG_XEN */