ia64/linux-2.6.18-xen.hg

view arch/i386/kernel/io_apic-xen.c @ 749:2892ca2b9c17

linux/x86: cleanup IO-APIC code

- get 32-bit code in sync with 64-bit wrt ExtINT pin detection being
unnecessary
- eliminate build warnings resulting from c/s 725

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Nov 28 13:31:21 2008 +0000 (2008-11-28)
parents 69694615aebb
children 2f1b770d84e5
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
35 #include <asm/io.h>
36 #include <asm/smp.h>
37 #include <asm/desc.h>
38 #include <asm/timer.h>
39 #include <asm/i8259.h>
40 #include <asm/nmi.h>
42 #include <mach_apic.h>
44 #include "io_ports.h"
46 #ifdef CONFIG_XEN
48 #include <xen/interface/xen.h>
49 #include <xen/interface/physdev.h>
50 #include <xen/evtchn.h>
52 /* Fake i8259 */
53 #define make_8259A_irq(_irq) (io_apic_irqs &= ~(1UL<<(_irq)))
54 #define disable_8259A_irq(_irq) ((void)0)
55 #define i8259A_irq_pending(_irq) (0)
57 unsigned long io_apic_irqs;
59 static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
60 {
61 struct physdev_apic apic_op;
62 int ret;
64 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
65 apic_op.reg = reg;
66 ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
67 if (ret)
68 return ret;
69 return apic_op.value;
70 }
72 static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
73 {
74 struct physdev_apic apic_op;
76 apic_op.apic_physbase = mp_ioapics[apic].mpc_apicaddr;
77 apic_op.reg = reg;
78 apic_op.value = value;
79 WARN_ON(HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op));
80 }
82 #define io_apic_read(a,r) xen_io_apic_read(a,r)
83 #define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
85 #endif /* CONFIG_XEN */
87 int (*ioapic_renumber_irq)(int ioapic, int irq);
88 atomic_t irq_mis_count;
90 #ifndef CONFIG_XEN
91 /* Where if anywhere is the i8259 connect in external int mode */
92 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
93 #endif
95 static DEFINE_SPINLOCK(ioapic_lock);
96 static DEFINE_SPINLOCK(vector_lock);
98 int timer_over_8254 __initdata = 1;
100 /*
101 * Is the SiS APIC rmw bug present ?
102 * -1 = don't know, 0 = no, 1 = yes
103 */
104 int sis_apic_bug = -1;
106 /*
107 * # of IRQ routing registers
108 */
109 int nr_ioapic_registers[MAX_IO_APICS];
111 int disable_timer_pin_1 __initdata;
113 /*
114 * Rough estimation of how many shared IRQs there are, can
115 * be changed anytime.
116 */
117 #define MAX_PLUS_SHARED_IRQS NR_IRQS
118 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
120 /*
121 * This is performance-critical, we want to do it O(1)
122 *
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
125 */
127 static struct irq_pin_list {
128 int apic, pin, next;
129 } irq_2_pin[PIN_MAP_SIZE];
131 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
132 #ifdef CONFIG_PCI_MSI
133 #define vector_to_irq(vector) \
134 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
135 #else
136 #define vector_to_irq(vector) (vector)
137 #endif
139 /*
140 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
141 * shared ISA-space IRQs, so we have to support them. We are super
142 * fast in the common case, and fast for shared ISA-space IRQs.
143 */
144 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
145 {
146 static int first_free_entry = NR_IRQS;
147 struct irq_pin_list *entry = irq_2_pin + irq;
149 while (entry->next)
150 entry = irq_2_pin + entry->next;
152 if (entry->pin != -1) {
153 entry->next = first_free_entry;
154 entry = irq_2_pin + entry->next;
155 if (++first_free_entry >= PIN_MAP_SIZE)
156 panic("io_apic.c: whoops");
157 }
158 entry->apic = apic;
159 entry->pin = pin;
160 }
162 #ifdef CONFIG_XEN
163 #define clear_IO_APIC() ((void)0)
164 #else
165 /*
166 * Reroute an IRQ to a different pin.
167 */
168 static void __init replace_pin_at_irq(unsigned int irq,
169 int oldapic, int oldpin,
170 int newapic, int newpin)
171 {
172 struct irq_pin_list *entry = irq_2_pin + irq;
174 while (1) {
175 if (entry->apic == oldapic && entry->pin == oldpin) {
176 entry->apic = newapic;
177 entry->pin = newpin;
178 }
179 if (!entry->next)
180 break;
181 entry = irq_2_pin + entry->next;
182 }
183 }
185 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
186 {
187 struct irq_pin_list *entry = irq_2_pin + irq;
188 unsigned int pin, reg;
190 for (;;) {
191 pin = entry->pin;
192 if (pin == -1)
193 break;
194 reg = io_apic_read(entry->apic, 0x10 + pin*2);
195 reg &= ~disable;
196 reg |= enable;
197 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
198 if (!entry->next)
199 break;
200 entry = irq_2_pin + entry->next;
201 }
202 }
204 /* mask = 1 */
205 static void __mask_IO_APIC_irq (unsigned int irq)
206 {
207 __modify_IO_APIC_irq(irq, 0x00010000, 0);
208 }
210 /* mask = 0 */
211 static void __unmask_IO_APIC_irq (unsigned int irq)
212 {
213 __modify_IO_APIC_irq(irq, 0, 0x00010000);
214 }
216 /* mask = 1, trigger = 0 */
217 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
218 {
219 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
220 }
222 /* mask = 0, trigger = 1 */
223 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
224 {
225 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
226 }
228 static void mask_IO_APIC_irq (unsigned int irq)
229 {
230 unsigned long flags;
232 spin_lock_irqsave(&ioapic_lock, flags);
233 __mask_IO_APIC_irq(irq);
234 spin_unlock_irqrestore(&ioapic_lock, flags);
235 }
237 static void unmask_IO_APIC_irq (unsigned int irq)
238 {
239 unsigned long flags;
241 spin_lock_irqsave(&ioapic_lock, flags);
242 __unmask_IO_APIC_irq(irq);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
244 }
246 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
247 {
248 struct IO_APIC_route_entry entry;
249 unsigned long flags;
251 /* Check delivery_mode to be sure we're not clearing an SMI pin */
252 spin_lock_irqsave(&ioapic_lock, flags);
253 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
254 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
255 spin_unlock_irqrestore(&ioapic_lock, flags);
256 if (entry.delivery_mode == dest_SMI)
257 return;
259 /*
260 * Disable it in the IO-APIC irq-routing table:
261 */
262 memset(&entry, 0, sizeof(entry));
263 entry.mask = 1;
264 spin_lock_irqsave(&ioapic_lock, flags);
265 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
266 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
267 spin_unlock_irqrestore(&ioapic_lock, flags);
268 }
270 static void clear_IO_APIC (void)
271 {
272 int apic, pin;
274 for (apic = 0; apic < nr_ioapics; apic++)
275 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
276 clear_IO_APIC_pin(apic, pin);
277 }
279 #ifdef CONFIG_SMP
280 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
281 {
282 unsigned long flags;
283 int pin;
284 struct irq_pin_list *entry = irq_2_pin + irq;
285 unsigned int apicid_value;
286 cpumask_t tmp;
288 cpus_and(tmp, cpumask, cpu_online_map);
289 if (cpus_empty(tmp))
290 tmp = TARGET_CPUS;
292 cpus_and(cpumask, tmp, CPU_MASK_ALL);
294 apicid_value = cpu_mask_to_apicid(cpumask);
295 /* Prepare to do the io_apic_write */
296 apicid_value = apicid_value << 24;
297 spin_lock_irqsave(&ioapic_lock, flags);
298 for (;;) {
299 pin = entry->pin;
300 if (pin == -1)
301 break;
302 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
303 if (!entry->next)
304 break;
305 entry = irq_2_pin + entry->next;
306 }
307 set_irq_info(irq, cpumask);
308 spin_unlock_irqrestore(&ioapic_lock, flags);
309 }
311 #if defined(CONFIG_IRQBALANCE)
312 # include <asm/processor.h> /* kernel_thread() */
313 # include <linux/kernel_stat.h> /* kstat */
314 # include <linux/slab.h> /* kmalloc() */
315 # include <linux/timer.h> /* time_after() */
317 #ifdef CONFIG_BALANCED_IRQ_DEBUG
318 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
319 # define Dprintk(x...) do { TDprintk(x); } while (0)
320 # else
321 # define TDprintk(x...)
322 # define Dprintk(x...)
323 # endif
325 #define IRQBALANCE_CHECK_ARCH -999
326 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
327 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
328 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
329 #define BALANCED_IRQ_LESS_DELTA (HZ)
331 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
332 static int physical_balance __read_mostly;
333 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
335 static struct irq_cpu_info {
336 unsigned long * last_irq;
337 unsigned long * irq_delta;
338 unsigned long irq;
339 } irq_cpu_data[NR_CPUS];
341 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
342 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
343 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
345 #define IDLE_ENOUGH(cpu,now) \
346 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
348 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
350 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
352 static cpumask_t balance_irq_affinity[NR_IRQS] = {
353 [0 ... NR_IRQS-1] = CPU_MASK_ALL
354 };
356 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
357 {
358 balance_irq_affinity[irq] = mask;
359 }
361 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
362 unsigned long now, int direction)
363 {
364 int search_idle = 1;
365 int cpu = curr_cpu;
367 goto inside;
369 do {
370 if (unlikely(cpu == curr_cpu))
371 search_idle = 0;
372 inside:
373 if (direction == 1) {
374 cpu++;
375 if (cpu >= NR_CPUS)
376 cpu = 0;
377 } else {
378 cpu--;
379 if (cpu == -1)
380 cpu = NR_CPUS-1;
381 }
382 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
383 (search_idle && !IDLE_ENOUGH(cpu,now)));
385 return cpu;
386 }
388 static inline void balance_irq(int cpu, int irq)
389 {
390 unsigned long now = jiffies;
391 cpumask_t allowed_mask;
392 unsigned int new_cpu;
394 if (irqbalance_disabled)
395 return;
397 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
398 new_cpu = move(cpu, allowed_mask, now, 1);
399 if (cpu != new_cpu) {
400 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
401 }
402 }
404 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
405 {
406 int i, j;
407 Dprintk("Rotating IRQs among CPUs.\n");
408 for_each_online_cpu(i) {
409 for (j = 0; j < NR_IRQS; j++) {
410 if (!irq_desc[j].action)
411 continue;
412 /* Is it a significant load ? */
413 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
414 useful_load_threshold)
415 continue;
416 balance_irq(i, j);
417 }
418 }
419 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
420 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
421 return;
422 }
424 static void do_irq_balance(void)
425 {
426 int i, j;
427 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
428 unsigned long move_this_load = 0;
429 int max_loaded = 0, min_loaded = 0;
430 int load;
431 unsigned long useful_load_threshold = balanced_irq_interval + 10;
432 int selected_irq;
433 int tmp_loaded, first_attempt = 1;
434 unsigned long tmp_cpu_irq;
435 unsigned long imbalance = 0;
436 cpumask_t allowed_mask, target_cpu_mask, tmp;
438 for_each_possible_cpu(i) {
439 int package_index;
440 CPU_IRQ(i) = 0;
441 if (!cpu_online(i))
442 continue;
443 package_index = CPU_TO_PACKAGEINDEX(i);
444 for (j = 0; j < NR_IRQS; j++) {
445 unsigned long value_now, delta;
446 /* Is this an active IRQ? */
447 if (!irq_desc[j].action)
448 continue;
449 if ( package_index == i )
450 IRQ_DELTA(package_index,j) = 0;
451 /* Determine the total count per processor per IRQ */
452 value_now = (unsigned long) kstat_cpu(i).irqs[j];
454 /* Determine the activity per processor per IRQ */
455 delta = value_now - LAST_CPU_IRQ(i,j);
457 /* Update last_cpu_irq[][] for the next time */
458 LAST_CPU_IRQ(i,j) = value_now;
460 /* Ignore IRQs whose rate is less than the clock */
461 if (delta < useful_load_threshold)
462 continue;
463 /* update the load for the processor or package total */
464 IRQ_DELTA(package_index,j) += delta;
466 /* Keep track of the higher numbered sibling as well */
467 if (i != package_index)
468 CPU_IRQ(i) += delta;
469 /*
470 * We have sibling A and sibling B in the package
471 *
472 * cpu_irq[A] = load for cpu A + load for cpu B
473 * cpu_irq[B] = load for cpu B
474 */
475 CPU_IRQ(package_index) += delta;
476 }
477 }
478 /* Find the least loaded processor package */
479 for_each_online_cpu(i) {
480 if (i != CPU_TO_PACKAGEINDEX(i))
481 continue;
482 if (min_cpu_irq > CPU_IRQ(i)) {
483 min_cpu_irq = CPU_IRQ(i);
484 min_loaded = i;
485 }
486 }
487 max_cpu_irq = ULONG_MAX;
489 tryanothercpu:
490 /* Look for heaviest loaded processor.
491 * We may come back to get the next heaviest loaded processor.
492 * Skip processors with trivial loads.
493 */
494 tmp_cpu_irq = 0;
495 tmp_loaded = -1;
496 for_each_online_cpu(i) {
497 if (i != CPU_TO_PACKAGEINDEX(i))
498 continue;
499 if (max_cpu_irq <= CPU_IRQ(i))
500 continue;
501 if (tmp_cpu_irq < CPU_IRQ(i)) {
502 tmp_cpu_irq = CPU_IRQ(i);
503 tmp_loaded = i;
504 }
505 }
507 if (tmp_loaded == -1) {
508 /* In the case of small number of heavy interrupt sources,
509 * loading some of the cpus too much. We use Ingo's original
510 * approach to rotate them around.
511 */
512 if (!first_attempt && imbalance >= useful_load_threshold) {
513 rotate_irqs_among_cpus(useful_load_threshold);
514 return;
515 }
516 goto not_worth_the_effort;
517 }
519 first_attempt = 0; /* heaviest search */
520 max_cpu_irq = tmp_cpu_irq; /* load */
521 max_loaded = tmp_loaded; /* processor */
522 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
524 Dprintk("max_loaded cpu = %d\n", max_loaded);
525 Dprintk("min_loaded cpu = %d\n", min_loaded);
526 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
527 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
528 Dprintk("load imbalance = %lu\n", imbalance);
530 /* if imbalance is less than approx 10% of max load, then
531 * observe diminishing returns action. - quit
532 */
533 if (imbalance < (max_cpu_irq >> 3)) {
534 Dprintk("Imbalance too trivial\n");
535 goto not_worth_the_effort;
536 }
538 tryanotherirq:
539 /* if we select an IRQ to move that can't go where we want, then
540 * see if there is another one to try.
541 */
542 move_this_load = 0;
543 selected_irq = -1;
544 for (j = 0; j < NR_IRQS; j++) {
545 /* Is this an active IRQ? */
546 if (!irq_desc[j].action)
547 continue;
548 if (imbalance <= IRQ_DELTA(max_loaded,j))
549 continue;
550 /* Try to find the IRQ that is closest to the imbalance
551 * without going over.
552 */
553 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
554 move_this_load = IRQ_DELTA(max_loaded,j);
555 selected_irq = j;
556 }
557 }
558 if (selected_irq == -1) {
559 goto tryanothercpu;
560 }
562 imbalance = move_this_load;
564 /* For physical_balance case, we accumlated both load
565 * values in the one of the siblings cpu_irq[],
566 * to use the same code for physical and logical processors
567 * as much as possible.
568 *
569 * NOTE: the cpu_irq[] array holds the sum of the load for
570 * sibling A and sibling B in the slot for the lowest numbered
571 * sibling (A), _AND_ the load for sibling B in the slot for
572 * the higher numbered sibling.
573 *
574 * We seek the least loaded sibling by making the comparison
575 * (A+B)/2 vs B
576 */
577 load = CPU_IRQ(min_loaded) >> 1;
578 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
579 if (load > CPU_IRQ(j)) {
580 /* This won't change cpu_sibling_map[min_loaded] */
581 load = CPU_IRQ(j);
582 min_loaded = j;
583 }
584 }
586 cpus_and(allowed_mask,
587 cpu_online_map,
588 balance_irq_affinity[selected_irq]);
589 target_cpu_mask = cpumask_of_cpu(min_loaded);
590 cpus_and(tmp, target_cpu_mask, allowed_mask);
592 if (!cpus_empty(tmp)) {
594 Dprintk("irq = %d moved to cpu = %d\n",
595 selected_irq, min_loaded);
596 /* mark for change destination */
597 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
599 /* Since we made a change, come back sooner to
600 * check for more variation.
601 */
602 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
603 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
604 return;
605 }
606 goto tryanotherirq;
608 not_worth_the_effort:
609 /*
610 * if we did not find an IRQ to move, then adjust the time interval
611 * upward
612 */
613 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
614 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
615 Dprintk("IRQ worth rotating not found\n");
616 return;
617 }
619 static int balanced_irq(void *unused)
620 {
621 int i;
622 unsigned long prev_balance_time = jiffies;
623 long time_remaining = balanced_irq_interval;
625 daemonize("kirqd");
627 /* push everything to CPU 0 to give us a starting point. */
628 for (i = 0 ; i < NR_IRQS ; i++) {
629 irq_desc[i].pending_mask = cpumask_of_cpu(0);
630 set_pending_irq(i, cpumask_of_cpu(0));
631 }
633 for ( ; ; ) {
634 time_remaining = schedule_timeout_interruptible(time_remaining);
635 try_to_freeze();
636 if (time_after(jiffies,
637 prev_balance_time+balanced_irq_interval)) {
638 preempt_disable();
639 do_irq_balance();
640 prev_balance_time = jiffies;
641 time_remaining = balanced_irq_interval;
642 preempt_enable();
643 }
644 }
645 return 0;
646 }
648 static int __init balanced_irq_init(void)
649 {
650 int i;
651 struct cpuinfo_x86 *c;
652 cpumask_t tmp;
654 cpus_shift_right(tmp, cpu_online_map, 2);
655 c = &boot_cpu_data;
656 /* When not overwritten by the command line ask subarchitecture. */
657 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
658 irqbalance_disabled = NO_BALANCE_IRQ;
659 if (irqbalance_disabled)
660 return 0;
662 /* disable irqbalance completely if there is only one processor online */
663 if (num_online_cpus() < 2) {
664 irqbalance_disabled = 1;
665 return 0;
666 }
667 /*
668 * Enable physical balance only if more than 1 physical processor
669 * is present
670 */
671 if (smp_num_siblings > 1 && !cpus_empty(tmp))
672 physical_balance = 1;
674 for_each_online_cpu(i) {
675 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
676 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
677 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
678 printk(KERN_ERR "balanced_irq_init: out of memory");
679 goto failed;
680 }
681 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
682 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
683 }
685 printk(KERN_INFO "Starting balanced_irq\n");
686 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
687 return 0;
688 else
689 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
690 failed:
691 for_each_possible_cpu(i) {
692 kfree(irq_cpu_data[i].irq_delta);
693 irq_cpu_data[i].irq_delta = NULL;
694 kfree(irq_cpu_data[i].last_irq);
695 irq_cpu_data[i].last_irq = NULL;
696 }
697 return 0;
698 }
700 int __init irqbalance_disable(char *str)
701 {
702 irqbalance_disabled = 1;
703 return 1;
704 }
706 __setup("noirqbalance", irqbalance_disable);
708 late_initcall(balanced_irq_init);
709 #endif /* CONFIG_IRQBALANCE */
710 #endif /* CONFIG_SMP */
711 #endif
713 #ifndef CONFIG_SMP
714 void fastcall send_IPI_self(int vector)
715 {
716 #ifndef CONFIG_XEN
717 unsigned int cfg;
719 /*
720 * Wait for idle.
721 */
722 apic_wait_icr_idle();
723 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
724 /*
725 * Send the IPI. The write to APIC_ICR fires this off.
726 */
727 apic_write_around(APIC_ICR, cfg);
728 #endif
729 }
730 #endif /* !CONFIG_SMP */
733 /*
734 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
735 * specific CPU-side IRQs.
736 */
738 #define MAX_PIRQS 8
739 static int pirq_entries [MAX_PIRQS];
740 static int pirqs_enabled;
741 int skip_ioapic_setup;
743 static int __init ioapic_setup(char *str)
744 {
745 skip_ioapic_setup = 1;
746 return 1;
747 }
749 __setup("noapic", ioapic_setup);
751 static int __init ioapic_pirq_setup(char *str)
752 {
753 int i, max;
754 int ints[MAX_PIRQS+1];
756 get_options(str, ARRAY_SIZE(ints), ints);
758 for (i = 0; i < MAX_PIRQS; i++)
759 pirq_entries[i] = -1;
761 pirqs_enabled = 1;
762 apic_printk(APIC_VERBOSE, KERN_INFO
763 "PIRQ redirection, working around broken MP-BIOS.\n");
764 max = MAX_PIRQS;
765 if (ints[0] < MAX_PIRQS)
766 max = ints[0];
768 for (i = 0; i < max; i++) {
769 apic_printk(APIC_VERBOSE, KERN_DEBUG
770 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
771 /*
772 * PIRQs are mapped upside down, usually.
773 */
774 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
775 }
776 return 1;
777 }
779 __setup("pirq=", ioapic_pirq_setup);
781 /*
782 * Find the IRQ entry number of a certain pin.
783 */
784 static int find_irq_entry(int apic, int pin, int type)
785 {
786 int i;
788 for (i = 0; i < mp_irq_entries; i++)
789 if (mp_irqs[i].mpc_irqtype == type &&
790 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
791 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
792 mp_irqs[i].mpc_dstirq == pin)
793 return i;
795 return -1;
796 }
798 #ifndef CONFIG_XEN
799 /*
800 * Find the pin to which IRQ[irq] (ISA) is connected
801 */
802 static int __init find_isa_irq_pin(int irq, int type)
803 {
804 int i;
806 for (i = 0; i < mp_irq_entries; i++) {
807 int lbus = mp_irqs[i].mpc_srcbus;
809 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
810 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
811 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
812 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
813 ) &&
814 (mp_irqs[i].mpc_irqtype == type) &&
815 (mp_irqs[i].mpc_srcbusirq == irq))
817 return mp_irqs[i].mpc_dstirq;
818 }
819 return -1;
820 }
822 static int __init find_isa_irq_apic(int irq, int type)
823 {
824 int i;
826 for (i = 0; i < mp_irq_entries; i++) {
827 int lbus = mp_irqs[i].mpc_srcbus;
829 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
830 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
831 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
832 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
833 ) &&
834 (mp_irqs[i].mpc_irqtype == type) &&
835 (mp_irqs[i].mpc_srcbusirq == irq))
836 break;
837 }
838 if (i < mp_irq_entries) {
839 int apic;
840 for(apic = 0; apic < nr_ioapics; apic++) {
841 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
842 return apic;
843 }
844 }
846 return -1;
847 }
848 #endif
850 /*
851 * Find a specific PCI IRQ entry.
852 * Not an __init, possibly needed by modules
853 */
854 static int pin_2_irq(int idx, int apic, int pin);
856 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
857 {
858 int apic, i, best_guess = -1;
860 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
861 "slot:%d, pin:%d.\n", bus, slot, pin);
862 if (mp_bus_id_to_pci_bus[bus] == -1) {
863 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
864 return -1;
865 }
866 for (i = 0; i < mp_irq_entries; i++) {
867 int lbus = mp_irqs[i].mpc_srcbus;
869 for (apic = 0; apic < nr_ioapics; apic++)
870 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
871 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
872 break;
874 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
875 !mp_irqs[i].mpc_irqtype &&
876 (bus == lbus) &&
877 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
878 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
880 if (!(apic || IO_APIC_IRQ(irq)))
881 continue;
883 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
884 return irq;
885 /*
886 * Use the first all-but-pin matching entry as a
887 * best-guess fuzzy result for broken mptables.
888 */
889 if (best_guess < 0)
890 best_guess = irq;
891 }
892 }
893 return best_guess;
894 }
895 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
897 /*
898 * This function currently is only a helper for the i386 smp boot process where
899 * we need to reprogram the ioredtbls to cater for the cpus which have come online
900 * so mask in all cases should simply be TARGET_CPUS
901 */
902 #ifdef CONFIG_SMP
903 #ifndef CONFIG_XEN
904 void __init setup_ioapic_dest(void)
905 {
906 int pin, ioapic, irq, irq_entry;
908 if (skip_ioapic_setup == 1)
909 return;
911 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
912 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
913 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
914 if (irq_entry == -1)
915 continue;
916 irq = pin_2_irq(irq_entry, ioapic, pin);
917 set_ioapic_affinity_irq(irq, TARGET_CPUS);
918 }
920 }
921 }
922 #endif /* !CONFIG_XEN */
923 #endif
925 /*
926 * EISA Edge/Level control register, ELCR
927 */
928 static int EISA_ELCR(unsigned int irq)
929 {
930 if (irq < 16) {
931 unsigned int port = 0x4d0 + (irq >> 3);
932 return (inb(port) >> (irq & 7)) & 1;
933 }
934 apic_printk(APIC_VERBOSE, KERN_INFO
935 "Broken MPtable reports ISA irq %d\n", irq);
936 return 0;
937 }
939 /* EISA interrupts are always polarity zero and can be edge or level
940 * trigger depending on the ELCR value. If an interrupt is listed as
941 * EISA conforming in the MP table, that means its trigger type must
942 * be read in from the ELCR */
944 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
945 #define default_EISA_polarity(idx) (0)
947 /* ISA interrupts are always polarity zero edge triggered,
948 * when listed as conforming in the MP table. */
950 #define default_ISA_trigger(idx) (0)
951 #define default_ISA_polarity(idx) (0)
953 /* PCI interrupts are always polarity one level triggered,
954 * when listed as conforming in the MP table. */
956 #define default_PCI_trigger(idx) (1)
957 #define default_PCI_polarity(idx) (1)
959 /* MCA interrupts are always polarity zero level triggered,
960 * when listed as conforming in the MP table. */
962 #define default_MCA_trigger(idx) (1)
963 #define default_MCA_polarity(idx) (0)
965 /* NEC98 interrupts are always polarity zero edge triggered,
966 * when listed as conforming in the MP table. */
968 #define default_NEC98_trigger(idx) (0)
969 #define default_NEC98_polarity(idx) (0)
971 static int __init MPBIOS_polarity(int idx)
972 {
973 int bus = mp_irqs[idx].mpc_srcbus;
974 int polarity;
976 /*
977 * Determine IRQ line polarity (high active or low active):
978 */
979 switch (mp_irqs[idx].mpc_irqflag & 3)
980 {
981 case 0: /* conforms, ie. bus-type dependent polarity */
982 {
983 switch (mp_bus_id_to_type[bus])
984 {
985 case MP_BUS_ISA: /* ISA pin */
986 {
987 polarity = default_ISA_polarity(idx);
988 break;
989 }
990 case MP_BUS_EISA: /* EISA pin */
991 {
992 polarity = default_EISA_polarity(idx);
993 break;
994 }
995 case MP_BUS_PCI: /* PCI pin */
996 {
997 polarity = default_PCI_polarity(idx);
998 break;
999 }
1000 case MP_BUS_MCA: /* MCA pin */
1002 polarity = default_MCA_polarity(idx);
1003 break;
1005 case MP_BUS_NEC98: /* NEC 98 pin */
1007 polarity = default_NEC98_polarity(idx);
1008 break;
1010 default:
1012 printk(KERN_WARNING "broken BIOS!!\n");
1013 polarity = 1;
1014 break;
1017 break;
1019 case 1: /* high active */
1021 polarity = 0;
1022 break;
1024 case 2: /* reserved */
1026 printk(KERN_WARNING "broken BIOS!!\n");
1027 polarity = 1;
1028 break;
1030 case 3: /* low active */
1032 polarity = 1;
1033 break;
1035 default: /* invalid */
1037 printk(KERN_WARNING "broken BIOS!!\n");
1038 polarity = 1;
1039 break;
1042 return polarity;
1045 static int MPBIOS_trigger(int idx)
1047 int bus = mp_irqs[idx].mpc_srcbus;
1048 int trigger;
1050 /*
1051 * Determine IRQ trigger mode (edge or level sensitive):
1052 */
1053 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1055 case 0: /* conforms, ie. bus-type dependent */
1057 switch (mp_bus_id_to_type[bus])
1059 case MP_BUS_ISA: /* ISA pin */
1061 trigger = default_ISA_trigger(idx);
1062 break;
1064 case MP_BUS_EISA: /* EISA pin */
1066 trigger = default_EISA_trigger(idx);
1067 break;
1069 case MP_BUS_PCI: /* PCI pin */
1071 trigger = default_PCI_trigger(idx);
1072 break;
1074 case MP_BUS_MCA: /* MCA pin */
1076 trigger = default_MCA_trigger(idx);
1077 break;
1079 case MP_BUS_NEC98: /* NEC 98 pin */
1081 trigger = default_NEC98_trigger(idx);
1082 break;
1084 default:
1086 printk(KERN_WARNING "broken BIOS!!\n");
1087 trigger = 1;
1088 break;
1091 break;
1093 case 1: /* edge */
1095 trigger = 0;
1096 break;
1098 case 2: /* reserved */
1100 printk(KERN_WARNING "broken BIOS!!\n");
1101 trigger = 1;
1102 break;
1104 case 3: /* level */
1106 trigger = 1;
1107 break;
1109 default: /* invalid */
1111 printk(KERN_WARNING "broken BIOS!!\n");
1112 trigger = 0;
1113 break;
1116 return trigger;
1119 static inline int irq_polarity(int idx)
1121 return MPBIOS_polarity(idx);
1124 static inline int irq_trigger(int idx)
1126 return MPBIOS_trigger(idx);
1129 static int pin_2_irq(int idx, int apic, int pin)
1131 int irq, i;
1132 int bus = mp_irqs[idx].mpc_srcbus;
1134 /*
1135 * Debugging check, we are in big trouble if this message pops up!
1136 */
1137 if (mp_irqs[idx].mpc_dstirq != pin)
1138 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1140 switch (mp_bus_id_to_type[bus])
1142 case MP_BUS_ISA: /* ISA pin */
1143 case MP_BUS_EISA:
1144 case MP_BUS_MCA:
1145 case MP_BUS_NEC98:
1147 irq = mp_irqs[idx].mpc_srcbusirq;
1148 break;
1150 case MP_BUS_PCI: /* PCI pin */
1152 /*
1153 * PCI IRQs are mapped in order
1154 */
1155 i = irq = 0;
1156 while (i < apic)
1157 irq += nr_ioapic_registers[i++];
1158 irq += pin;
1160 /*
1161 * For MPS mode, so far only needed by ES7000 platform
1162 */
1163 if (ioapic_renumber_irq)
1164 irq = ioapic_renumber_irq(apic, irq);
1166 break;
1168 default:
1170 printk(KERN_ERR "unknown bus type %d.\n",bus);
1171 irq = 0;
1172 break;
1176 /*
1177 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1178 */
1179 if ((pin >= 16) && (pin <= 23)) {
1180 if (pirq_entries[pin-16] != -1) {
1181 if (!pirq_entries[pin-16]) {
1182 apic_printk(APIC_VERBOSE, KERN_DEBUG
1183 "disabling PIRQ%d\n", pin-16);
1184 } else {
1185 irq = pirq_entries[pin-16];
1186 apic_printk(APIC_VERBOSE, KERN_DEBUG
1187 "using PIRQ%d -> IRQ %d\n",
1188 pin-16, irq);
1192 return irq;
1195 static inline int IO_APIC_irq_trigger(int irq)
1197 int apic, idx, pin;
1199 for (apic = 0; apic < nr_ioapics; apic++) {
1200 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1201 idx = find_irq_entry(apic,pin,mp_INT);
1202 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1203 return irq_trigger(idx);
1206 /*
1207 * nonexistent IRQs are edge default
1208 */
1209 return 0;
1212 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1213 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly; /* = { FIRST_DEVICE_VECTOR , 0 }; */
1215 int assign_irq_vector(int irq)
1217 unsigned long flags;
1218 int vector;
1219 struct physdev_irq irq_op;
1221 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
1223 if (irq < PIRQ_BASE || irq - PIRQ_BASE > NR_PIRQS)
1224 return -EINVAL;
1226 spin_lock_irqsave(&vector_lock, flags);
1228 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
1229 spin_unlock_irqrestore(&vector_lock, flags);
1230 return IO_APIC_VECTOR(irq);
1233 irq_op.irq = irq;
1234 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
1235 spin_unlock_irqrestore(&vector_lock, flags);
1236 return -ENOSPC;
1239 vector = irq_op.vector;
1240 vector_irq[vector] = irq;
1241 if (irq != AUTO_ASSIGN)
1242 IO_APIC_VECTOR(irq) = vector;
1244 spin_unlock_irqrestore(&vector_lock, flags);
1246 return vector;
1249 #ifndef CONFIG_XEN
1250 static struct hw_interrupt_type ioapic_level_type;
1251 static struct hw_interrupt_type ioapic_edge_type;
1253 #define IOAPIC_AUTO -1
1254 #define IOAPIC_EDGE 0
1255 #define IOAPIC_LEVEL 1
1257 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1259 unsigned idx;
1261 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
1263 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1264 trigger == IOAPIC_LEVEL)
1265 irq_desc[idx].chip = &ioapic_level_type;
1266 else
1267 irq_desc[idx].chip = &ioapic_edge_type;
1268 set_intr_gate(vector, interrupt[idx]);
1270 #else
1271 #define ioapic_register_intr(irq, vector, trigger) evtchn_register_pirq(irq)
1272 #endif
1274 static void __init setup_IO_APIC_irqs(void)
1276 struct IO_APIC_route_entry entry;
1277 int apic, pin, idx, irq, first_notcon = 1, vector;
1278 unsigned long flags;
1280 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1282 for (apic = 0; apic < nr_ioapics; apic++) {
1283 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1285 /*
1286 * add it to the IO-APIC irq-routing table:
1287 */
1288 memset(&entry,0,sizeof(entry));
1290 entry.delivery_mode = INT_DELIVERY_MODE;
1291 entry.dest_mode = INT_DEST_MODE;
1292 entry.mask = 0; /* enable IRQ */
1293 entry.dest.logical.logical_dest =
1294 cpu_mask_to_apicid(TARGET_CPUS);
1296 idx = find_irq_entry(apic,pin,mp_INT);
1297 if (idx == -1) {
1298 if (first_notcon) {
1299 apic_printk(APIC_VERBOSE, KERN_DEBUG
1300 " IO-APIC (apicid-pin) %d-%d",
1301 mp_ioapics[apic].mpc_apicid,
1302 pin);
1303 first_notcon = 0;
1304 } else
1305 apic_printk(APIC_VERBOSE, ", %d-%d",
1306 mp_ioapics[apic].mpc_apicid, pin);
1307 continue;
1310 entry.trigger = irq_trigger(idx);
1311 entry.polarity = irq_polarity(idx);
1313 if (irq_trigger(idx)) {
1314 entry.trigger = 1;
1315 entry.mask = 1;
1318 irq = pin_2_irq(idx, apic, pin);
1319 /*
1320 * skip adding the timer int on secondary nodes, which causes
1321 * a small but painful rift in the time-space continuum
1322 */
1323 if (multi_timer_check(apic, irq))
1324 continue;
1325 else
1326 add_pin_to_irq(irq, apic, pin);
1328 if (/*!apic &&*/ !IO_APIC_IRQ(irq))
1329 continue;
1331 if (IO_APIC_IRQ(irq)) {
1332 vector = assign_irq_vector(irq);
1333 entry.vector = vector;
1334 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1336 if (!apic && (irq < 16))
1337 disable_8259A_irq(irq);
1339 spin_lock_irqsave(&ioapic_lock, flags);
1340 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1341 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1342 set_native_irq_info(irq, TARGET_CPUS);
1343 spin_unlock_irqrestore(&ioapic_lock, flags);
1347 if (!first_notcon)
1348 apic_printk(APIC_VERBOSE, " not connected.\n");
1351 /*
1352 * Set up the 8259A-master output pin:
1353 */
1354 #ifndef CONFIG_XEN
1355 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1357 struct IO_APIC_route_entry entry;
1358 unsigned long flags;
1360 memset(&entry,0,sizeof(entry));
1362 disable_8259A_irq(0);
1364 /* mask LVT0 */
1365 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1367 /*
1368 * We use logical delivery to get the timer IRQ
1369 * to the first CPU.
1370 */
1371 entry.dest_mode = INT_DEST_MODE;
1372 entry.mask = 0; /* unmask IRQ now */
1373 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1374 entry.delivery_mode = INT_DELIVERY_MODE;
1375 entry.polarity = 0;
1376 entry.trigger = 0;
1377 entry.vector = vector;
1379 /*
1380 * The timer IRQ doesn't have to know that behind the
1381 * scene we have a 8259A-master in AEOI mode ...
1382 */
1383 irq_desc[0].chip = &ioapic_edge_type;
1385 /*
1386 * Add it to the IO-APIC irq-routing table:
1387 */
1388 spin_lock_irqsave(&ioapic_lock, flags);
1389 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1390 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1391 spin_unlock_irqrestore(&ioapic_lock, flags);
1393 enable_8259A_irq(0);
1396 static inline void UNEXPECTED_IO_APIC(void)
1400 void __init print_IO_APIC(void)
1402 int apic, i;
1403 union IO_APIC_reg_00 reg_00;
1404 union IO_APIC_reg_01 reg_01;
1405 union IO_APIC_reg_02 reg_02;
1406 union IO_APIC_reg_03 reg_03;
1407 unsigned long flags;
1409 if (apic_verbosity == APIC_QUIET)
1410 return;
1412 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1413 for (i = 0; i < nr_ioapics; i++)
1414 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1415 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1417 /*
1418 * We are a bit conservative about what we expect. We have to
1419 * know about every hardware change ASAP.
1420 */
1421 printk(KERN_INFO "testing the IO APIC.......................\n");
1423 for (apic = 0; apic < nr_ioapics; apic++) {
1425 spin_lock_irqsave(&ioapic_lock, flags);
1426 reg_00.raw = io_apic_read(apic, 0);
1427 reg_01.raw = io_apic_read(apic, 1);
1428 if (reg_01.bits.version >= 0x10)
1429 reg_02.raw = io_apic_read(apic, 2);
1430 if (reg_01.bits.version >= 0x20)
1431 reg_03.raw = io_apic_read(apic, 3);
1432 spin_unlock_irqrestore(&ioapic_lock, flags);
1434 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1435 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1436 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1437 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1438 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1439 if (reg_00.bits.ID >= get_physical_broadcast())
1440 UNEXPECTED_IO_APIC();
1441 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1442 UNEXPECTED_IO_APIC();
1444 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1445 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1446 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1447 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1448 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1449 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1450 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1451 (reg_01.bits.entries != 0x2E) &&
1452 (reg_01.bits.entries != 0x3F)
1454 UNEXPECTED_IO_APIC();
1456 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1457 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1458 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1459 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1460 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1461 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1462 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1464 UNEXPECTED_IO_APIC();
1465 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1466 UNEXPECTED_IO_APIC();
1468 /*
1469 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1470 * but the value of reg_02 is read as the previous read register
1471 * value, so ignore it if reg_02 == reg_01.
1472 */
1473 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1474 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1475 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1476 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1477 UNEXPECTED_IO_APIC();
1480 /*
1481 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1482 * or reg_03, but the value of reg_0[23] is read as the previous read
1483 * register value, so ignore it if reg_03 == reg_0[12].
1484 */
1485 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1486 reg_03.raw != reg_01.raw) {
1487 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1488 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1489 if (reg_03.bits.__reserved_1)
1490 UNEXPECTED_IO_APIC();
1493 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1495 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1496 " Stat Dest Deli Vect: \n");
1498 for (i = 0; i <= reg_01.bits.entries; i++) {
1499 struct IO_APIC_route_entry entry;
1501 spin_lock_irqsave(&ioapic_lock, flags);
1502 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1503 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1504 spin_unlock_irqrestore(&ioapic_lock, flags);
1506 printk(KERN_DEBUG " %02x %03X %02X ",
1507 i,
1508 entry.dest.logical.logical_dest,
1509 entry.dest.physical.physical_dest
1510 );
1512 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1513 entry.mask,
1514 entry.trigger,
1515 entry.irr,
1516 entry.polarity,
1517 entry.delivery_status,
1518 entry.dest_mode,
1519 entry.delivery_mode,
1520 entry.vector
1521 );
1524 if (use_pci_vector())
1525 printk(KERN_INFO "Using vector-based indexing\n");
1526 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1527 for (i = 0; i < NR_IRQS; i++) {
1528 struct irq_pin_list *entry = irq_2_pin + i;
1529 if (entry->pin < 0)
1530 continue;
1531 if (use_pci_vector() && !platform_legacy_irq(i))
1532 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1533 else
1534 printk(KERN_DEBUG "IRQ%d ", i);
1535 for (;;) {
1536 printk("-> %d:%d", entry->apic, entry->pin);
1537 if (!entry->next)
1538 break;
1539 entry = irq_2_pin + entry->next;
1541 printk("\n");
1544 printk(KERN_INFO ".................................... done.\n");
1546 return;
1549 static void print_APIC_bitfield (int base)
1551 unsigned int v;
1552 int i, j;
1554 if (apic_verbosity == APIC_QUIET)
1555 return;
1557 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1558 for (i = 0; i < 8; i++) {
1559 v = apic_read(base + i*0x10);
1560 for (j = 0; j < 32; j++) {
1561 if (v & (1<<j))
1562 printk("1");
1563 else
1564 printk("0");
1566 printk("\n");
1570 void /*__init*/ print_local_APIC(void * dummy)
1572 unsigned int v, ver, maxlvt;
1574 if (apic_verbosity == APIC_QUIET)
1575 return;
1577 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1578 smp_processor_id(), hard_smp_processor_id());
1579 v = apic_read(APIC_ID);
1580 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1581 v = apic_read(APIC_LVR);
1582 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1583 ver = GET_APIC_VERSION(v);
1584 maxlvt = get_maxlvt();
1586 v = apic_read(APIC_TASKPRI);
1587 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1589 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1590 v = apic_read(APIC_ARBPRI);
1591 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1592 v & APIC_ARBPRI_MASK);
1593 v = apic_read(APIC_PROCPRI);
1594 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1597 v = apic_read(APIC_EOI);
1598 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1599 v = apic_read(APIC_RRR);
1600 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1601 v = apic_read(APIC_LDR);
1602 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1603 v = apic_read(APIC_DFR);
1604 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1605 v = apic_read(APIC_SPIV);
1606 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1608 printk(KERN_DEBUG "... APIC ISR field:\n");
1609 print_APIC_bitfield(APIC_ISR);
1610 printk(KERN_DEBUG "... APIC TMR field:\n");
1611 print_APIC_bitfield(APIC_TMR);
1612 printk(KERN_DEBUG "... APIC IRR field:\n");
1613 print_APIC_bitfield(APIC_IRR);
1615 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1616 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1617 apic_write(APIC_ESR, 0);
1618 v = apic_read(APIC_ESR);
1619 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1622 v = apic_read(APIC_ICR);
1623 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1624 v = apic_read(APIC_ICR2);
1625 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1627 v = apic_read(APIC_LVTT);
1628 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1630 if (maxlvt > 3) { /* PC is LVT#4. */
1631 v = apic_read(APIC_LVTPC);
1632 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1634 v = apic_read(APIC_LVT0);
1635 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1636 v = apic_read(APIC_LVT1);
1637 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1639 if (maxlvt > 2) { /* ERR is LVT#3. */
1640 v = apic_read(APIC_LVTERR);
1641 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1644 v = apic_read(APIC_TMICT);
1645 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1646 v = apic_read(APIC_TMCCT);
1647 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1648 v = apic_read(APIC_TDCR);
1649 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1650 printk("\n");
1653 void print_all_local_APICs (void)
1655 on_each_cpu(print_local_APIC, NULL, 1, 1);
1658 void /*__init*/ print_PIC(void)
1660 unsigned int v;
1661 unsigned long flags;
1663 if (apic_verbosity == APIC_QUIET)
1664 return;
1666 printk(KERN_DEBUG "\nprinting PIC contents\n");
1668 spin_lock_irqsave(&i8259A_lock, flags);
1670 v = inb(0xa1) << 8 | inb(0x21);
1671 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1673 v = inb(0xa0) << 8 | inb(0x20);
1674 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1676 outb(0x0b,0xa0);
1677 outb(0x0b,0x20);
1678 v = inb(0xa0) << 8 | inb(0x20);
1679 outb(0x0a,0xa0);
1680 outb(0x0a,0x20);
1682 spin_unlock_irqrestore(&i8259A_lock, flags);
1684 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1686 v = inb(0x4d1) << 8 | inb(0x4d0);
1687 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1689 #endif /* !CONFIG_XEN */
1691 static void __init enable_IO_APIC(void)
1693 union IO_APIC_reg_01 reg_01;
1694 #ifndef CONFIG_XEN
1695 int i8259_apic, i8259_pin;
1696 #endif
1697 int i, apic;
1698 unsigned long flags;
1700 for (i = 0; i < PIN_MAP_SIZE; i++) {
1701 irq_2_pin[i].pin = -1;
1702 irq_2_pin[i].next = 0;
1704 if (!pirqs_enabled)
1705 for (i = 0; i < MAX_PIRQS; i++)
1706 pirq_entries[i] = -1;
1708 /*
1709 * The number of IO-APIC IRQ registers (== #pins):
1710 */
1711 for (apic = 0; apic < nr_ioapics; apic++) {
1712 spin_lock_irqsave(&ioapic_lock, flags);
1713 reg_01.raw = io_apic_read(apic, 1);
1714 spin_unlock_irqrestore(&ioapic_lock, flags);
1715 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1717 #ifndef CONFIG_XEN
1718 for(apic = 0; apic < nr_ioapics; apic++) {
1719 int pin;
1720 /* See if any of the pins is in ExtINT mode */
1721 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1722 struct IO_APIC_route_entry entry;
1723 spin_lock_irqsave(&ioapic_lock, flags);
1724 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1725 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1726 spin_unlock_irqrestore(&ioapic_lock, flags);
1729 /* If the interrupt line is enabled and in ExtInt mode
1730 * I have found the pin where the i8259 is connected.
1731 */
1732 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1733 ioapic_i8259.apic = apic;
1734 ioapic_i8259.pin = pin;
1735 goto found_i8259;
1739 found_i8259:
1740 /* Look to see what if the MP table has reported the ExtINT */
1741 /* If we could not find the appropriate pin by looking at the ioapic
1742 * the i8259 probably is not connected the ioapic but give the
1743 * mptable a chance anyway.
1744 */
1745 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1746 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1747 /* Trust the MP table if nothing is setup in the hardware */
1748 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1749 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1750 ioapic_i8259.pin = i8259_pin;
1751 ioapic_i8259.apic = i8259_apic;
1753 /* Complain if the MP table and the hardware disagree */
1754 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1755 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1757 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1759 #endif
1761 /*
1762 * Do not trust the IO-APIC being empty at bootup
1763 */
1764 clear_IO_APIC();
1767 /*
1768 * Not an __init, needed by the reboot code
1769 */
1770 void disable_IO_APIC(void)
1772 /*
1773 * Clear the IO-APIC before rebooting:
1774 */
1775 clear_IO_APIC();
1777 #ifndef CONFIG_XEN
1778 /*
1779 * If the i8259 is routed through an IOAPIC
1780 * Put that IOAPIC in virtual wire mode
1781 * so legacy interrupts can be delivered.
1782 */
1783 if (ioapic_i8259.pin != -1) {
1784 struct IO_APIC_route_entry entry;
1785 unsigned long flags;
1787 memset(&entry, 0, sizeof(entry));
1788 entry.mask = 0; /* Enabled */
1789 entry.trigger = 0; /* Edge */
1790 entry.irr = 0;
1791 entry.polarity = 0; /* High */
1792 entry.delivery_status = 0;
1793 entry.dest_mode = 0; /* Physical */
1794 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1795 entry.vector = 0;
1796 entry.dest.physical.physical_dest =
1797 GET_APIC_ID(apic_read(APIC_ID));
1799 /*
1800 * Add it to the IO-APIC irq-routing table:
1801 */
1802 spin_lock_irqsave(&ioapic_lock, flags);
1803 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1804 *(((int *)&entry)+1));
1805 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1806 *(((int *)&entry)+0));
1807 spin_unlock_irqrestore(&ioapic_lock, flags);
1809 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1810 #endif
1813 /*
1814 * function to set the IO-APIC physical IDs based on the
1815 * values stored in the MPC table.
1817 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1818 */
1820 #if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
1821 static void __init setup_ioapic_ids_from_mpc(void)
1823 union IO_APIC_reg_00 reg_00;
1824 physid_mask_t phys_id_present_map;
1825 int apic;
1826 int i;
1827 unsigned char old_id;
1828 unsigned long flags;
1830 /*
1831 * Don't check I/O APIC IDs for xAPIC systems. They have
1832 * no meaning without the serial APIC bus.
1833 */
1834 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1835 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1836 return;
1837 /*
1838 * This is broken; anything with a real cpu count has to
1839 * circumvent this idiocy regardless.
1840 */
1841 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1843 /*
1844 * Set the IOAPIC ID to the value stored in the MPC table.
1845 */
1846 for (apic = 0; apic < nr_ioapics; apic++) {
1848 /* Read the register 0 value */
1849 spin_lock_irqsave(&ioapic_lock, flags);
1850 reg_00.raw = io_apic_read(apic, 0);
1851 spin_unlock_irqrestore(&ioapic_lock, flags);
1853 old_id = mp_ioapics[apic].mpc_apicid;
1855 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1856 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1857 apic, mp_ioapics[apic].mpc_apicid);
1858 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1859 reg_00.bits.ID);
1860 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1863 /*
1864 * Sanity check, is the ID really free? Every APIC in a
1865 * system must have a unique ID or we get lots of nice
1866 * 'stuck on smp_invalidate_needed IPI wait' messages.
1867 */
1868 if (check_apicid_used(phys_id_present_map,
1869 mp_ioapics[apic].mpc_apicid)) {
1870 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1871 apic, mp_ioapics[apic].mpc_apicid);
1872 for (i = 0; i < get_physical_broadcast(); i++)
1873 if (!physid_isset(i, phys_id_present_map))
1874 break;
1875 if (i >= get_physical_broadcast())
1876 panic("Max APIC ID exceeded!\n");
1877 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1878 i);
1879 physid_set(i, phys_id_present_map);
1880 mp_ioapics[apic].mpc_apicid = i;
1881 } else {
1882 physid_mask_t tmp;
1883 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1884 apic_printk(APIC_VERBOSE, "Setting %d in the "
1885 "phys_id_present_map\n",
1886 mp_ioapics[apic].mpc_apicid);
1887 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1891 /*
1892 * We need to adjust the IRQ routing table
1893 * if the ID changed.
1894 */
1895 if (old_id != mp_ioapics[apic].mpc_apicid)
1896 for (i = 0; i < mp_irq_entries; i++)
1897 if (mp_irqs[i].mpc_dstapic == old_id)
1898 mp_irqs[i].mpc_dstapic
1899 = mp_ioapics[apic].mpc_apicid;
1901 /*
1902 * Read the right value from the MPC table and
1903 * write it into the ID register.
1904 */
1905 apic_printk(APIC_VERBOSE, KERN_INFO
1906 "...changing IO-APIC physical APIC ID to %d ...",
1907 mp_ioapics[apic].mpc_apicid);
1909 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1910 spin_lock_irqsave(&ioapic_lock, flags);
1911 io_apic_write(apic, 0, reg_00.raw);
1912 spin_unlock_irqrestore(&ioapic_lock, flags);
1914 /*
1915 * Sanity check
1916 */
1917 spin_lock_irqsave(&ioapic_lock, flags);
1918 reg_00.raw = io_apic_read(apic, 0);
1919 spin_unlock_irqrestore(&ioapic_lock, flags);
1920 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1921 printk("could not set ID!\n");
1922 else
1923 apic_printk(APIC_VERBOSE, " ok.\n");
1926 #else
1927 static void __init setup_ioapic_ids_from_mpc(void) { }
1928 #endif
1930 #ifndef CONFIG_XEN
1931 /*
1932 * There is a nasty bug in some older SMP boards, their mptable lies
1933 * about the timer IRQ. We do the following to work around the situation:
1935 * - timer IRQ defaults to IO-APIC IRQ
1936 * - if this function detects that timer IRQs are defunct, then we fall
1937 * back to ISA timer IRQs
1938 */
1939 static int __init timer_irq_works(void)
1941 unsigned long t1 = jiffies;
1943 local_irq_enable();
1944 /* Let ten ticks pass... */
1945 mdelay((10 * 1000) / HZ);
1947 /*
1948 * Expect a few ticks at least, to be sure some possible
1949 * glue logic does not lock up after one or two first
1950 * ticks in a non-ExtINT mode. Also the local APIC
1951 * might have cached one ExtINT interrupt. Finally, at
1952 * least one tick may be lost due to delays.
1953 */
1954 if (jiffies - t1 > 4)
1955 return 1;
1957 return 0;
1960 /*
1961 * In the SMP+IOAPIC case it might happen that there are an unspecified
1962 * number of pending IRQ events unhandled. These cases are very rare,
1963 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1964 * better to do it this way as thus we do not have to be aware of
1965 * 'pending' interrupts in the IRQ path, except at this point.
1966 */
1967 /*
1968 * Edge triggered needs to resend any interrupt
1969 * that was delayed but this is now handled in the device
1970 * independent code.
1971 */
1973 /*
1974 * Starting up a edge-triggered IO-APIC interrupt is
1975 * nasty - we need to make sure that we get the edge.
1976 * If it is already asserted for some reason, we need
1977 * return 1 to indicate that is was pending.
1979 * This is not complete - we should be able to fake
1980 * an edge even if it isn't on the 8259A...
1981 */
1982 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1984 int was_pending = 0;
1985 unsigned long flags;
1987 spin_lock_irqsave(&ioapic_lock, flags);
1988 if (irq < 16) {
1989 disable_8259A_irq(irq);
1990 if (i8259A_irq_pending(irq))
1991 was_pending = 1;
1993 __unmask_IO_APIC_irq(irq);
1994 spin_unlock_irqrestore(&ioapic_lock, flags);
1996 return was_pending;
1999 /*
2000 * Once we have recorded IRQ_PENDING already, we can mask the
2001 * interrupt for real. This prevents IRQ storms from unhandled
2002 * devices.
2003 */
2004 static void ack_edge_ioapic_irq(unsigned int irq)
2006 move_irq(irq);
2007 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
2008 == (IRQ_PENDING | IRQ_DISABLED))
2009 mask_IO_APIC_irq(irq);
2010 ack_APIC_irq();
2013 /*
2014 * Level triggered interrupts can just be masked,
2015 * and shutting down and starting up the interrupt
2016 * is the same as enabling and disabling them -- except
2017 * with a startup need to return a "was pending" value.
2019 * Level triggered interrupts are special because we
2020 * do not touch any IO-APIC register while handling
2021 * them. We ack the APIC in the end-IRQ handler, not
2022 * in the start-IRQ-handler. Protection against reentrance
2023 * from the same interrupt is still provided, both by the
2024 * generic IRQ layer and by the fact that an unacked local
2025 * APIC does not accept IRQs.
2026 */
2027 static unsigned int startup_level_ioapic_irq (unsigned int irq)
2029 unmask_IO_APIC_irq(irq);
2031 return 0; /* don't check for pending */
2034 static void end_level_ioapic_irq (unsigned int irq)
2036 unsigned long v;
2037 int i;
2039 move_irq(irq);
2040 /*
2041 * It appears there is an erratum which affects at least version 0x11
2042 * of I/O APIC (that's the 82093AA and cores integrated into various
2043 * chipsets). Under certain conditions a level-triggered interrupt is
2044 * erroneously delivered as edge-triggered one but the respective IRR
2045 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2046 * message but it will never arrive and further interrupts are blocked
2047 * from the source. The exact reason is so far unknown, but the
2048 * phenomenon was observed when two consecutive interrupt requests
2049 * from a given source get delivered to the same CPU and the source is
2050 * temporarily disabled in between.
2052 * A workaround is to simulate an EOI message manually. We achieve it
2053 * by setting the trigger mode to edge and then to level when the edge
2054 * trigger mode gets detected in the TMR of a local APIC for a
2055 * level-triggered interrupt. We mask the source for the time of the
2056 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2057 * The idea is from Manfred Spraul. --macro
2058 */
2059 i = IO_APIC_VECTOR(irq);
2061 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2063 ack_APIC_irq();
2065 if (!(v & (1 << (i & 0x1f)))) {
2066 atomic_inc(&irq_mis_count);
2067 spin_lock(&ioapic_lock);
2068 __mask_and_edge_IO_APIC_irq(irq);
2069 __unmask_and_level_IO_APIC_irq(irq);
2070 spin_unlock(&ioapic_lock);
2074 #ifdef CONFIG_PCI_MSI
2075 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2077 int irq = vector_to_irq(vector);
2079 return startup_edge_ioapic_irq(irq);
2082 static void ack_edge_ioapic_vector(unsigned int vector)
2084 int irq = vector_to_irq(vector);
2086 move_native_irq(vector);
2087 ack_edge_ioapic_irq(irq);
2090 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2092 int irq = vector_to_irq(vector);
2094 return startup_level_ioapic_irq (irq);
2097 static void end_level_ioapic_vector (unsigned int vector)
2099 int irq = vector_to_irq(vector);
2101 move_native_irq(vector);
2102 end_level_ioapic_irq(irq);
2105 static void mask_IO_APIC_vector (unsigned int vector)
2107 int irq = vector_to_irq(vector);
2109 mask_IO_APIC_irq(irq);
2112 static void unmask_IO_APIC_vector (unsigned int vector)
2114 int irq = vector_to_irq(vector);
2116 unmask_IO_APIC_irq(irq);
2119 #ifdef CONFIG_SMP
2120 static void set_ioapic_affinity_vector (unsigned int vector,
2121 cpumask_t cpu_mask)
2123 int irq = vector_to_irq(vector);
2125 set_native_irq_info(vector, cpu_mask);
2126 set_ioapic_affinity_irq(irq, cpu_mask);
2128 #endif
2129 #endif
2131 static int ioapic_retrigger(unsigned int irq)
2133 send_IPI_self(IO_APIC_VECTOR(irq));
2135 return 1;
2138 /*
2139 * Level and edge triggered IO-APIC interrupts need different handling,
2140 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2141 * handled with the level-triggered descriptor, but that one has slightly
2142 * more overhead. Level-triggered interrupts cannot be handled with the
2143 * edge-triggered handler, without risking IRQ storms and other ugly
2144 * races.
2145 */
2146 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2147 .typename = "IO-APIC-edge",
2148 .startup = startup_edge_ioapic,
2149 .shutdown = shutdown_edge_ioapic,
2150 .enable = enable_edge_ioapic,
2151 .disable = disable_edge_ioapic,
2152 .ack = ack_edge_ioapic,
2153 .end = end_edge_ioapic,
2154 #ifdef CONFIG_SMP
2155 .set_affinity = set_ioapic_affinity,
2156 #endif
2157 .retrigger = ioapic_retrigger,
2158 };
2160 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2161 .typename = "IO-APIC-level",
2162 .startup = startup_level_ioapic,
2163 .shutdown = shutdown_level_ioapic,
2164 .enable = enable_level_ioapic,
2165 .disable = disable_level_ioapic,
2166 .ack = mask_and_ack_level_ioapic,
2167 .end = end_level_ioapic,
2168 #ifdef CONFIG_SMP
2169 .set_affinity = set_ioapic_affinity,
2170 #endif
2171 .retrigger = ioapic_retrigger,
2172 };
2173 #endif /* !CONFIG_XEN */
2175 static inline void init_IO_APIC_traps(void)
2177 int irq;
2179 /*
2180 * NOTE! The local APIC isn't very good at handling
2181 * multiple interrupts at the same interrupt level.
2182 * As the interrupt level is determined by taking the
2183 * vector number and shifting that right by 4, we
2184 * want to spread these out a bit so that they don't
2185 * all fall in the same interrupt level.
2187 * Also, we've got to be careful not to trash gate
2188 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2189 */
2190 for (irq = 0; irq < NR_IRQS ; irq++) {
2191 int tmp = irq;
2192 if (use_pci_vector()) {
2193 if (!platform_legacy_irq(tmp))
2194 if ((tmp = vector_to_irq(tmp)) == -1)
2195 continue;
2197 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2198 /*
2199 * Hmm.. We don't have an entry for this,
2200 * so default to an old-fashioned 8259
2201 * interrupt if we can..
2202 */
2203 if (irq < 16)
2204 make_8259A_irq(irq);
2205 #ifndef CONFIG_XEN
2206 else
2207 /* Strange. Oh, well.. */
2208 irq_desc[irq].chip = &no_irq_type;
2209 #endif
2214 #ifndef CONFIG_XEN
2215 static void enable_lapic_irq (unsigned int irq)
2217 unsigned long v;
2219 v = apic_read(APIC_LVT0);
2220 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2223 static void disable_lapic_irq (unsigned int irq)
2225 unsigned long v;
2227 v = apic_read(APIC_LVT0);
2228 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2231 static void ack_lapic_irq (unsigned int irq)
2233 ack_APIC_irq();
2236 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2238 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2239 .typename = "local-APIC-edge",
2240 .startup = NULL, /* startup_irq() not used for IRQ0 */
2241 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
2242 .enable = enable_lapic_irq,
2243 .disable = disable_lapic_irq,
2244 .ack = ack_lapic_irq,
2245 .end = end_lapic_irq
2246 };
2248 static void setup_nmi (void)
2250 /*
2251 * Dirty trick to enable the NMI watchdog ...
2252 * We put the 8259A master into AEOI mode and
2253 * unmask on all local APICs LVT0 as NMI.
2255 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2256 * is from Maciej W. Rozycki - so we do not have to EOI from
2257 * the NMI handler or the timer interrupt.
2258 */
2259 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2261 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2263 apic_printk(APIC_VERBOSE, " done.\n");
2266 /*
2267 * This looks a bit hackish but it's about the only one way of sending
2268 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2269 * not support the ExtINT mode, unfortunately. We need to send these
2270 * cycles as some i82489DX-based boards have glue logic that keeps the
2271 * 8259A interrupt line asserted until INTA. --macro
2272 */
2273 static inline void unlock_ExtINT_logic(void)
2275 int apic, pin, i;
2276 struct IO_APIC_route_entry entry0, entry1;
2277 unsigned char save_control, save_freq_select;
2278 unsigned long flags;
2280 pin = find_isa_irq_pin(8, mp_INT);
2281 apic = find_isa_irq_apic(8, mp_INT);
2282 if (pin == -1)
2283 return;
2285 spin_lock_irqsave(&ioapic_lock, flags);
2286 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2287 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2288 spin_unlock_irqrestore(&ioapic_lock, flags);
2289 clear_IO_APIC_pin(apic, pin);
2291 memset(&entry1, 0, sizeof(entry1));
2293 entry1.dest_mode = 0; /* physical delivery */
2294 entry1.mask = 0; /* unmask IRQ now */
2295 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2296 entry1.delivery_mode = dest_ExtINT;
2297 entry1.polarity = entry0.polarity;
2298 entry1.trigger = 0;
2299 entry1.vector = 0;
2301 spin_lock_irqsave(&ioapic_lock, flags);
2302 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2303 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2304 spin_unlock_irqrestore(&ioapic_lock, flags);
2306 save_control = CMOS_READ(RTC_CONTROL);
2307 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2308 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2309 RTC_FREQ_SELECT);
2310 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2312 i = 100;
2313 while (i-- > 0) {
2314 mdelay(10);
2315 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2316 i -= 10;
2319 CMOS_WRITE(save_control, RTC_CONTROL);
2320 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2321 clear_IO_APIC_pin(apic, pin);
2323 spin_lock_irqsave(&ioapic_lock, flags);
2324 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2325 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2326 spin_unlock_irqrestore(&ioapic_lock, flags);
2329 int timer_uses_ioapic_pin_0;
2331 /*
2332 * This code may look a bit paranoid, but it's supposed to cooperate with
2333 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2334 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2335 * fanatically on his truly buggy board.
2336 */
2337 static inline void check_timer(void)
2339 int apic1, pin1, apic2, pin2;
2340 int vector;
2342 /*
2343 * get/set the timer IRQ vector:
2344 */
2345 disable_8259A_irq(0);
2346 vector = assign_irq_vector(0);
2347 set_intr_gate(vector, interrupt[0]);
2349 /*
2350 * Subtle, code in do_timer_interrupt() expects an AEOI
2351 * mode for the 8259A whenever interrupts are routed
2352 * through I/O APICs. Also IRQ0 has to be enabled in
2353 * the 8259A which implies the virtual wire has to be
2354 * disabled in the local APIC.
2355 */
2356 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2357 init_8259A(1);
2358 timer_ack = 1;
2359 if (timer_over_8254 > 0)
2360 enable_8259A_irq(0);
2362 pin1 = find_isa_irq_pin(0, mp_INT);
2363 apic1 = find_isa_irq_apic(0, mp_INT);
2364 pin2 = ioapic_i8259.pin;
2365 apic2 = ioapic_i8259.apic;
2367 if (pin1 == 0)
2368 timer_uses_ioapic_pin_0 = 1;
2370 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2371 vector, apic1, pin1, apic2, pin2);
2373 if (pin1 != -1) {
2374 /*
2375 * Ok, does IRQ0 through the IOAPIC work?
2376 */
2377 unmask_IO_APIC_irq(0);
2378 if (timer_irq_works()) {
2379 if (nmi_watchdog == NMI_IO_APIC) {
2380 disable_8259A_irq(0);
2381 setup_nmi();
2382 enable_8259A_irq(0);
2384 if (disable_timer_pin_1 > 0)
2385 clear_IO_APIC_pin(0, pin1);
2386 return;
2388 clear_IO_APIC_pin(apic1, pin1);
2389 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2390 "IO-APIC\n");
2393 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2394 if (pin2 != -1) {
2395 printk("\n..... (found pin %d) ...", pin2);
2396 /*
2397 * legacy devices should be connected to IO APIC #0
2398 */
2399 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2400 if (timer_irq_works()) {
2401 printk("works.\n");
2402 if (pin1 != -1)
2403 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2404 else
2405 add_pin_to_irq(0, apic2, pin2);
2406 if (nmi_watchdog == NMI_IO_APIC) {
2407 setup_nmi();
2409 return;
2411 /*
2412 * Cleanup, just in case ...
2413 */
2414 clear_IO_APIC_pin(apic2, pin2);
2416 printk(" failed.\n");
2418 if (nmi_watchdog == NMI_IO_APIC) {
2419 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2420 nmi_watchdog = 0;
2423 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2425 disable_8259A_irq(0);
2426 irq_desc[0].chip = &lapic_irq_type;
2427 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2428 enable_8259A_irq(0);
2430 if (timer_irq_works()) {
2431 printk(" works.\n");
2432 return;
2434 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2435 printk(" failed.\n");
2437 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2439 timer_ack = 0;
2440 init_8259A(0);
2441 make_8259A_irq(0);
2442 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2444 unlock_ExtINT_logic();
2446 if (timer_irq_works()) {
2447 printk(" works.\n");
2448 return;
2450 printk(" failed :(.\n");
2451 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2452 "report. Then try booting with the 'noapic' option");
2454 #else
2455 int timer_uses_ioapic_pin_0 = 0;
2456 #define check_timer() ((void)0)
2457 #endif
2459 /*
2461 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2462 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2463 * Linux doesn't really care, as it's not actually used
2464 * for any interrupt handling anyway.
2465 */
2466 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2468 void __init setup_IO_APIC(void)
2470 enable_IO_APIC();
2472 if (acpi_ioapic)
2473 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2474 else
2475 io_apic_irqs = ~PIC_IRQS;
2477 printk("ENABLING IO-APIC IRQs\n");
2479 /*
2480 * Set up IO-APIC IRQ routing.
2481 */
2482 if (!acpi_ioapic)
2483 setup_ioapic_ids_from_mpc();
2484 #ifndef CONFIG_XEN
2485 sync_Arb_IDs();
2486 #endif
2487 setup_IO_APIC_irqs();
2488 init_IO_APIC_traps();
2489 check_timer();
2490 if (!acpi_ioapic)
2491 print_IO_APIC();
2494 static int __init setup_disable_8254_timer(char *s)
2496 timer_over_8254 = -1;
2497 return 1;
2499 static int __init setup_enable_8254_timer(char *s)
2501 timer_over_8254 = 2;
2502 return 1;
2505 __setup("disable_8254_timer", setup_disable_8254_timer);
2506 __setup("enable_8254_timer", setup_enable_8254_timer);
2508 /*
2509 * Called after all the initialization is done. If we didnt find any
2510 * APIC bugs then we can allow the modify fast path
2511 */
2513 static int __init io_apic_bug_finalize(void)
2515 if(sis_apic_bug == -1)
2516 sis_apic_bug = 0;
2517 if (is_initial_xendomain()) {
2518 struct xen_platform_op op = { .cmd = XENPF_platform_quirk };
2519 op.u.platform_quirk.quirk_id = sis_apic_bug ?
2520 QUIRK_IOAPIC_BAD_REGSEL : QUIRK_IOAPIC_GOOD_REGSEL;
2521 VOID(HYPERVISOR_platform_op(&op));
2523 return 0;
2526 late_initcall(io_apic_bug_finalize);
2528 #ifndef CONFIG_XEN
2530 struct sysfs_ioapic_data {
2531 struct sys_device dev;
2532 struct IO_APIC_route_entry entry[0];
2533 };
2534 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2536 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2538 struct IO_APIC_route_entry *entry;
2539 struct sysfs_ioapic_data *data;
2540 unsigned long flags;
2541 int i;
2543 data = container_of(dev, struct sysfs_ioapic_data, dev);
2544 entry = data->entry;
2545 spin_lock_irqsave(&ioapic_lock, flags);
2546 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2547 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2548 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2550 spin_unlock_irqrestore(&ioapic_lock, flags);
2552 return 0;
2555 static int ioapic_resume(struct sys_device *dev)
2557 struct IO_APIC_route_entry *entry;
2558 struct sysfs_ioapic_data *data;
2559 unsigned long flags;
2560 union IO_APIC_reg_00 reg_00;
2561 int i;
2563 data = container_of(dev, struct sysfs_ioapic_data, dev);
2564 entry = data->entry;
2566 spin_lock_irqsave(&ioapic_lock, flags);
2567 reg_00.raw = io_apic_read(dev->id, 0);
2568 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2569 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2570 io_apic_write(dev->id, 0, reg_00.raw);
2572 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2573 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2574 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2576 spin_unlock_irqrestore(&ioapic_lock, flags);
2578 return 0;
2581 static struct sysdev_class ioapic_sysdev_class = {
2582 set_kset_name("ioapic"),
2583 .suspend = ioapic_suspend,
2584 .resume = ioapic_resume,
2585 };
2587 static int __init ioapic_init_sysfs(void)
2589 struct sys_device * dev;
2590 int i, size, error = 0;
2592 error = sysdev_class_register(&ioapic_sysdev_class);
2593 if (error)
2594 return error;
2596 for (i = 0; i < nr_ioapics; i++ ) {
2597 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2598 * sizeof(struct IO_APIC_route_entry);
2599 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2600 if (!mp_ioapic_data[i]) {
2601 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2602 continue;
2604 memset(mp_ioapic_data[i], 0, size);
2605 dev = &mp_ioapic_data[i]->dev;
2606 dev->id = i;
2607 dev->cls = &ioapic_sysdev_class;
2608 error = sysdev_register(dev);
2609 if (error) {
2610 kfree(mp_ioapic_data[i]);
2611 mp_ioapic_data[i] = NULL;
2612 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2613 continue;
2617 return 0;
2620 device_initcall(ioapic_init_sysfs);
2622 #endif /* CONFIG_XEN */
2624 /* --------------------------------------------------------------------------
2625 ACPI-based IOAPIC Configuration
2626 -------------------------------------------------------------------------- */
2628 #ifdef CONFIG_ACPI
2630 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2632 #ifndef CONFIG_XEN
2633 union IO_APIC_reg_00 reg_00;
2634 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2635 physid_mask_t tmp;
2636 unsigned long flags;
2637 int i = 0;
2639 /*
2640 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2641 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2642 * supports up to 16 on one shared APIC bus.
2644 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2645 * advantage of new APIC bus architecture.
2646 */
2648 if (physids_empty(apic_id_map))
2649 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2651 spin_lock_irqsave(&ioapic_lock, flags);
2652 reg_00.raw = io_apic_read(ioapic, 0);
2653 spin_unlock_irqrestore(&ioapic_lock, flags);
2655 if (apic_id >= get_physical_broadcast()) {
2656 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2657 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2658 apic_id = reg_00.bits.ID;
2661 /*
2662 * Every APIC in a system must have a unique ID or we get lots of nice
2663 * 'stuck on smp_invalidate_needed IPI wait' messages.
2664 */
2665 if (check_apicid_used(apic_id_map, apic_id)) {
2667 for (i = 0; i < get_physical_broadcast(); i++) {
2668 if (!check_apicid_used(apic_id_map, i))
2669 break;
2672 if (i == get_physical_broadcast())
2673 panic("Max apic_id exceeded!\n");
2675 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2676 "trying %d\n", ioapic, apic_id, i);
2678 apic_id = i;
2681 tmp = apicid_to_cpu_present(apic_id);
2682 physids_or(apic_id_map, apic_id_map, tmp);
2684 if (reg_00.bits.ID != apic_id) {
2685 reg_00.bits.ID = apic_id;
2687 spin_lock_irqsave(&ioapic_lock, flags);
2688 io_apic_write(ioapic, 0, reg_00.raw);
2689 reg_00.raw = io_apic_read(ioapic, 0);
2690 spin_unlock_irqrestore(&ioapic_lock, flags);
2692 /* Sanity check */
2693 if (reg_00.bits.ID != apic_id) {
2694 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2695 return -1;
2699 apic_printk(APIC_VERBOSE, KERN_INFO
2700 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2701 #endif /* !CONFIG_XEN */
2703 return apic_id;
2707 int __init io_apic_get_version (int ioapic)
2709 union IO_APIC_reg_01 reg_01;
2710 unsigned long flags;
2712 spin_lock_irqsave(&ioapic_lock, flags);
2713 reg_01.raw = io_apic_read(ioapic, 1);
2714 spin_unlock_irqrestore(&ioapic_lock, flags);
2716 return reg_01.bits.version;
2720 int __init io_apic_get_redir_entries (int ioapic)
2722 union IO_APIC_reg_01 reg_01;
2723 unsigned long flags;
2725 spin_lock_irqsave(&ioapic_lock, flags);
2726 reg_01.raw = io_apic_read(ioapic, 1);
2727 spin_unlock_irqrestore(&ioapic_lock, flags);
2729 return reg_01.bits.entries;
2733 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2735 struct IO_APIC_route_entry entry;
2736 unsigned long flags;
2738 if (!IO_APIC_IRQ(irq)) {
2739 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2740 ioapic);
2741 return -EINVAL;
2744 /*
2745 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2746 * Note that we mask (disable) IRQs now -- these get enabled when the
2747 * corresponding device driver registers for this IRQ.
2748 */
2750 memset(&entry,0,sizeof(entry));
2752 entry.delivery_mode = INT_DELIVERY_MODE;
2753 entry.dest_mode = INT_DEST_MODE;
2754 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2755 entry.trigger = edge_level;
2756 entry.polarity = active_high_low;
2757 entry.mask = 1;
2759 /*
2760 * IRQs < 16 are already in the irq_2_pin[] map
2761 */
2762 if (irq >= 16)
2763 add_pin_to_irq(irq, ioapic, pin);
2765 entry.vector = assign_irq_vector(irq);
2767 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2768 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2769 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2770 edge_level, active_high_low);
2772 ioapic_register_intr(irq, entry.vector, edge_level);
2774 if (!ioapic && (irq < 16))
2775 disable_8259A_irq(irq);
2777 spin_lock_irqsave(&ioapic_lock, flags);
2778 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2779 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2780 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2781 spin_unlock_irqrestore(&ioapic_lock, flags);
2783 return 0;
2786 #endif /* CONFIG_ACPI */