ia64/linux-2.6.18-xen.hg

diff drivers/net/smc911x.h @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
parents
children
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/drivers/net/smc911x.h	Wed Apr 11 14:15:44 2007 +0100
     1.3 @@ -0,0 +1,835 @@
     1.4 +/*------------------------------------------------------------------------
     1.5 + . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
     1.6 + .
     1.7 + . Copyright (C) 2005 Sensoria Corp.
     1.8 + . Derived from the unified SMC91x driver by Nicolas Pitre
     1.9 + .
    1.10 + . This program is free software; you can redistribute it and/or modify
    1.11 + . it under the terms of the GNU General Public License as published by
    1.12 + . the Free Software Foundation; either version 2 of the License, or
    1.13 + . (at your option) any later version.
    1.14 + .
    1.15 + . This program is distributed in the hope that it will be useful,
    1.16 + . but WITHOUT ANY WARRANTY; without even the implied warranty of
    1.17 + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    1.18 + . GNU General Public License for more details.
    1.19 + .
    1.20 + . You should have received a copy of the GNU General Public License
    1.21 + . along with this program; if not, write to the Free Software
    1.22 + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
    1.23 + .
    1.24 + . Information contained in this file was obtained from the LAN9118
    1.25 + . manual from SMC.  To get a copy, if you really want one, you can find
    1.26 + . information under www.smsc.com.
    1.27 + .
    1.28 + . Authors
    1.29 + .	 Dustin McIntire		 <dustin@sensoria.com>
    1.30 + .
    1.31 + ---------------------------------------------------------------------------*/
    1.32 +#ifndef _SMC911X_H_
    1.33 +#define _SMC911X_H_
    1.34 +
    1.35 +/*
    1.36 + * Use the DMA feature on PXA chips
    1.37 + */
    1.38 +#ifdef CONFIG_ARCH_PXA
    1.39 +  #define SMC_USE_PXA_DMA	1
    1.40 +  #define SMC_USE_16BIT		0
    1.41 +  #define SMC_USE_32BIT		1
    1.42 +#endif
    1.43 +
    1.44 +
    1.45 +/*
    1.46 + * Define the bus width specific IO macros
    1.47 + */
    1.48 +
    1.49 +#if	SMC_USE_16BIT
    1.50 +#define SMC_inb(a, r)			 readb((a) + (r))
    1.51 +#define SMC_inw(a, r)			 readw((a) + (r))
    1.52 +#define SMC_inl(a, r)			 ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
    1.53 +#define SMC_outb(v, a, r)		 writeb(v, (a) + (r))
    1.54 +#define SMC_outw(v, a, r)		 writew(v, (a) + (r))
    1.55 +#define SMC_outl(v, a, r) 			 \
    1.56 +	do{					 \
    1.57 +		 writel(v & 0xFFFF, (a) + (r));	 \
    1.58 +		 writel(v >> 16, (a) + (r) + 2); \
    1.59 +	 } while (0)
    1.60 +#define SMC_insl(a, r, p, l)	 readsw((short*)((a) + (r)), p, l*2)
    1.61 +#define SMC_outsl(a, r, p, l)	 writesw((short*)((a) + (r)), p, l*2)
    1.62 +
    1.63 +#elif	SMC_USE_32BIT
    1.64 +#define SMC_inb(a, r)		 readb((a) + (r))
    1.65 +#define SMC_inw(a, r)		 readw((a) + (r))
    1.66 +#define SMC_inl(a, r)		 readl((a) + (r))
    1.67 +#define SMC_outb(v, a, r)	 writeb(v, (a) + (r))
    1.68 +#define SMC_outl(v, a, r)	 writel(v, (a) + (r))
    1.69 +#define SMC_insl(a, r, p, l)	 readsl((int*)((a) + (r)), p, l)
    1.70 +#define SMC_outsl(a, r, p, l)	 writesl((int*)((a) + (r)), p, l)
    1.71 +
    1.72 +#endif /* SMC_USE_16BIT */
    1.73 +
    1.74 +
    1.75 +
    1.76 +#if	 SMC_USE_PXA_DMA
    1.77 +#define SMC_USE_DMA
    1.78 +
    1.79 +/*
    1.80 + * Define the request and free functions
    1.81 + * These are unfortunately architecture specific as no generic allocation
    1.82 + * mechanism exits
    1.83 + */
    1.84 +#define SMC_DMA_REQUEST(dev, handler) \
    1.85 +	 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
    1.86 +
    1.87 +#define SMC_DMA_FREE(dev, dma) \
    1.88 +	 pxa_free_dma(dma)
    1.89 +
    1.90 +#define SMC_DMA_ACK_IRQ(dev, dma)					\
    1.91 +{									\
    1.92 +	if (DCSR(dma) & DCSR_BUSERR) {					\
    1.93 +		printk("%s: DMA %d bus error!\n", dev->name, dma);	\
    1.94 +	}								\
    1.95 +	DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;		\
    1.96 +}
    1.97 +
    1.98 +/*
    1.99 + * Use a DMA for RX and TX packets.
   1.100 + */
   1.101 +#include <linux/dma-mapping.h>
   1.102 +#include <asm/dma.h>
   1.103 +#include <asm/arch/pxa-regs.h>
   1.104 +
   1.105 +static dma_addr_t rx_dmabuf, tx_dmabuf;
   1.106 +static int rx_dmalen, tx_dmalen;
   1.107 +
   1.108 +#ifdef SMC_insl
   1.109 +#undef SMC_insl
   1.110 +#define SMC_insl(a, r, p, l) \
   1.111 +	smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
   1.112 +
   1.113 +static inline void
   1.114 +smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
   1.115 +		int reg, int dma, u_char *buf, int len)
   1.116 +{
   1.117 +	/* 64 bit alignment is required for memory to memory DMA */
   1.118 +	if ((long)buf & 4) {
   1.119 +		*((u32 *)buf) = SMC_inl(ioaddr, reg);
   1.120 +		buf += 4;
   1.121 +		len--;
   1.122 +	}
   1.123 +
   1.124 +	len *= 4;
   1.125 +	rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
   1.126 +	rx_dmalen = len;
   1.127 +	DCSR(dma) = DCSR_NODESC;
   1.128 +	DTADR(dma) = rx_dmabuf;
   1.129 +	DSADR(dma) = physaddr + reg;
   1.130 +	DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
   1.131 +		DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
   1.132 +	DCSR(dma) = DCSR_NODESC | DCSR_RUN;
   1.133 +}
   1.134 +#endif
   1.135 +
   1.136 +#ifdef SMC_insw
   1.137 +#undef SMC_insw
   1.138 +#define SMC_insw(a, r, p, l) \
   1.139 +	smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
   1.140 +
   1.141 +static inline void
   1.142 +smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
   1.143 +		int reg, int dma, u_char *buf, int len)
   1.144 +{
   1.145 +	/* 64 bit alignment is required for memory to memory DMA */
   1.146 +	while ((long)buf & 6) {
   1.147 +		*((u16 *)buf) = SMC_inw(ioaddr, reg);
   1.148 +		buf += 2;
   1.149 +		len--;
   1.150 +	}
   1.151 +
   1.152 +	len *= 2;
   1.153 +	rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
   1.154 +	rx_dmalen = len;
   1.155 +	DCSR(dma) = DCSR_NODESC;
   1.156 +	DTADR(dma) = rx_dmabuf;
   1.157 +	DSADR(dma) = physaddr + reg;
   1.158 +	DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
   1.159 +		DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
   1.160 +	DCSR(dma) = DCSR_NODESC | DCSR_RUN;
   1.161 +}
   1.162 +#endif
   1.163 +
   1.164 +#ifdef SMC_outsl
   1.165 +#undef SMC_outsl
   1.166 +#define SMC_outsl(a, r, p, l) \
   1.167 +	 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
   1.168 +
   1.169 +static inline void
   1.170 +smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
   1.171 +		int reg, int dma, u_char *buf, int len)
   1.172 +{
   1.173 +	/* 64 bit alignment is required for memory to memory DMA */
   1.174 +	if ((long)buf & 4) {
   1.175 +		SMC_outl(*((u32 *)buf), ioaddr, reg);
   1.176 +		buf += 4;
   1.177 +		len--;
   1.178 +	}
   1.179 +
   1.180 +	len *= 4;
   1.181 +	tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
   1.182 +	tx_dmalen = len;
   1.183 +	DCSR(dma) = DCSR_NODESC;
   1.184 +	DSADR(dma) = tx_dmabuf;
   1.185 +	DTADR(dma) = physaddr + reg;
   1.186 +	DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
   1.187 +		DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
   1.188 +	DCSR(dma) = DCSR_NODESC | DCSR_RUN;
   1.189 +}
   1.190 +#endif
   1.191 +
   1.192 +#ifdef SMC_outsw
   1.193 +#undef SMC_outsw
   1.194 +#define SMC_outsw(a, r, p, l) \
   1.195 +	smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
   1.196 +
   1.197 +static inline void
   1.198 +smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
   1.199 +		  int reg, int dma, u_char *buf, int len)
   1.200 +{
   1.201 +	/* 64 bit alignment is required for memory to memory DMA */
   1.202 +	while ((long)buf & 6) {
   1.203 +		SMC_outw(*((u16 *)buf), ioaddr, reg);
   1.204 +		buf += 2;
   1.205 +		len--;
   1.206 +	}
   1.207 +
   1.208 +	len *= 2;
   1.209 +	tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
   1.210 +	tx_dmalen = len;
   1.211 +	DCSR(dma) = DCSR_NODESC;
   1.212 +	DSADR(dma) = tx_dmabuf;
   1.213 +	DTADR(dma) = physaddr + reg;
   1.214 +	DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
   1.215 +		DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
   1.216 +	DCSR(dma) = DCSR_NODESC | DCSR_RUN;
   1.217 +}
   1.218 +#endif
   1.219 +
   1.220 +#endif	 /* SMC_USE_PXA_DMA */
   1.221 +
   1.222 +
   1.223 +/* Chip Parameters and Register Definitions */
   1.224 +
   1.225 +#define SMC911X_TX_FIFO_LOW_THRESHOLD	(1536*2)
   1.226 +
   1.227 +#define SMC911X_IO_EXTENT	 0x100
   1.228 +
   1.229 +#define SMC911X_EEPROM_LEN	 7
   1.230 +
   1.231 +/* Below are the register offsets and bit definitions
   1.232 + * of the Lan911x memory space
   1.233 + */
   1.234 +#define RX_DATA_FIFO		 (0x00)
   1.235 +
   1.236 +#define TX_DATA_FIFO		 (0x20)
   1.237 +#define	TX_CMD_A_INT_ON_COMP_		(0x80000000)
   1.238 +#define	TX_CMD_A_INT_BUF_END_ALGN_	(0x03000000)
   1.239 +#define	TX_CMD_A_INT_4_BYTE_ALGN_	(0x00000000)
   1.240 +#define	TX_CMD_A_INT_16_BYTE_ALGN_	(0x01000000)
   1.241 +#define	TX_CMD_A_INT_32_BYTE_ALGN_	(0x02000000)
   1.242 +#define	TX_CMD_A_INT_DATA_OFFSET_	(0x001F0000)
   1.243 +#define	TX_CMD_A_INT_FIRST_SEG_		(0x00002000)
   1.244 +#define	TX_CMD_A_INT_LAST_SEG_		(0x00001000)
   1.245 +#define	TX_CMD_A_BUF_SIZE_		(0x000007FF)
   1.246 +#define	TX_CMD_B_PKT_TAG_		(0xFFFF0000)
   1.247 +#define	TX_CMD_B_ADD_CRC_DISABLE_	(0x00002000)
   1.248 +#define	TX_CMD_B_DISABLE_PADDING_	(0x00001000)
   1.249 +#define	TX_CMD_B_PKT_BYTE_LENGTH_	(0x000007FF)
   1.250 +
   1.251 +#define RX_STATUS_FIFO		(0x40)
   1.252 +#define	RX_STS_PKT_LEN_			(0x3FFF0000)
   1.253 +#define	RX_STS_ES_			(0x00008000)
   1.254 +#define	RX_STS_BCST_			(0x00002000)
   1.255 +#define	RX_STS_LEN_ERR_			(0x00001000)
   1.256 +#define	RX_STS_RUNT_ERR_		(0x00000800)
   1.257 +#define	RX_STS_MCAST_			(0x00000400)
   1.258 +#define	RX_STS_TOO_LONG_		(0x00000080)
   1.259 +#define	RX_STS_COLL_			(0x00000040)
   1.260 +#define	RX_STS_ETH_TYPE_		(0x00000020)
   1.261 +#define	RX_STS_WDOG_TMT_		(0x00000010)
   1.262 +#define	RX_STS_MII_ERR_			(0x00000008)
   1.263 +#define	RX_STS_DRIBBLING_		(0x00000004)
   1.264 +#define	RX_STS_CRC_ERR_			(0x00000002)
   1.265 +#define RX_STATUS_FIFO_PEEK 	(0x44)
   1.266 +#define TX_STATUS_FIFO		(0x48)
   1.267 +#define	TX_STS_TAG_			(0xFFFF0000)
   1.268 +#define	TX_STS_ES_			(0x00008000)
   1.269 +#define	TX_STS_LOC_			(0x00000800)
   1.270 +#define	TX_STS_NO_CARR_			(0x00000400)
   1.271 +#define	TX_STS_LATE_COLL_		(0x00000200)
   1.272 +#define	TX_STS_MANY_COLL_		(0x00000100)
   1.273 +#define	TX_STS_COLL_CNT_		(0x00000078)
   1.274 +#define	TX_STS_MANY_DEFER_		(0x00000004)
   1.275 +#define	TX_STS_UNDERRUN_		(0x00000002)
   1.276 +#define	TX_STS_DEFERRED_		(0x00000001)
   1.277 +#define TX_STATUS_FIFO_PEEK	(0x4C)
   1.278 +#define ID_REV			(0x50)
   1.279 +#define	ID_REV_CHIP_ID_			(0xFFFF0000)  /* RO */
   1.280 +#define	ID_REV_REV_ID_			(0x0000FFFF)  /* RO */
   1.281 +
   1.282 +#define INT_CFG			(0x54)
   1.283 +#define	INT_CFG_INT_DEAS_		(0xFF000000)  /* R/W */
   1.284 +#define	INT_CFG_INT_DEAS_CLR_		(0x00004000)
   1.285 +#define	INT_CFG_INT_DEAS_STS_		(0x00002000)
   1.286 +#define	INT_CFG_IRQ_INT_		(0x00001000)  /* RO */
   1.287 +#define	INT_CFG_IRQ_EN_			(0x00000100)  /* R/W */
   1.288 +#define	INT_CFG_IRQ_POL_		(0x00000010)  /* R/W Not Affected by SW Reset */
   1.289 +#define	INT_CFG_IRQ_TYPE_		(0x00000001)  /* R/W Not Affected by SW Reset */
   1.290 +
   1.291 +#define INT_STS			(0x58)
   1.292 +#define	INT_STS_SW_INT_			(0x80000000)  /* R/WC */
   1.293 +#define	INT_STS_TXSTOP_INT_		(0x02000000)  /* R/WC */
   1.294 +#define	INT_STS_RXSTOP_INT_		(0x01000000)  /* R/WC */
   1.295 +#define	INT_STS_RXDFH_INT_		(0x00800000)  /* R/WC */
   1.296 +#define	INT_STS_RXDF_INT_		(0x00400000)  /* R/WC */
   1.297 +#define	INT_STS_TX_IOC_			(0x00200000)  /* R/WC */
   1.298 +#define	INT_STS_RXD_INT_		(0x00100000)  /* R/WC */
   1.299 +#define	INT_STS_GPT_INT_		(0x00080000)  /* R/WC */
   1.300 +#define	INT_STS_PHY_INT_		(0x00040000)  /* RO */
   1.301 +#define	INT_STS_PME_INT_		(0x00020000)  /* R/WC */
   1.302 +#define	INT_STS_TXSO_			(0x00010000)  /* R/WC */
   1.303 +#define	INT_STS_RWT_			(0x00008000)  /* R/WC */
   1.304 +#define	INT_STS_RXE_			(0x00004000)  /* R/WC */
   1.305 +#define	INT_STS_TXE_			(0x00002000)  /* R/WC */
   1.306 +//#define	INT_STS_ERX_		(0x00001000)  /* R/WC */
   1.307 +#define	INT_STS_TDFU_			(0x00000800)  /* R/WC */
   1.308 +#define	INT_STS_TDFO_			(0x00000400)  /* R/WC */
   1.309 +#define	INT_STS_TDFA_			(0x00000200)  /* R/WC */
   1.310 +#define	INT_STS_TSFF_			(0x00000100)  /* R/WC */
   1.311 +#define	INT_STS_TSFL_			(0x00000080)  /* R/WC */
   1.312 +//#define	INT_STS_RXDF_		(0x00000040)  /* R/WC */
   1.313 +#define	INT_STS_RDFO_			(0x00000040)  /* R/WC */
   1.314 +#define	INT_STS_RDFL_			(0x00000020)  /* R/WC */
   1.315 +#define	INT_STS_RSFF_			(0x00000010)  /* R/WC */
   1.316 +#define	INT_STS_RSFL_			(0x00000008)  /* R/WC */
   1.317 +#define	INT_STS_GPIO2_INT_		(0x00000004)  /* R/WC */
   1.318 +#define	INT_STS_GPIO1_INT_		(0x00000002)  /* R/WC */
   1.319 +#define	INT_STS_GPIO0_INT_		(0x00000001)  /* R/WC */
   1.320 +
   1.321 +#define INT_EN			(0x5C)
   1.322 +#define	INT_EN_SW_INT_EN_		(0x80000000)  /* R/W */
   1.323 +#define	INT_EN_TXSTOP_INT_EN_		(0x02000000)  /* R/W */
   1.324 +#define	INT_EN_RXSTOP_INT_EN_		(0x01000000)  /* R/W */
   1.325 +#define	INT_EN_RXDFH_INT_EN_		(0x00800000)  /* R/W */
   1.326 +//#define	INT_EN_RXDF_INT_EN_		(0x00400000)  /* R/W */
   1.327 +#define	INT_EN_TIOC_INT_EN_		(0x00200000)  /* R/W */
   1.328 +#define	INT_EN_RXD_INT_EN_		(0x00100000)  /* R/W */
   1.329 +#define	INT_EN_GPT_INT_EN_		(0x00080000)  /* R/W */
   1.330 +#define	INT_EN_PHY_INT_EN_		(0x00040000)  /* R/W */
   1.331 +#define	INT_EN_PME_INT_EN_		(0x00020000)  /* R/W */
   1.332 +#define	INT_EN_TXSO_EN_			(0x00010000)  /* R/W */
   1.333 +#define	INT_EN_RWT_EN_			(0x00008000)  /* R/W */
   1.334 +#define	INT_EN_RXE_EN_			(0x00004000)  /* R/W */
   1.335 +#define	INT_EN_TXE_EN_			(0x00002000)  /* R/W */
   1.336 +//#define	INT_EN_ERX_EN_			(0x00001000)  /* R/W */
   1.337 +#define	INT_EN_TDFU_EN_			(0x00000800)  /* R/W */
   1.338 +#define	INT_EN_TDFO_EN_			(0x00000400)  /* R/W */
   1.339 +#define	INT_EN_TDFA_EN_			(0x00000200)  /* R/W */
   1.340 +#define	INT_EN_TSFF_EN_			(0x00000100)  /* R/W */
   1.341 +#define	INT_EN_TSFL_EN_			(0x00000080)  /* R/W */
   1.342 +//#define	INT_EN_RXDF_EN_			(0x00000040)  /* R/W */
   1.343 +#define	INT_EN_RDFO_EN_			(0x00000040)  /* R/W */
   1.344 +#define	INT_EN_RDFL_EN_			(0x00000020)  /* R/W */
   1.345 +#define	INT_EN_RSFF_EN_			(0x00000010)  /* R/W */
   1.346 +#define	INT_EN_RSFL_EN_			(0x00000008)  /* R/W */
   1.347 +#define	INT_EN_GPIO2_INT_		(0x00000004)  /* R/W */
   1.348 +#define	INT_EN_GPIO1_INT_		(0x00000002)  /* R/W */
   1.349 +#define	INT_EN_GPIO0_INT_		(0x00000001)  /* R/W */
   1.350 +
   1.351 +#define BYTE_TEST		(0x64)
   1.352 +#define FIFO_INT		(0x68)
   1.353 +#define	FIFO_INT_TX_AVAIL_LEVEL_	(0xFF000000)  /* R/W */
   1.354 +#define	FIFO_INT_TX_STS_LEVEL_		(0x00FF0000)  /* R/W */
   1.355 +#define	FIFO_INT_RX_AVAIL_LEVEL_	(0x0000FF00)  /* R/W */
   1.356 +#define	FIFO_INT_RX_STS_LEVEL_		(0x000000FF)  /* R/W */
   1.357 +
   1.358 +#define RX_CFG			(0x6C)
   1.359 +#define	RX_CFG_RX_END_ALGN_		(0xC0000000)  /* R/W */
   1.360 +#define		RX_CFG_RX_END_ALGN4_		(0x00000000)  /* R/W */
   1.361 +#define		RX_CFG_RX_END_ALGN16_		(0x40000000)  /* R/W */
   1.362 +#define		RX_CFG_RX_END_ALGN32_		(0x80000000)  /* R/W */
   1.363 +#define	RX_CFG_RX_DMA_CNT_		(0x0FFF0000)  /* R/W */
   1.364 +#define	RX_CFG_RX_DUMP_			(0x00008000)  /* R/W */
   1.365 +#define	RX_CFG_RXDOFF_			(0x00001F00)  /* R/W */
   1.366 +//#define	RX_CFG_RXBAD_			(0x00000001)  /* R/W */
   1.367 +
   1.368 +#define TX_CFG			(0x70)
   1.369 +//#define	TX_CFG_TX_DMA_LVL_		(0xE0000000)	 /* R/W */
   1.370 +//#define	TX_CFG_TX_DMA_CNT_		(0x0FFF0000)	 /* R/W Self Clearing */
   1.371 +#define	TX_CFG_TXS_DUMP_		(0x00008000)  /* Self Clearing */
   1.372 +#define	TX_CFG_TXD_DUMP_		(0x00004000)  /* Self Clearing */
   1.373 +#define	TX_CFG_TXSAO_			(0x00000004)  /* R/W */
   1.374 +#define	TX_CFG_TX_ON_			(0x00000002)  /* R/W */
   1.375 +#define	TX_CFG_STOP_TX_			(0x00000001)  /* Self Clearing */
   1.376 +
   1.377 +#define HW_CFG			(0x74)
   1.378 +#define	HW_CFG_TTM_			(0x00200000)  /* R/W */
   1.379 +#define	HW_CFG_SF_			(0x00100000)  /* R/W */
   1.380 +#define	HW_CFG_TX_FIF_SZ_		(0x000F0000)  /* R/W */
   1.381 +#define	HW_CFG_TR_			(0x00003000)  /* R/W */
   1.382 +#define	HW_CFG_PHY_CLK_SEL_		(0x00000060)  /* R/W */
   1.383 +#define		 HW_CFG_PHY_CLK_SEL_INT_PHY_ 	(0x00000000) /* R/W */
   1.384 +#define		 HW_CFG_PHY_CLK_SEL_EXT_PHY_ 	(0x00000020) /* R/W */
   1.385 +#define		 HW_CFG_PHY_CLK_SEL_CLK_DIS_ 	(0x00000040) /* R/W */
   1.386 +#define	HW_CFG_SMI_SEL_			(0x00000010)  /* R/W */
   1.387 +#define	HW_CFG_EXT_PHY_DET_		(0x00000008)  /* RO */
   1.388 +#define	HW_CFG_EXT_PHY_EN_		(0x00000004)  /* R/W */
   1.389 +#define	HW_CFG_32_16_BIT_MODE_		(0x00000004)  /* RO */
   1.390 +#define	HW_CFG_SRST_TO_			(0x00000002)  /* RO */
   1.391 +#define	HW_CFG_SRST_			(0x00000001)  /* Self Clearing */
   1.392 +
   1.393 +#define RX_DP_CTRL		(0x78)
   1.394 +#define	RX_DP_CTRL_RX_FFWD_		(0x80000000)  /* R/W */
   1.395 +#define	RX_DP_CTRL_FFWD_BUSY_		(0x80000000)  /* RO */
   1.396 +
   1.397 +#define RX_FIFO_INF		(0x7C)
   1.398 +#define	 RX_FIFO_INF_RXSUSED_		(0x00FF0000)  /* RO */
   1.399 +#define	 RX_FIFO_INF_RXDUSED_		(0x0000FFFF)  /* RO */
   1.400 +
   1.401 +#define TX_FIFO_INF		(0x80)
   1.402 +#define	TX_FIFO_INF_TSUSED_		(0x00FF0000)  /* RO */
   1.403 +#define	TX_FIFO_INF_TDFREE_		(0x0000FFFF)  /* RO */
   1.404 +
   1.405 +#define PMT_CTRL		(0x84)
   1.406 +#define	PMT_CTRL_PM_MODE_		(0x00003000)  /* Self Clearing */
   1.407 +#define	PMT_CTRL_PHY_RST_		(0x00000400)  /* Self Clearing */
   1.408 +#define	PMT_CTRL_WOL_EN_		(0x00000200)  /* R/W */
   1.409 +#define	PMT_CTRL_ED_EN_			(0x00000100)  /* R/W */
   1.410 +#define	PMT_CTRL_PME_TYPE_		(0x00000040)  /* R/W Not Affected by SW Reset */
   1.411 +#define	PMT_CTRL_WUPS_			(0x00000030)  /* R/WC */
   1.412 +#define		PMT_CTRL_WUPS_NOWAKE_		(0x00000000)  /* R/WC */
   1.413 +#define		PMT_CTRL_WUPS_ED_		(0x00000010)  /* R/WC */
   1.414 +#define		PMT_CTRL_WUPS_WOL_		(0x00000020)  /* R/WC */
   1.415 +#define		PMT_CTRL_WUPS_MULTI_		(0x00000030)  /* R/WC */
   1.416 +#define	PMT_CTRL_PME_IND_		(0x00000008)  /* R/W */
   1.417 +#define	PMT_CTRL_PME_POL_		(0x00000004)  /* R/W */
   1.418 +#define	PMT_CTRL_PME_EN_		(0x00000002)  /* R/W Not Affected by SW Reset */
   1.419 +#define	PMT_CTRL_READY_			(0x00000001)  /* RO */
   1.420 +
   1.421 +#define GPIO_CFG		(0x88)
   1.422 +#define	GPIO_CFG_LED3_EN_		(0x40000000)  /* R/W */
   1.423 +#define	GPIO_CFG_LED2_EN_		(0x20000000)  /* R/W */
   1.424 +#define	GPIO_CFG_LED1_EN_		(0x10000000)  /* R/W */
   1.425 +#define	GPIO_CFG_GPIO2_INT_POL_		(0x04000000)  /* R/W */
   1.426 +#define	GPIO_CFG_GPIO1_INT_POL_		(0x02000000)  /* R/W */
   1.427 +#define	GPIO_CFG_GPIO0_INT_POL_		(0x01000000)  /* R/W */
   1.428 +#define	GPIO_CFG_EEPR_EN_		(0x00700000)  /* R/W */
   1.429 +#define	GPIO_CFG_GPIOBUF2_		(0x00040000)  /* R/W */
   1.430 +#define	GPIO_CFG_GPIOBUF1_		(0x00020000)  /* R/W */
   1.431 +#define	GPIO_CFG_GPIOBUF0_		(0x00010000)  /* R/W */
   1.432 +#define	GPIO_CFG_GPIODIR2_		(0x00000400)  /* R/W */
   1.433 +#define	GPIO_CFG_GPIODIR1_		(0x00000200)  /* R/W */
   1.434 +#define	GPIO_CFG_GPIODIR0_		(0x00000100)  /* R/W */
   1.435 +#define	GPIO_CFG_GPIOD4_		(0x00000010)  /* R/W */
   1.436 +#define	GPIO_CFG_GPIOD3_		(0x00000008)  /* R/W */
   1.437 +#define	GPIO_CFG_GPIOD2_		(0x00000004)  /* R/W */
   1.438 +#define	GPIO_CFG_GPIOD1_		(0x00000002)  /* R/W */
   1.439 +#define	GPIO_CFG_GPIOD0_		(0x00000001)  /* R/W */
   1.440 +
   1.441 +#define GPT_CFG			(0x8C)
   1.442 +#define	GPT_CFG_TIMER_EN_		(0x20000000)  /* R/W */
   1.443 +#define	GPT_CFG_GPT_LOAD_		(0x0000FFFF)  /* R/W */
   1.444 +
   1.445 +#define GPT_CNT			(0x90)
   1.446 +#define	GPT_CNT_GPT_CNT_		(0x0000FFFF)  /* RO */
   1.447 +
   1.448 +#define ENDIAN			(0x98)
   1.449 +#define FREE_RUN		(0x9C)
   1.450 +#define RX_DROP			(0xA0)
   1.451 +#define MAC_CSR_CMD		(0xA4)
   1.452 +#define	 MAC_CSR_CMD_CSR_BUSY_		(0x80000000)  /* Self Clearing */
   1.453 +#define	 MAC_CSR_CMD_R_NOT_W_		(0x40000000)  /* R/W */
   1.454 +#define	 MAC_CSR_CMD_CSR_ADDR_		(0x000000FF)  /* R/W */
   1.455 +
   1.456 +#define MAC_CSR_DATA		(0xA8)
   1.457 +#define AFC_CFG			(0xAC)
   1.458 +#define		AFC_CFG_AFC_HI_			(0x00FF0000)  /* R/W */
   1.459 +#define		AFC_CFG_AFC_LO_			(0x0000FF00)  /* R/W */
   1.460 +#define		AFC_CFG_BACK_DUR_		(0x000000F0)  /* R/W */
   1.461 +#define		AFC_CFG_FCMULT_			(0x00000008)  /* R/W */
   1.462 +#define		AFC_CFG_FCBRD_			(0x00000004)  /* R/W */
   1.463 +#define		AFC_CFG_FCADD_			(0x00000002)  /* R/W */
   1.464 +#define		AFC_CFG_FCANY_			(0x00000001)  /* R/W */
   1.465 +
   1.466 +#define E2P_CMD			(0xB0)
   1.467 +#define	E2P_CMD_EPC_BUSY_		(0x80000000)  /* Self Clearing */
   1.468 +#define	E2P_CMD_EPC_CMD_			(0x70000000)  /* R/W */
   1.469 +#define		E2P_CMD_EPC_CMD_READ_		(0x00000000)  /* R/W */
   1.470 +#define		E2P_CMD_EPC_CMD_EWDS_		(0x10000000)  /* R/W */
   1.471 +#define		E2P_CMD_EPC_CMD_EWEN_		(0x20000000)  /* R/W */
   1.472 +#define		E2P_CMD_EPC_CMD_WRITE_		(0x30000000)  /* R/W */
   1.473 +#define		E2P_CMD_EPC_CMD_WRAL_		(0x40000000)  /* R/W */
   1.474 +#define		E2P_CMD_EPC_CMD_ERASE_		(0x50000000)  /* R/W */
   1.475 +#define		E2P_CMD_EPC_CMD_ERAL_		(0x60000000)  /* R/W */
   1.476 +#define		E2P_CMD_EPC_CMD_RELOAD_		(0x70000000)  /* R/W */
   1.477 +#define	E2P_CMD_EPC_TIMEOUT_		(0x00000200)  /* RO */
   1.478 +#define	E2P_CMD_MAC_ADDR_LOADED_	(0x00000100)  /* RO */
   1.479 +#define	E2P_CMD_EPC_ADDR_		(0x000000FF)  /* R/W */
   1.480 +
   1.481 +#define E2P_DATA		(0xB4)
   1.482 +#define	E2P_DATA_EEPROM_DATA_		(0x000000FF)  /* R/W */
   1.483 +/* end of LAN register offsets and bit definitions */
   1.484 +
   1.485 +/*
   1.486 + ****************************************************************************
   1.487 + ****************************************************************************
   1.488 + * MAC Control and Status Register (Indirect Address)
   1.489 + * Offset (through the MAC_CSR CMD and DATA port)
   1.490 + ****************************************************************************
   1.491 + ****************************************************************************
   1.492 + *
   1.493 + */
   1.494 +#define MAC_CR			(0x01)  /* R/W */
   1.495 +
   1.496 +/* MAC_CR - MAC Control Register */
   1.497 +#define MAC_CR_RXALL_			(0x80000000)
   1.498 +// TODO: delete this bit? It is not described in the data sheet.
   1.499 +#define MAC_CR_HBDIS_			(0x10000000)
   1.500 +#define MAC_CR_RCVOWN_			(0x00800000)
   1.501 +#define MAC_CR_LOOPBK_			(0x00200000)
   1.502 +#define MAC_CR_FDPX_			(0x00100000)
   1.503 +#define MAC_CR_MCPAS_			(0x00080000)
   1.504 +#define MAC_CR_PRMS_			(0x00040000)
   1.505 +#define MAC_CR_INVFILT_			(0x00020000)
   1.506 +#define MAC_CR_PASSBAD_			(0x00010000)
   1.507 +#define MAC_CR_HFILT_			(0x00008000)
   1.508 +#define MAC_CR_HPFILT_			(0x00002000)
   1.509 +#define MAC_CR_LCOLL_			(0x00001000)
   1.510 +#define MAC_CR_BCAST_			(0x00000800)
   1.511 +#define MAC_CR_DISRTY_			(0x00000400)
   1.512 +#define MAC_CR_PADSTR_			(0x00000100)
   1.513 +#define MAC_CR_BOLMT_MASK_		(0x000000C0)
   1.514 +#define MAC_CR_DFCHK_			(0x00000020)
   1.515 +#define MAC_CR_TXEN_			(0x00000008)
   1.516 +#define MAC_CR_RXEN_			(0x00000004)
   1.517 +
   1.518 +#define ADDRH			(0x02)	  /* R/W mask 0x0000FFFFUL */
   1.519 +#define ADDRL			(0x03)	  /* R/W mask 0xFFFFFFFFUL */
   1.520 +#define HASHH			(0x04)	  /* R/W */
   1.521 +#define HASHL			(0x05)	  /* R/W */
   1.522 +
   1.523 +#define MII_ACC			(0x06)	  /* R/W */
   1.524 +#define MII_ACC_PHY_ADDR_		(0x0000F800)
   1.525 +#define MII_ACC_MIIRINDA_		(0x000007C0)
   1.526 +#define MII_ACC_MII_WRITE_		(0x00000002)
   1.527 +#define MII_ACC_MII_BUSY_		(0x00000001)
   1.528 +
   1.529 +#define MII_DATA		(0x07)	  /* R/W mask 0x0000FFFFUL */
   1.530 +
   1.531 +#define FLOW			(0x08)	  /* R/W */
   1.532 +#define FLOW_FCPT_			(0xFFFF0000)
   1.533 +#define FLOW_FCPASS_			(0x00000004)
   1.534 +#define FLOW_FCEN_			(0x00000002)
   1.535 +#define FLOW_FCBSY_			(0x00000001)
   1.536 +
   1.537 +#define VLAN1			(0x09)	  /* R/W mask 0x0000FFFFUL */
   1.538 +#define VLAN1_VTI1_			(0x0000ffff)
   1.539 +
   1.540 +#define VLAN2			(0x0A)	  /* R/W mask 0x0000FFFFUL */
   1.541 +#define VLAN2_VTI2_			(0x0000ffff)
   1.542 +
   1.543 +#define WUFF			(0x0B)	  /* WO */
   1.544 +
   1.545 +#define WUCSR			(0x0C)	  /* R/W */
   1.546 +#define WUCSR_GUE_			(0x00000200)
   1.547 +#define WUCSR_WUFR_			(0x00000040)
   1.548 +#define WUCSR_MPR_			(0x00000020)
   1.549 +#define WUCSR_WAKE_EN_			(0x00000004)
   1.550 +#define WUCSR_MPEN_			(0x00000002)
   1.551 +
   1.552 +/*
   1.553 + ****************************************************************************
   1.554 + * Chip Specific MII Defines
   1.555 + ****************************************************************************
   1.556 + *
   1.557 + * Phy register offsets and bit definitions
   1.558 + *
   1.559 + */
   1.560 +
   1.561 +#define PHY_MODE_CTRL_STS	((u32)17)	/* Mode Control/Status Register */
   1.562 +//#define MODE_CTRL_STS_FASTRIP_	  ((u16)0x4000)
   1.563 +#define MODE_CTRL_STS_EDPWRDOWN_	 ((u16)0x2000)
   1.564 +//#define MODE_CTRL_STS_LOWSQEN_	   ((u16)0x0800)
   1.565 +//#define MODE_CTRL_STS_MDPREBP_	   ((u16)0x0400)
   1.566 +//#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
   1.567 +//#define MODE_CTRL_STS_FASTEST_	   ((u16)0x0100)
   1.568 +//#define MODE_CTRL_STS_REFCLKEN_	   ((u16)0x0010)
   1.569 +//#define MODE_CTRL_STS_PHYADBP_	   ((u16)0x0008)
   1.570 +//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
   1.571 +#define MODE_CTRL_STS_ENERGYON_	 	((u16)0x0002)
   1.572 +
   1.573 +#define PHY_INT_SRC			((u32)29)
   1.574 +#define PHY_INT_SRC_ENERGY_ON_			((u16)0x0080)
   1.575 +#define PHY_INT_SRC_ANEG_COMP_			((u16)0x0040)
   1.576 +#define PHY_INT_SRC_REMOTE_FAULT_		((u16)0x0020)
   1.577 +#define PHY_INT_SRC_LINK_DOWN_			((u16)0x0010)
   1.578 +#define PHY_INT_SRC_ANEG_LP_ACK_		((u16)0x0008)
   1.579 +#define PHY_INT_SRC_PAR_DET_FAULT_		((u16)0x0004)
   1.580 +#define PHY_INT_SRC_ANEG_PGRX_			((u16)0x0002)
   1.581 +
   1.582 +#define PHY_INT_MASK			((u32)30)
   1.583 +#define PHY_INT_MASK_ENERGY_ON_			((u16)0x0080)
   1.584 +#define PHY_INT_MASK_ANEG_COMP_			((u16)0x0040)
   1.585 +#define PHY_INT_MASK_REMOTE_FAULT_		((u16)0x0020)
   1.586 +#define PHY_INT_MASK_LINK_DOWN_			((u16)0x0010)
   1.587 +#define PHY_INT_MASK_ANEG_LP_ACK_		((u16)0x0008)
   1.588 +#define PHY_INT_MASK_PAR_DET_FAULT_		((u16)0x0004)
   1.589 +#define PHY_INT_MASK_ANEG_PGRX_			((u16)0x0002)
   1.590 +
   1.591 +#define PHY_SPECIAL			((u32)31)
   1.592 +#define PHY_SPECIAL_ANEG_DONE_			((u16)0x1000)
   1.593 +#define PHY_SPECIAL_RES_			((u16)0x0040)
   1.594 +#define PHY_SPECIAL_RES_MASK_			((u16)0x0FE1)
   1.595 +#define PHY_SPECIAL_SPD_			((u16)0x001C)
   1.596 +#define PHY_SPECIAL_SPD_10HALF_			((u16)0x0004)
   1.597 +#define PHY_SPECIAL_SPD_10FULL_			((u16)0x0014)
   1.598 +#define PHY_SPECIAL_SPD_100HALF_		((u16)0x0008)
   1.599 +#define PHY_SPECIAL_SPD_100FULL_		((u16)0x0018)
   1.600 +
   1.601 +#define LAN911X_INTERNAL_PHY_ID		(0x0007C000)
   1.602 +
   1.603 +/* Chip ID values */
   1.604 +#define CHIP_9115	0x115
   1.605 +#define CHIP_9116	0x116
   1.606 +#define CHIP_9117	0x117
   1.607 +#define CHIP_9118	0x118
   1.608 +
   1.609 +struct chip_id {
   1.610 +	u16 id;
   1.611 +	char *name;
   1.612 +};
   1.613 +
   1.614 +static const struct chip_id chip_ids[] =  {
   1.615 +	{ CHIP_9115, "LAN9115" },
   1.616 +	{ CHIP_9116, "LAN9116" },
   1.617 +	{ CHIP_9117, "LAN9117" },
   1.618 +	{ CHIP_9118, "LAN9118" },
   1.619 +	{ 0, NULL },
   1.620 +};
   1.621 +
   1.622 +#define IS_REV_A(x)	((x & 0xFFFF)==0)
   1.623 +
   1.624 +/*
   1.625 + * Macros to abstract register access according to the data bus
   1.626 + * capabilities.  Please use those and not the in/out primitives.
   1.627 + */
   1.628 +/* FIFO read/write macros */
   1.629 +#define SMC_PUSH_DATA(p, l)	SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
   1.630 +#define SMC_PULL_DATA(p, l)	SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
   1.631 +#define SMC_SET_TX_FIFO(x) 	SMC_outl( x, ioaddr, TX_DATA_FIFO )
   1.632 +#define SMC_GET_RX_FIFO()	SMC_inl( ioaddr, RX_DATA_FIFO )
   1.633 +
   1.634 +
   1.635 +/* I/O mapped register read/write macros */
   1.636 +#define SMC_GET_TX_STS_FIFO()		SMC_inl( ioaddr, TX_STATUS_FIFO )
   1.637 +#define SMC_GET_RX_STS_FIFO()		SMC_inl( ioaddr, RX_STATUS_FIFO )
   1.638 +#define SMC_GET_RX_STS_FIFO_PEEK()	SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
   1.639 +#define SMC_GET_PN()			(SMC_inl( ioaddr, ID_REV ) >> 16)
   1.640 +#define SMC_GET_REV()			(SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
   1.641 +#define SMC_GET_IRQ_CFG()		SMC_inl( ioaddr, INT_CFG )
   1.642 +#define SMC_SET_IRQ_CFG(x)		SMC_outl( x, ioaddr, INT_CFG )
   1.643 +#define SMC_GET_INT()			SMC_inl( ioaddr, INT_STS )
   1.644 +#define SMC_ACK_INT(x)			SMC_outl( x, ioaddr, INT_STS )
   1.645 +#define SMC_GET_INT_EN()		SMC_inl( ioaddr, INT_EN )
   1.646 +#define SMC_SET_INT_EN(x)		SMC_outl( x, ioaddr, INT_EN )
   1.647 +#define SMC_GET_BYTE_TEST()		SMC_inl( ioaddr, BYTE_TEST )
   1.648 +#define SMC_SET_BYTE_TEST(x)		SMC_outl( x, ioaddr, BYTE_TEST )
   1.649 +#define SMC_GET_FIFO_INT()		SMC_inl( ioaddr, FIFO_INT )
   1.650 +#define SMC_SET_FIFO_INT(x)		SMC_outl( x, ioaddr, FIFO_INT )
   1.651 +#define SMC_SET_FIFO_TDA(x)					\
   1.652 +	do {							\
   1.653 +		unsigned long __flags;				\
   1.654 +		int __mask;					\
   1.655 +		local_irq_save(__flags);			\
   1.656 +		__mask = SMC_GET_FIFO_INT() & ~(0xFF<<24);	\
   1.657 +		SMC_SET_FIFO_INT( __mask | (x)<<24 );		\
   1.658 +		local_irq_restore(__flags);			\
   1.659 +	} while (0)
   1.660 +#define SMC_SET_FIFO_TSL(x)					\
   1.661 +	do {							\
   1.662 +		unsigned long __flags;				\
   1.663 +		int __mask;					\
   1.664 +		local_irq_save(__flags);			\
   1.665 +		__mask = SMC_GET_FIFO_INT() & ~(0xFF<<16);	\
   1.666 +		SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16));	\
   1.667 +		local_irq_restore(__flags);			\
   1.668 +	} while (0)
   1.669 +#define SMC_SET_FIFO_RSA(x)					\
   1.670 +	do {							\
   1.671 +		unsigned long __flags;				\
   1.672 +		int __mask;					\
   1.673 +		local_irq_save(__flags);			\
   1.674 +		__mask = SMC_GET_FIFO_INT() & ~(0xFF<<8);	\
   1.675 +		SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8));	\
   1.676 +		local_irq_restore(__flags);			\
   1.677 +	} while (0)
   1.678 +#define SMC_SET_FIFO_RSL(x)					\
   1.679 +	do {							\
   1.680 +		unsigned long __flags;				\
   1.681 +		int __mask;					\
   1.682 +		local_irq_save(__flags);			\
   1.683 +		__mask = SMC_GET_FIFO_INT() & ~0xFF;		\
   1.684 +		SMC_SET_FIFO_INT( __mask | ((x) & 0xFF));	\
   1.685 +		local_irq_restore(__flags);			\
   1.686 +	} while (0)
   1.687 +#define SMC_GET_RX_CFG()		SMC_inl( ioaddr, RX_CFG )
   1.688 +#define SMC_SET_RX_CFG(x)		SMC_outl( x, ioaddr, RX_CFG )
   1.689 +#define SMC_GET_TX_CFG()		SMC_inl( ioaddr, TX_CFG )
   1.690 +#define SMC_SET_TX_CFG(x)		SMC_outl( x, ioaddr, TX_CFG )
   1.691 +#define SMC_GET_HW_CFG()		SMC_inl( ioaddr, HW_CFG )
   1.692 +#define SMC_SET_HW_CFG(x)		SMC_outl( x, ioaddr, HW_CFG )
   1.693 +#define SMC_GET_RX_DP_CTRL()		SMC_inl( ioaddr, RX_DP_CTRL )
   1.694 +#define SMC_SET_RX_DP_CTRL(x)		SMC_outl( x, ioaddr, RX_DP_CTRL )
   1.695 +#define SMC_GET_PMT_CTRL()		SMC_inl( ioaddr, PMT_CTRL )
   1.696 +#define SMC_SET_PMT_CTRL(x)		SMC_outl( x, ioaddr, PMT_CTRL )
   1.697 +#define SMC_GET_GPIO_CFG()		SMC_inl( ioaddr, GPIO_CFG )
   1.698 +#define SMC_SET_GPIO_CFG(x)		SMC_outl( x, ioaddr, GPIO_CFG )
   1.699 +#define SMC_GET_RX_FIFO_INF()		SMC_inl( ioaddr, RX_FIFO_INF )
   1.700 +#define SMC_SET_RX_FIFO_INF(x)		SMC_outl( x, ioaddr, RX_FIFO_INF )
   1.701 +#define SMC_GET_TX_FIFO_INF()		SMC_inl( ioaddr, TX_FIFO_INF )
   1.702 +#define SMC_SET_TX_FIFO_INF(x)		SMC_outl( x, ioaddr, TX_FIFO_INF )
   1.703 +#define SMC_GET_GPT_CFG()		SMC_inl( ioaddr, GPT_CFG )
   1.704 +#define SMC_SET_GPT_CFG(x)		SMC_outl( x, ioaddr, GPT_CFG )
   1.705 +#define SMC_GET_RX_DROP()		SMC_inl( ioaddr, RX_DROP )
   1.706 +#define SMC_SET_RX_DROP(x)		SMC_outl( x, ioaddr, RX_DROP )
   1.707 +#define SMC_GET_MAC_CMD()		SMC_inl( ioaddr, MAC_CSR_CMD )
   1.708 +#define SMC_SET_MAC_CMD(x)		SMC_outl( x, ioaddr, MAC_CSR_CMD )
   1.709 +#define SMC_GET_MAC_DATA()		SMC_inl( ioaddr, MAC_CSR_DATA )
   1.710 +#define SMC_SET_MAC_DATA(x)		SMC_outl( x, ioaddr, MAC_CSR_DATA )
   1.711 +#define SMC_GET_AFC_CFG()		SMC_inl( ioaddr, AFC_CFG )
   1.712 +#define SMC_SET_AFC_CFG(x)		SMC_outl( x, ioaddr, AFC_CFG )
   1.713 +#define SMC_GET_E2P_CMD()		SMC_inl( ioaddr, E2P_CMD )
   1.714 +#define SMC_SET_E2P_CMD(x)		SMC_outl( x, ioaddr, E2P_CMD )
   1.715 +#define SMC_GET_E2P_DATA()		SMC_inl( ioaddr, E2P_DATA )
   1.716 +#define SMC_SET_E2P_DATA(x)		SMC_outl( x, ioaddr, E2P_DATA )
   1.717 +
   1.718 +/* MAC register read/write macros */
   1.719 +#define SMC_GET_MAC_CSR(a,v)						\
   1.720 +	do {								\
   1.721 +		while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);	\
   1.722 +		SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ |			\
   1.723 +			MAC_CSR_CMD_R_NOT_W_ | (a) );			\
   1.724 +		while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);	\
   1.725 +		v = SMC_GET_MAC_DATA();					\
   1.726 +	} while (0)
   1.727 +#define SMC_SET_MAC_CSR(a,v)						\
   1.728 +	do {								\
   1.729 +		while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);	\
   1.730 +		SMC_SET_MAC_DATA(v);					\
   1.731 +		SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) );		\
   1.732 +		while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);	\
   1.733 +	} while (0)
   1.734 +#define SMC_GET_MAC_CR(x)	SMC_GET_MAC_CSR( MAC_CR, x )
   1.735 +#define SMC_SET_MAC_CR(x)	SMC_SET_MAC_CSR( MAC_CR, x )
   1.736 +#define SMC_GET_ADDRH(x)	SMC_GET_MAC_CSR( ADDRH, x )
   1.737 +#define SMC_SET_ADDRH(x)	SMC_SET_MAC_CSR( ADDRH, x )
   1.738 +#define SMC_GET_ADDRL(x)	SMC_GET_MAC_CSR( ADDRL, x )
   1.739 +#define SMC_SET_ADDRL(x)	SMC_SET_MAC_CSR( ADDRL, x )
   1.740 +#define SMC_GET_HASHH(x)	SMC_GET_MAC_CSR( HASHH, x )
   1.741 +#define SMC_SET_HASHH(x)	SMC_SET_MAC_CSR( HASHH, x )
   1.742 +#define SMC_GET_HASHL(x)	SMC_GET_MAC_CSR( HASHL, x )
   1.743 +#define SMC_SET_HASHL(x)	SMC_SET_MAC_CSR( HASHL, x )
   1.744 +#define SMC_GET_MII_ACC(x)	SMC_GET_MAC_CSR( MII_ACC, x )
   1.745 +#define SMC_SET_MII_ACC(x)	SMC_SET_MAC_CSR( MII_ACC, x )
   1.746 +#define SMC_GET_MII_DATA(x)	SMC_GET_MAC_CSR( MII_DATA, x )
   1.747 +#define SMC_SET_MII_DATA(x)	SMC_SET_MAC_CSR( MII_DATA, x )
   1.748 +#define SMC_GET_FLOW(x)		SMC_GET_MAC_CSR( FLOW, x )
   1.749 +#define SMC_SET_FLOW(x)		SMC_SET_MAC_CSR( FLOW, x )
   1.750 +#define SMC_GET_VLAN1(x)	SMC_GET_MAC_CSR( VLAN1, x )
   1.751 +#define SMC_SET_VLAN1(x)	SMC_SET_MAC_CSR( VLAN1, x )
   1.752 +#define SMC_GET_VLAN2(x)	SMC_GET_MAC_CSR( VLAN2, x )
   1.753 +#define SMC_SET_VLAN2(x)	SMC_SET_MAC_CSR( VLAN2, x )
   1.754 +#define SMC_SET_WUFF(x)		SMC_SET_MAC_CSR( WUFF, x )
   1.755 +#define SMC_GET_WUCSR(x)	SMC_GET_MAC_CSR( WUCSR, x )
   1.756 +#define SMC_SET_WUCSR(x)	SMC_SET_MAC_CSR( WUCSR, x )
   1.757 +
   1.758 +/* PHY register read/write macros */
   1.759 +#define SMC_GET_MII(a,phy,v)					\
   1.760 +	do {							\
   1.761 +		u32 __v;					\
   1.762 +		do {						\
   1.763 +			SMC_GET_MII_ACC(__v);			\
   1.764 +		} while ( __v & MII_ACC_MII_BUSY_ );		\
   1.765 +		SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |	\
   1.766 +			MII_ACC_MII_BUSY_);			\
   1.767 +		do {						\
   1.768 +			SMC_GET_MII_ACC(__v);			\
   1.769 +		} while ( __v & MII_ACC_MII_BUSY_ );		\
   1.770 +		SMC_GET_MII_DATA(v);				\
   1.771 +	} while (0)
   1.772 +#define SMC_SET_MII(a,phy,v)					\
   1.773 +	do {							\
   1.774 +		u32 __v;					\
   1.775 +		do {						\
   1.776 +			SMC_GET_MII_ACC(__v);			\
   1.777 +		} while ( __v & MII_ACC_MII_BUSY_ );		\
   1.778 +		SMC_SET_MII_DATA(v);				\
   1.779 +		SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |	\
   1.780 +			MII_ACC_MII_BUSY_	 |		\
   1.781 +			MII_ACC_MII_WRITE_  );			\
   1.782 +		do {						\
   1.783 +			SMC_GET_MII_ACC(__v);			\
   1.784 +		} while ( __v & MII_ACC_MII_BUSY_ );		\
   1.785 +	} while (0)
   1.786 +#define SMC_GET_PHY_BMCR(phy,x)		SMC_GET_MII( MII_BMCR, phy, x )
   1.787 +#define SMC_SET_PHY_BMCR(phy,x)		SMC_SET_MII( MII_BMCR, phy, x )
   1.788 +#define SMC_GET_PHY_BMSR(phy,x)		SMC_GET_MII( MII_BMSR, phy, x )
   1.789 +#define SMC_GET_PHY_ID1(phy,x)		SMC_GET_MII( MII_PHYSID1, phy, x )
   1.790 +#define SMC_GET_PHY_ID2(phy,x)		SMC_GET_MII( MII_PHYSID2, phy, x )
   1.791 +#define SMC_GET_PHY_MII_ADV(phy,x)	SMC_GET_MII( MII_ADVERTISE, phy, x )
   1.792 +#define SMC_SET_PHY_MII_ADV(phy,x)	SMC_SET_MII( MII_ADVERTISE, phy, x )
   1.793 +#define SMC_GET_PHY_MII_LPA(phy,x)	SMC_GET_MII( MII_LPA, phy, x )
   1.794 +#define SMC_SET_PHY_MII_LPA(phy,x)	SMC_SET_MII( MII_LPA, phy, x )
   1.795 +#define SMC_GET_PHY_CTRL_STS(phy,x)	SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
   1.796 +#define SMC_SET_PHY_CTRL_STS(phy,x)	SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
   1.797 +#define SMC_GET_PHY_INT_SRC(phy,x)	SMC_GET_MII( PHY_INT_SRC, phy, x )
   1.798 +#define SMC_SET_PHY_INT_SRC(phy,x)	SMC_SET_MII( PHY_INT_SRC, phy, x )
   1.799 +#define SMC_GET_PHY_INT_MASK(phy,x)	SMC_GET_MII( PHY_INT_MASK, phy, x )
   1.800 +#define SMC_SET_PHY_INT_MASK(phy,x)	SMC_SET_MII( PHY_INT_MASK, phy, x )
   1.801 +#define SMC_GET_PHY_SPECIAL(phy,x)	SMC_GET_MII( PHY_SPECIAL, phy, x )
   1.802 +
   1.803 +
   1.804 +
   1.805 +/* Misc read/write macros */
   1.806 +
   1.807 +#ifndef SMC_GET_MAC_ADDR
   1.808 +#define SMC_GET_MAC_ADDR(addr)					\
   1.809 +	do {							\
   1.810 +		unsigned int __v;				\
   1.811 +								\
   1.812 +		SMC_GET_MAC_CSR(ADDRL, __v);			\
   1.813 +		addr[0] = __v; addr[1] = __v >> 8;		\
   1.814 +		addr[2] = __v >> 16; addr[3] = __v >> 24;	\
   1.815 +		SMC_GET_MAC_CSR(ADDRH, __v);			\
   1.816 +		addr[4] = __v; addr[5] = __v >> 8;		\
   1.817 +	} while (0)
   1.818 +#endif
   1.819 +
   1.820 +#define SMC_SET_MAC_ADDR(addr)					\
   1.821 +	do {							\
   1.822 +		 SMC_SET_MAC_CSR(ADDRL,				\
   1.823 +				 addr[0] |			\
   1.824 +				(addr[1] << 8) |		\
   1.825 +				(addr[2] << 16) |		\
   1.826 +				(addr[3] << 24));		\
   1.827 +		 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
   1.828 +	} while (0)
   1.829 +
   1.830 +
   1.831 +#define SMC_WRITE_EEPROM_CMD(cmd, addr)					\
   1.832 +	do {								\
   1.833 +		while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_);	\
   1.834 +		SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a );		\
   1.835 +		while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);	\
   1.836 +	} while (0)
   1.837 +
   1.838 +#endif	 /* _SMC911X_H_ */