ia64/linux-2.6.18-xen.hg

diff arch/v850/kernel/v850e_cache.c @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
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     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/arch/v850/kernel/v850e_cache.c	Wed Apr 11 14:15:44 2007 +0100
     1.3 @@ -0,0 +1,174 @@
     1.4 +/*
     1.5 + * arch/v850/kernel/v850e_cache.c -- Cache control for V850E cache memories
     1.6 + *
     1.7 + *  Copyright (C) 2003  NEC Electronics Corporation
     1.8 + *  Copyright (C) 2003  Miles Bader <miles@gnu.org>
     1.9 + *
    1.10 + * This file is subject to the terms and conditions of the GNU General
    1.11 + * Public License.  See the file COPYING in the main directory of this
    1.12 + * archive for more details.
    1.13 + *
    1.14 + * Written by Miles Bader <miles@gnu.org>
    1.15 + */
    1.16 +
    1.17 +/* This file implements cache control for the rather simple cache used on
    1.18 +   some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
    1.19 +   CPU.  V850E2 processors have their own (better) cache
    1.20 +   implementation.  */
    1.21 +
    1.22 +#include <asm/entry.h>
    1.23 +#include <asm/cacheflush.h>
    1.24 +#include <asm/v850e_cache.h>
    1.25 +
    1.26 +#define WAIT_UNTIL_CLEAR(value) while (value) {}
    1.27 +
    1.28 +/* Set caching params via the BHC and DCC registers.  */
    1.29 +void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc)
    1.30 +{
    1.31 +	unsigned long *r0_ram = (unsigned long *)R0_RAM_ADDR;
    1.32 +	register u16 bhc_val asm ("r6") = bhc;
    1.33 +
    1.34 +	/* Read the instruction cache control register (ICC) and confirm
    1.35 +	   that bits 0 and 1 (TCLR0, TCLR1) are all cleared.  */
    1.36 +	WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
    1.37 +	V850E_CACHE_ICC = icc;
    1.38 +
    1.39 +#ifdef V850E_CACHE_DCC
    1.40 +	/* Configure data-cache.  */
    1.41 +	V850E_CACHE_DCC = dcc;
    1.42 +#endif /* V850E_CACHE_DCC */
    1.43 +
    1.44 +	/* Configure caching for various memory regions by writing the BHC
    1.45 +	   register.  The documentation says that an instruction _cannot_
    1.46 +	   enable/disable caching for the memory region in which the
    1.47 +	   instruction itself exists; to work around this, we store
    1.48 +	   appropriate instructions into the on-chip RAM area (which is never
    1.49 +	   cached), and briefly jump there to do the work.  */
    1.50 +#ifdef V850E_CACHE_WRITE_IBS
    1.51 +	*r0_ram++ 	= 0xf0720760;	/* st.h r0, 0xfffff072[r0] */
    1.52 +#endif
    1.53 +	*r0_ram++ 	= 0xf06a3760;	/* st.h r6, 0xfffff06a[r0] */
    1.54 +	*r0_ram 	= 0x5640006b;	/* jmp [r11] */
    1.55 +
    1.56 +	asm ("mov hilo(1f), r11; jmp [%1]; 1:;"
    1.57 +	     :: "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
    1.58 +}
    1.59 +
    1.60 +static void clear_icache (void)
    1.61 +{
    1.62 +	/* 1. Read the instruction cache control register (ICC) and confirm
    1.63 +	      that bits 0 and 1 (TCLR0, TCLR1) are all cleared.  */
    1.64 +	WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
    1.65 +
    1.66 +	/* 2. Read the ICC register and confirm that bit 12 (LOCK0) is
    1.67 +  	      cleared.  Bit 13 of the ICC register is always cleared.  */
    1.68 +	WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x1000);
    1.69 +
    1.70 +	/* 3. Set the TCLR0 and TCLR1 bits of the ICC register as follows,
    1.71 +	      when clearing way 0 and way 1 at the same time:
    1.72 +	        (a) Set the TCLR0 and TCLR1 bits.
    1.73 +		(b) Read the TCLR0 and TCLR1 bits to confirm that these bits
    1.74 +		    are cleared.
    1.75 +		(c) Perform (a) and (b) above again.  */
    1.76 +	V850E_CACHE_ICC |= 0x3;
    1.77 +	WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
    1.78 +
    1.79 +#ifdef V850E_CACHE_REPEAT_ICC_WRITE
    1.80 +	/* Do it again.  */
    1.81 +	V850E_CACHE_ICC |= 0x3;
    1.82 +	WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
    1.83 +#endif
    1.84 +}
    1.85 +
    1.86 +#ifdef V850E_CACHE_DCC
    1.87 +/* Flush or clear (or both) the data cache, depending on the value of FLAGS;
    1.88 +   the procedure is the same for both, just the control bits used differ (and
    1.89 +   both may be performed simultaneously).  */
    1.90 +static void dcache_op (unsigned short flags)
    1.91 +{
    1.92 +	/* 1. Read the data cache control register (DCC) and confirm that bits
    1.93 +	      0, 1, 4, and 5 (DC00, DC01, DC04, DC05) are all cleared.  */
    1.94 +	WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & 0x33);
    1.95 +
    1.96 +	/* 2. Clear DCC register bit 12 (DC12), bit 13 (DC13), or both
    1.97 +	      depending on the way for which tags are to be cleared.  */
    1.98 +	V850E_CACHE_DCC &= ~0xC000;
    1.99 +
   1.100 +	/* 3. Set DCC register bit 0 (DC00), bit 1 (DC01) or both depending on
   1.101 +	      the way for which tags are to be cleared.
   1.102 +	      ...
   1.103 +	      Set DCC register bit 4 (DC04), bit 5 (DC05), or both depending
   1.104 +	      on the way to be data flushed.  */
   1.105 +	V850E_CACHE_DCC |= flags;
   1.106 +
   1.107 +	/* 4. Read DCC register bit DC00, DC01 [DC04, DC05], or both depending
   1.108 +	      on the way for which tags were cleared [flushed] and confirm
   1.109 +	      that that bit is cleared.  */
   1.110 +	WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & flags);
   1.111 +}
   1.112 +#endif /* V850E_CACHE_DCC */
   1.113 +
   1.114 +/* Flushes the contents of the dcache to memory.  */
   1.115 +static inline void flush_dcache (void)
   1.116 +{
   1.117 +#ifdef V850E_CACHE_DCC
   1.118 +	/* We only need to do something if in write-back mode.  */
   1.119 +	if (V850E_CACHE_DCC & 0x0400)
   1.120 +		dcache_op (0x30);
   1.121 +#endif /* V850E_CACHE_DCC */
   1.122 +}
   1.123 +
   1.124 +/* Flushes the contents of the dcache to memory, and then clears it.  */
   1.125 +static inline void clear_dcache (void)
   1.126 +{
   1.127 +#ifdef V850E_CACHE_DCC
   1.128 +	/* We only need to do something if the dcache is enabled.  */
   1.129 +	if (V850E_CACHE_DCC & 0x0C00)
   1.130 +		dcache_op (0x33);
   1.131 +#endif /* V850E_CACHE_DCC */
   1.132 +}
   1.133 +
   1.134 +/* Clears the dcache without flushing to memory first.  */
   1.135 +static inline void clear_dcache_no_flush (void)
   1.136 +{
   1.137 +#ifdef V850E_CACHE_DCC
   1.138 +	/* We only need to do something if the dcache is enabled.  */
   1.139 +	if (V850E_CACHE_DCC & 0x0C00)
   1.140 +		dcache_op (0x3);
   1.141 +#endif /* V850E_CACHE_DCC */
   1.142 +}
   1.143 +
   1.144 +static inline void cache_exec_after_store (void)
   1.145 +{
   1.146 +	flush_dcache ();
   1.147 +	clear_icache ();
   1.148 +}
   1.149 +
   1.150 +
   1.151 +/* Exported functions.  */
   1.152 +
   1.153 +void flush_icache (void)
   1.154 +{
   1.155 +	cache_exec_after_store ();
   1.156 +}
   1.157 +
   1.158 +void flush_icache_range (unsigned long start, unsigned long end)
   1.159 +{
   1.160 +	cache_exec_after_store ();
   1.161 +}
   1.162 +
   1.163 +void flush_icache_page (struct vm_area_struct *vma, struct page *page)
   1.164 +{
   1.165 +	cache_exec_after_store ();
   1.166 +}
   1.167 +
   1.168 +void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
   1.169 +			      unsigned long adr, int len)
   1.170 +{
   1.171 +	cache_exec_after_store ();
   1.172 +}
   1.173 +
   1.174 +void flush_cache_sigtramp (unsigned long addr)
   1.175 +{
   1.176 +	cache_exec_after_store ();
   1.177 +}