ia64/linux-2.6.18-xen.hg

diff arch/mips/sgi-ip32/ip32-setup.c @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
parents
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     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/arch/mips/sgi-ip32/ip32-setup.c	Wed Apr 11 14:15:44 2007 +0100
     1.3 @@ -0,0 +1,149 @@
     1.4 +/*
     1.5 + * IP32 basic setup
     1.6 + *
     1.7 + * This file is subject to the terms and conditions of the GNU General Public
     1.8 + * License.  See the file "COPYING" in the main directory of this archive
     1.9 + * for more details.
    1.10 + *
    1.11 + * Copyright (C) 2000 Harald Koerfgen
    1.12 + * Copyright (C) 2002, 2003, 2005 Ilya A. Volynets
    1.13 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
    1.14 + */
    1.15 +#include <linux/console.h>
    1.16 +#include <linux/init.h>
    1.17 +#include <linux/interrupt.h>
    1.18 +#include <linux/mc146818rtc.h>
    1.19 +#include <linux/param.h>
    1.20 +#include <linux/sched.h>
    1.21 +
    1.22 +#include <asm/bootinfo.h>
    1.23 +#include <asm/mc146818-time.h>
    1.24 +#include <asm/mipsregs.h>
    1.25 +#include <asm/mmu_context.h>
    1.26 +#include <asm/sgialib.h>
    1.27 +#include <asm/time.h>
    1.28 +#include <asm/traps.h>
    1.29 +#include <asm/io.h>
    1.30 +#include <asm/ip32/crime.h>
    1.31 +#include <asm/ip32/mace.h>
    1.32 +#include <asm/ip32/ip32_ints.h>
    1.33 +
    1.34 +extern void ip32_be_init(void);
    1.35 +extern void crime_init(void);
    1.36 +
    1.37 +#ifdef CONFIG_SGI_O2MACE_ETH
    1.38 +/*
    1.39 + * This is taken care of in here 'cause they say using Arc later on is
    1.40 + * problematic
    1.41 + */
    1.42 +extern char o2meth_eaddr[8];
    1.43 +static inline unsigned char str2hexnum(unsigned char c)
    1.44 +{
    1.45 +	if (c >= '0' && c <= '9')
    1.46 +		return c - '0';
    1.47 +	if (c >= 'a' && c <= 'f')
    1.48 +		return c - 'a' + 10;
    1.49 +	return 0; /* foo */
    1.50 +}
    1.51 +
    1.52 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
    1.53 +{
    1.54 +	int i;
    1.55 +
    1.56 +	for (i = 0; i < 6; i++) {
    1.57 +		unsigned char num;
    1.58 +
    1.59 +		if(*str == ':')
    1.60 +			str++;
    1.61 +		num = str2hexnum(*str++) << 4;
    1.62 +		num |= (str2hexnum(*str++));
    1.63 +		ea[i] = num;
    1.64 +	}
    1.65 +}
    1.66 +#endif
    1.67 +
    1.68 +#ifdef CONFIG_SERIAL_8250
    1.69 +#include <linux/tty.h>
    1.70 +#include <linux/serial.h>
    1.71 +#include <linux/serial_core.h>
    1.72 +#endif /* CONFIG_SERIAL_8250 */
    1.73 +
    1.74 +/* An arbitrary time; this can be decreased if reliability looks good */
    1.75 +#define WAIT_MS 10
    1.76 +
    1.77 +void __init ip32_time_init(void)
    1.78 +{
    1.79 +	printk(KERN_INFO "Calibrating system timer... ");
    1.80 +	write_c0_count(0);
    1.81 +	crime->timer = 0;
    1.82 +	while (crime->timer < CRIME_MASTER_FREQ * WAIT_MS / 1000) ;
    1.83 +	mips_hpt_frequency = read_c0_count() * 1000 / WAIT_MS;
    1.84 +	printk("%d MHz CPU detected\n", mips_hpt_frequency * 2 / 1000000);
    1.85 +}
    1.86 +
    1.87 +void __init plat_timer_setup(struct irqaction *irq)
    1.88 +{
    1.89 +	irq->handler = no_action;
    1.90 +	setup_irq(IP32_R4K_TIMER_IRQ, irq);
    1.91 +}
    1.92 +
    1.93 +void __init plat_mem_setup(void)
    1.94 +{
    1.95 +	board_be_init = ip32_be_init;
    1.96 +
    1.97 +	rtc_mips_get_time = mc146818_get_cmos_time;
    1.98 +	rtc_mips_set_mmss = mc146818_set_rtc_mmss;
    1.99 +
   1.100 +	board_time_init = ip32_time_init;
   1.101 +
   1.102 +#ifdef CONFIG_SERIAL_8250
   1.103 +	{
   1.104 +		static struct uart_port o2_serial[2];
   1.105 +
   1.106 +		memset(o2_serial, 0, sizeof(o2_serial));
   1.107 +		o2_serial[0].type	= PORT_16550A;
   1.108 +		o2_serial[0].line	= 0;
   1.109 +		o2_serial[0].irq	= MACEISA_SERIAL1_IRQ;
   1.110 +		o2_serial[0].flags	= UPF_SKIP_TEST;
   1.111 +		o2_serial[0].uartclk	= 1843200;
   1.112 +		o2_serial[0].iotype	= UPIO_MEM;
   1.113 +		o2_serial[0].membase	= (char *)&mace->isa.serial1;
   1.114 +		o2_serial[0].fifosize	= 14;
   1.115 +                /* How much to shift register offset by. Each UART register
   1.116 +		 * is replicated over 256 byte space */
   1.117 +		o2_serial[0].regshift	= 8;
   1.118 +		o2_serial[1].type	= PORT_16550A;
   1.119 +		o2_serial[1].line	= 1;
   1.120 +		o2_serial[1].irq	= MACEISA_SERIAL2_IRQ;
   1.121 +		o2_serial[1].flags	= UPF_SKIP_TEST;
   1.122 +		o2_serial[1].uartclk	= 1843200;
   1.123 +		o2_serial[1].iotype	= UPIO_MEM;
   1.124 +		o2_serial[1].membase	= (char *)&mace->isa.serial2;
   1.125 +		o2_serial[1].fifosize	= 14;
   1.126 +		o2_serial[1].regshift	= 8;
   1.127 +
   1.128 +		early_serial_setup(&o2_serial[0]);
   1.129 +		early_serial_setup(&o2_serial[1]);
   1.130 +	}
   1.131 +#endif
   1.132 +#ifdef CONFIG_SGI_O2MACE_ETH
   1.133 +	{
   1.134 +		char *mac = ArcGetEnvironmentVariable("eaddr");
   1.135 +		str2eaddr(o2meth_eaddr, mac);
   1.136 +	}
   1.137 +#endif
   1.138 +
   1.139 +#if defined(CONFIG_SERIAL_CORE_CONSOLE)
   1.140 +	{
   1.141 +		char* con = ArcGetEnvironmentVariable("console");
   1.142 +		if (con && *con == 'd') {
   1.143 +			static char options[8];
   1.144 +			char *baud = ArcGetEnvironmentVariable("dbaud");
   1.145 +			if (baud)
   1.146 +				strcpy(options, baud);
   1.147 +			add_preferred_console("ttyS", *(con + 1) == '2' ? 1 : 0,
   1.148 +					      baud ? options : NULL);
   1.149 +		}
   1.150 +	}
   1.151 +#endif
   1.152 +}