ia64/linux-2.6.18-xen.hg

diff arch/mips/pci/ops-pnx8550.c @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
parents
children
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/arch/mips/pci/ops-pnx8550.c	Wed Apr 11 14:15:44 2007 +0100
     1.3 @@ -0,0 +1,284 @@
     1.4 +/*
     1.5 + *
     1.6 + *  BRIEF MODULE DESCRIPTION
     1.7 + *
     1.8 + *  2.6 port, Embedded Alley Solutions, Inc
     1.9 + *
    1.10 + *  Based on:
    1.11 + *  Author: source@mvista.com
    1.12 + *
    1.13 + *  This program is free software; you can distribute it and/or modify it
    1.14 + *  under the terms of the GNU General Public License (Version 2) as
    1.15 + *  published by the Free Software Foundation.
    1.16 + *
    1.17 + *  This program is distributed in the hope it will be useful, but WITHOUT
    1.18 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    1.19 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    1.20 + *  for more details.
    1.21 + *
    1.22 + *  You should have received a copy of the GNU General Public License along
    1.23 + *  with this program; if not, write to the Free Software Foundation, Inc.,
    1.24 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
    1.25 + */
    1.26 +#include <linux/types.h>
    1.27 +#include <linux/pci.h>
    1.28 +#include <linux/kernel.h>
    1.29 +#include <linux/init.h>
    1.30 +#include <linux/vmalloc.h>
    1.31 +#include <linux/delay.h>
    1.32 +
    1.33 +#include <asm/mach-pnx8550/pci.h>
    1.34 +#include <asm/mach-pnx8550/glb.h>
    1.35 +#include <asm/debug.h>
    1.36 +
    1.37 +
    1.38 +static inline void clear_status(void)
    1.39 +{
    1.40 +	unsigned long pci_stat;
    1.41 +
    1.42 +	pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS);
    1.43 +	outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR);
    1.44 +}
    1.45 +
    1.46 +static inline unsigned int
    1.47 +calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where)
    1.48 +{
    1.49 +	unsigned int addr;
    1.50 +
    1.51 +	addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0);
    1.52 +	addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc);
    1.53 +
    1.54 +	return addr;
    1.55 +}
    1.56 +
    1.57 +static int
    1.58 +config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val)
    1.59 +{
    1.60 +	unsigned int flags;
    1.61 +	unsigned long loops = 0;
    1.62 +	unsigned long ioaddr = calc_cfg_addr(bus, devfn, where);
    1.63 +
    1.64 +	local_irq_save(flags);
    1.65 +	/*Clear pending interrupt status */
    1.66 +	if (inl(PCI_BASE | PCI_GPPM_STATUS)) {
    1.67 +		clear_status();
    1.68 +		while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ;
    1.69 +	}
    1.70 +
    1.71 +	outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR);
    1.72 +
    1.73 +	if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE))
    1.74 +		outl(*val, PCI_BASE | PCI_GPPM_WDAT);
    1.75 +
    1.76 +	outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK),
    1.77 +	     PCI_BASE | PCI_GPPM_CTRL);
    1.78 +
    1.79 +	loops =
    1.80 +	    ((loops_per_jiffy *
    1.81 +	      PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT));
    1.82 +	while (1) {
    1.83 +		if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) {
    1.84 +			if ((pci_cmd == PCI_CMD_IOR) ||
    1.85 +			    (pci_cmd == PCI_CMD_CONFIG_READ))
    1.86 +				*val = inl(PCI_BASE | PCI_GPPM_RDAT);
    1.87 +			clear_status();
    1.88 +			local_irq_restore(flags);
    1.89 +			return PCIBIOS_SUCCESSFUL;
    1.90 +		} else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) {
    1.91 +			break;
    1.92 +		}
    1.93 +
    1.94 +		loops--;
    1.95 +		if (loops == 0) {
    1.96 +			printk("%s : Arbiter Locked.\n", __FUNCTION__);
    1.97 +		}
    1.98 +	}
    1.99 +
   1.100 +	clear_status();
   1.101 +	if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) {
   1.102 +		printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n",
   1.103 +		       __FUNCTION__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr,
   1.104 +		       pci_cmd);
   1.105 +	}
   1.106 +
   1.107 +	if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ))
   1.108 +		*val = 0xffffffff;
   1.109 +	local_irq_restore(flags);
   1.110 +	return PCIBIOS_DEVICE_NOT_FOUND;
   1.111 +}
   1.112 +
   1.113 +/*
   1.114 + * We can't address 8 and 16 bit words directly.  Instead we have to
   1.115 + * read/write a 32bit word and mask/modify the data we actually want.
   1.116 + */
   1.117 +static int
   1.118 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
   1.119 +{
   1.120 +	unsigned int data = 0;
   1.121 +	int err;
   1.122 +
   1.123 +	if (bus == 0)
   1.124 +		return -1;
   1.125 +
   1.126 +	err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
   1.127 +	switch (where & 0x03) {
   1.128 +	case 0:
   1.129 +		*val = (unsigned char)(data & 0x000000ff);
   1.130 +		break;
   1.131 +	case 1:
   1.132 +		*val = (unsigned char)((data & 0x0000ff00) >> 8);
   1.133 +		break;
   1.134 +	case 2:
   1.135 +		*val = (unsigned char)((data & 0x00ff0000) >> 16);
   1.136 +		break;
   1.137 +	case 3:
   1.138 +		*val = (unsigned char)((data & 0xff000000) >> 24);
   1.139 +		break;
   1.140 +	}
   1.141 +
   1.142 +	return err;
   1.143 +}
   1.144 +
   1.145 +static int
   1.146 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
   1.147 +{
   1.148 +	unsigned int data = 0;
   1.149 +	int err;
   1.150 +
   1.151 +	if (bus == 0)
   1.152 +		return -1;
   1.153 +
   1.154 +	if (where & 0x01)
   1.155 +		return PCIBIOS_BAD_REGISTER_NUMBER;
   1.156 +
   1.157 +	err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data);
   1.158 +	switch (where & 0x02) {
   1.159 +	case 0:
   1.160 +		*val = (unsigned short)(data & 0x0000ffff);
   1.161 +		break;
   1.162 +	case 2:
   1.163 +		*val = (unsigned short)((data & 0xffff0000) >> 16);
   1.164 +		break;
   1.165 +	}
   1.166 +
   1.167 +	return err;
   1.168 +}
   1.169 +
   1.170 +static int
   1.171 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
   1.172 +{
   1.173 +	int err;
   1.174 +	if (bus == 0)
   1.175 +		return -1;
   1.176 +
   1.177 +	if (where & 0x03)
   1.178 +		return PCIBIOS_BAD_REGISTER_NUMBER;
   1.179 +
   1.180 +	err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val);
   1.181 +
   1.182 +	return err;
   1.183 +}
   1.184 +
   1.185 +static int
   1.186 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
   1.187 +{
   1.188 +	unsigned int data = (unsigned int)val;
   1.189 +	int err;
   1.190 +
   1.191 +	if (bus == 0)
   1.192 +		return -1;
   1.193 +
   1.194 +	switch (where & 0x03) {
   1.195 +	case 1:
   1.196 +		data = (data << 8);
   1.197 +		break;
   1.198 +	case 2:
   1.199 +		data = (data << 16);
   1.200 +		break;
   1.201 +	case 3:
   1.202 +		data = (data << 24);
   1.203 +		break;
   1.204 +	default:
   1.205 +		break;
   1.206 +	}
   1.207 +
   1.208 +	err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
   1.209 +
   1.210 +	return err;
   1.211 +}
   1.212 +
   1.213 +static int
   1.214 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
   1.215 +{
   1.216 +	unsigned int data = (unsigned int)val;
   1.217 +	int err;
   1.218 +
   1.219 +	if (bus == 0)
   1.220 +		return -1;
   1.221 +
   1.222 +	if (where & 0x01)
   1.223 +		return PCIBIOS_BAD_REGISTER_NUMBER;
   1.224 +
   1.225 +	switch (where & 0x02) {
   1.226 +	case 2:
   1.227 +		data = (data << 16);
   1.228 +		break;
   1.229 +	default:
   1.230 +		break;
   1.231 +	}
   1.232 +	err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data);
   1.233 +
   1.234 +	return err;
   1.235 +}
   1.236 +
   1.237 +static int
   1.238 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
   1.239 +{
   1.240 +	int err;
   1.241 +	if (bus == 0)
   1.242 +		return -1;
   1.243 +
   1.244 +	if (where & 0x03)
   1.245 +		return PCIBIOS_BAD_REGISTER_NUMBER;
   1.246 +
   1.247 +	err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val);
   1.248 +
   1.249 +	return err;
   1.250 +}
   1.251 +
   1.252 +static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
   1.253 +{
   1.254 +	switch (size) {
   1.255 +	case 1: {
   1.256 +			u8 _val;
   1.257 +			int rc = read_config_byte(bus, devfn, where, &_val);
   1.258 +			*val = _val;
   1.259 +			return rc;
   1.260 +		}
   1.261 +       case 2: {
   1.262 +			u16 _val;
   1.263 +			int rc = read_config_word(bus, devfn, where, &_val);
   1.264 +			*val = _val;
   1.265 +			return rc;
   1.266 +		}
   1.267 +	default:
   1.268 +		return read_config_dword(bus, devfn, where, val);
   1.269 +	}
   1.270 +}
   1.271 +
   1.272 +static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
   1.273 +{
   1.274 +	switch (size) {
   1.275 +	case 1:
   1.276 +		return write_config_byte(bus, devfn, where, (u8) val);
   1.277 +	case 2:
   1.278 +		return write_config_word(bus, devfn, where, (u16) val);
   1.279 +	default:
   1.280 +		return write_config_dword(bus, devfn, where, val);
   1.281 +	}
   1.282 +}
   1.283 +
   1.284 +struct pci_ops pnx8550_pci_ops = {
   1.285 +	config_read,
   1.286 +	config_write
   1.287 +};