ia64/linux-2.6.18-xen.hg

annotate drivers/serial/sunsab.h @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
rev   line source
ian@0 1 /* sunsab.h: Register Definitions for the Siemens SAB82532 DUSCC
ian@0 2 *
ian@0 3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
ian@0 4 */
ian@0 5
ian@0 6 #ifndef _SUNSAB_H
ian@0 7 #define _SUNSAB_H
ian@0 8
ian@0 9 struct sab82532_async_rd_regs {
ian@0 10 u8 rfifo[0x20]; /* Receive FIFO */
ian@0 11 u8 star; /* Status Register */
ian@0 12 u8 __pad1;
ian@0 13 u8 mode; /* Mode Register */
ian@0 14 u8 timr; /* Timer Register */
ian@0 15 u8 xon; /* XON Character */
ian@0 16 u8 xoff; /* XOFF Character */
ian@0 17 u8 tcr; /* Termination Character Register */
ian@0 18 u8 dafo; /* Data Format */
ian@0 19 u8 rfc; /* RFIFO Control Register */
ian@0 20 u8 __pad2;
ian@0 21 u8 rbcl; /* Receive Byte Count Low */
ian@0 22 u8 rbch; /* Receive Byte Count High */
ian@0 23 u8 ccr0; /* Channel Configuration Register 0 */
ian@0 24 u8 ccr1; /* Channel Configuration Register 1 */
ian@0 25 u8 ccr2; /* Channel Configuration Register 2 */
ian@0 26 u8 ccr3; /* Channel Configuration Register 3 */
ian@0 27 u8 __pad3[4];
ian@0 28 u8 vstr; /* Version Status Register */
ian@0 29 u8 __pad4[3];
ian@0 30 u8 gis; /* Global Interrupt Status */
ian@0 31 u8 ipc; /* Interrupt Port Configuration */
ian@0 32 u8 isr0; /* Interrupt Status 0 */
ian@0 33 u8 isr1; /* Interrupt Status 1 */
ian@0 34 u8 pvr; /* Port Value Register */
ian@0 35 u8 pis; /* Port Interrupt Status */
ian@0 36 u8 pcr; /* Port Configuration Register */
ian@0 37 u8 ccr4; /* Channel Configuration Register 4 */
ian@0 38 };
ian@0 39
ian@0 40 struct sab82532_async_wr_regs {
ian@0 41 u8 xfifo[0x20]; /* Transmit FIFO */
ian@0 42 u8 cmdr; /* Command Register */
ian@0 43 u8 __pad1;
ian@0 44 u8 mode;
ian@0 45 u8 timr;
ian@0 46 u8 xon;
ian@0 47 u8 xoff;
ian@0 48 u8 tcr;
ian@0 49 u8 dafo;
ian@0 50 u8 rfc;
ian@0 51 u8 __pad2;
ian@0 52 u8 xbcl; /* Transmit Byte Count Low */
ian@0 53 u8 xbch; /* Transmit Byte Count High */
ian@0 54 u8 ccr0;
ian@0 55 u8 ccr1;
ian@0 56 u8 ccr2;
ian@0 57 u8 ccr3;
ian@0 58 u8 tsax; /* Time-Slot Assignment Reg. Transmit */
ian@0 59 u8 tsar; /* Time-Slot Assignment Reg. Receive */
ian@0 60 u8 xccr; /* Transmit Channel Capacity Register */
ian@0 61 u8 rccr; /* Receive Channel Capacity Register */
ian@0 62 u8 bgr; /* Baud Rate Generator Register */
ian@0 63 u8 tic; /* Transmit Immediate Character */
ian@0 64 u8 mxn; /* Mask XON Character */
ian@0 65 u8 mxf; /* Mask XOFF Character */
ian@0 66 u8 iva; /* Interrupt Vector Address */
ian@0 67 u8 ipc;
ian@0 68 u8 imr0; /* Interrupt Mask Register 0 */
ian@0 69 u8 imr1; /* Interrupt Mask Register 1 */
ian@0 70 u8 pvr;
ian@0 71 u8 pim; /* Port Interrupt Mask */
ian@0 72 u8 pcr;
ian@0 73 u8 ccr4;
ian@0 74 };
ian@0 75
ian@0 76 struct sab82532_async_rw_regs { /* Read/Write registers */
ian@0 77 u8 __pad1[0x20];
ian@0 78 u8 __pad2;
ian@0 79 u8 __pad3;
ian@0 80 u8 mode;
ian@0 81 u8 timr;
ian@0 82 u8 xon;
ian@0 83 u8 xoff;
ian@0 84 u8 tcr;
ian@0 85 u8 dafo;
ian@0 86 u8 rfc;
ian@0 87 u8 __pad4;
ian@0 88 u8 __pad5;
ian@0 89 u8 __pad6;
ian@0 90 u8 ccr0;
ian@0 91 u8 ccr1;
ian@0 92 u8 ccr2;
ian@0 93 u8 ccr3;
ian@0 94 u8 __pad7;
ian@0 95 u8 __pad8;
ian@0 96 u8 __pad9;
ian@0 97 u8 __pad10;
ian@0 98 u8 __pad11;
ian@0 99 u8 __pad12;
ian@0 100 u8 __pad13;
ian@0 101 u8 __pad14;
ian@0 102 u8 __pad15;
ian@0 103 u8 ipc;
ian@0 104 u8 __pad16;
ian@0 105 u8 __pad17;
ian@0 106 u8 pvr;
ian@0 107 u8 __pad18;
ian@0 108 u8 pcr;
ian@0 109 u8 ccr4;
ian@0 110 };
ian@0 111
ian@0 112 union sab82532_async_regs {
ian@0 113 __volatile__ struct sab82532_async_rd_regs r;
ian@0 114 __volatile__ struct sab82532_async_wr_regs w;
ian@0 115 __volatile__ struct sab82532_async_rw_regs rw;
ian@0 116 };
ian@0 117
ian@0 118 union sab82532_irq_status {
ian@0 119 unsigned short stat;
ian@0 120 struct {
ian@0 121 unsigned char isr0;
ian@0 122 unsigned char isr1;
ian@0 123 } sreg;
ian@0 124 };
ian@0 125
ian@0 126 /* irqflags bits */
ian@0 127 #define SAB82532_ALLS 0x00000001
ian@0 128 #define SAB82532_XPR 0x00000002
ian@0 129 #define SAB82532_REGS_PENDING 0x00000004
ian@0 130
ian@0 131 /* RFIFO Status Byte */
ian@0 132 #define SAB82532_RSTAT_PE 0x80
ian@0 133 #define SAB82532_RSTAT_FE 0x40
ian@0 134 #define SAB82532_RSTAT_PARITY 0x01
ian@0 135
ian@0 136 /* Status Register (STAR) */
ian@0 137 #define SAB82532_STAR_XDOV 0x80
ian@0 138 #define SAB82532_STAR_XFW 0x40
ian@0 139 #define SAB82532_STAR_RFNE 0x20
ian@0 140 #define SAB82532_STAR_FCS 0x10
ian@0 141 #define SAB82532_STAR_TEC 0x08
ian@0 142 #define SAB82532_STAR_CEC 0x04
ian@0 143 #define SAB82532_STAR_CTS 0x02
ian@0 144
ian@0 145 /* Command Register (CMDR) */
ian@0 146 #define SAB82532_CMDR_RMC 0x80
ian@0 147 #define SAB82532_CMDR_RRES 0x40
ian@0 148 #define SAB82532_CMDR_RFRD 0x20
ian@0 149 #define SAB82532_CMDR_STI 0x10
ian@0 150 #define SAB82532_CMDR_XF 0x08
ian@0 151 #define SAB82532_CMDR_XRES 0x01
ian@0 152
ian@0 153 /* Mode Register (MODE) */
ian@0 154 #define SAB82532_MODE_FRTS 0x40
ian@0 155 #define SAB82532_MODE_FCTS 0x20
ian@0 156 #define SAB82532_MODE_FLON 0x10
ian@0 157 #define SAB82532_MODE_RAC 0x08
ian@0 158 #define SAB82532_MODE_RTS 0x04
ian@0 159 #define SAB82532_MODE_TRS 0x02
ian@0 160 #define SAB82532_MODE_TLP 0x01
ian@0 161
ian@0 162 /* Timer Register (TIMR) */
ian@0 163 #define SAB82532_TIMR_CNT_MASK 0xe0
ian@0 164 #define SAB82532_TIMR_VALUE_MASK 0x1f
ian@0 165
ian@0 166 /* Data Format (DAFO) */
ian@0 167 #define SAB82532_DAFO_XBRK 0x40
ian@0 168 #define SAB82532_DAFO_STOP 0x20
ian@0 169 #define SAB82532_DAFO_PAR_SPACE 0x00
ian@0 170 #define SAB82532_DAFO_PAR_ODD 0x08
ian@0 171 #define SAB82532_DAFO_PAR_EVEN 0x10
ian@0 172 #define SAB82532_DAFO_PAR_MARK 0x18
ian@0 173 #define SAB82532_DAFO_PARE 0x04
ian@0 174 #define SAB82532_DAFO_CHL8 0x00
ian@0 175 #define SAB82532_DAFO_CHL7 0x01
ian@0 176 #define SAB82532_DAFO_CHL6 0x02
ian@0 177 #define SAB82532_DAFO_CHL5 0x03
ian@0 178
ian@0 179 /* RFIFO Control Register (RFC) */
ian@0 180 #define SAB82532_RFC_DPS 0x40
ian@0 181 #define SAB82532_RFC_DXS 0x20
ian@0 182 #define SAB82532_RFC_RFDF 0x10
ian@0 183 #define SAB82532_RFC_RFTH_1 0x00
ian@0 184 #define SAB82532_RFC_RFTH_4 0x04
ian@0 185 #define SAB82532_RFC_RFTH_16 0x08
ian@0 186 #define SAB82532_RFC_RFTH_32 0x0c
ian@0 187 #define SAB82532_RFC_TCDE 0x01
ian@0 188
ian@0 189 /* Received Byte Count High (RBCH) */
ian@0 190 #define SAB82532_RBCH_DMA 0x80
ian@0 191 #define SAB82532_RBCH_CAS 0x20
ian@0 192
ian@0 193 /* Transmit Byte Count High (XBCH) */
ian@0 194 #define SAB82532_XBCH_DMA 0x80
ian@0 195 #define SAB82532_XBCH_CAS 0x20
ian@0 196 #define SAB82532_XBCH_XC 0x10
ian@0 197
ian@0 198 /* Channel Configuration Register 0 (CCR0) */
ian@0 199 #define SAB82532_CCR0_PU 0x80
ian@0 200 #define SAB82532_CCR0_MCE 0x40
ian@0 201 #define SAB82532_CCR0_SC_NRZ 0x00
ian@0 202 #define SAB82532_CCR0_SC_NRZI 0x08
ian@0 203 #define SAB82532_CCR0_SC_FM0 0x10
ian@0 204 #define SAB82532_CCR0_SC_FM1 0x14
ian@0 205 #define SAB82532_CCR0_SC_MANCH 0x18
ian@0 206 #define SAB82532_CCR0_SM_HDLC 0x00
ian@0 207 #define SAB82532_CCR0_SM_SDLC_LOOP 0x01
ian@0 208 #define SAB82532_CCR0_SM_BISYNC 0x02
ian@0 209 #define SAB82532_CCR0_SM_ASYNC 0x03
ian@0 210
ian@0 211 /* Channel Configuration Register 1 (CCR1) */
ian@0 212 #define SAB82532_CCR1_ODS 0x10
ian@0 213 #define SAB82532_CCR1_BCR 0x08
ian@0 214 #define SAB82532_CCR1_CM_MASK 0x07
ian@0 215
ian@0 216 /* Channel Configuration Register 2 (CCR2) */
ian@0 217 #define SAB82532_CCR2_SOC1 0x80
ian@0 218 #define SAB82532_CCR2_SOC0 0x40
ian@0 219 #define SAB82532_CCR2_BR9 0x80
ian@0 220 #define SAB82532_CCR2_BR8 0x40
ian@0 221 #define SAB82532_CCR2_BDF 0x20
ian@0 222 #define SAB82532_CCR2_SSEL 0x10
ian@0 223 #define SAB82532_CCR2_XCS0 0x20
ian@0 224 #define SAB82532_CCR2_RCS0 0x10
ian@0 225 #define SAB82532_CCR2_TOE 0x08
ian@0 226 #define SAB82532_CCR2_RWX 0x04
ian@0 227 #define SAB82532_CCR2_DIV 0x01
ian@0 228
ian@0 229 /* Channel Configuration Register 3 (CCR3) */
ian@0 230 #define SAB82532_CCR3_PSD 0x01
ian@0 231
ian@0 232 /* Time Slot Assignment Register Transmit (TSAX) */
ian@0 233 #define SAB82532_TSAX_TSNX_MASK 0xfc
ian@0 234 #define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */
ian@0 235 #define SAB82532_TSAX_XCS1 0x01
ian@0 236
ian@0 237 /* Time Slot Assignment Register Receive (TSAR) */
ian@0 238 #define SAB82532_TSAR_TSNR_MASK 0xfc
ian@0 239 #define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */
ian@0 240 #define SAB82532_TSAR_RCS1 0x01
ian@0 241
ian@0 242 /* Version Status Register (VSTR) */
ian@0 243 #define SAB82532_VSTR_CD 0x80
ian@0 244 #define SAB82532_VSTR_DPLA 0x40
ian@0 245 #define SAB82532_VSTR_VN_MASK 0x0f
ian@0 246 #define SAB82532_VSTR_VN_1 0x00
ian@0 247 #define SAB82532_VSTR_VN_2 0x01
ian@0 248 #define SAB82532_VSTR_VN_3_2 0x02
ian@0 249
ian@0 250 /* Global Interrupt Status Register (GIS) */
ian@0 251 #define SAB82532_GIS_PI 0x80
ian@0 252 #define SAB82532_GIS_ISA1 0x08
ian@0 253 #define SAB82532_GIS_ISA0 0x04
ian@0 254 #define SAB82532_GIS_ISB1 0x02
ian@0 255 #define SAB82532_GIS_ISB0 0x01
ian@0 256
ian@0 257 /* Interrupt Vector Address (IVA) */
ian@0 258 #define SAB82532_IVA_MASK 0xf1
ian@0 259
ian@0 260 /* Interrupt Port Configuration (IPC) */
ian@0 261 #define SAB82532_IPC_VIS 0x80
ian@0 262 #define SAB82532_IPC_SLA1 0x10
ian@0 263 #define SAB82532_IPC_SLA0 0x08
ian@0 264 #define SAB82532_IPC_CASM 0x04
ian@0 265 #define SAB82532_IPC_IC_OPEN_DRAIN 0x00
ian@0 266 #define SAB82532_IPC_IC_ACT_LOW 0x01
ian@0 267 #define SAB82532_IPC_IC_ACT_HIGH 0x03
ian@0 268
ian@0 269 /* Interrupt Status Register 0 (ISR0) */
ian@0 270 #define SAB82532_ISR0_TCD 0x80
ian@0 271 #define SAB82532_ISR0_TIME 0x40
ian@0 272 #define SAB82532_ISR0_PERR 0x20
ian@0 273 #define SAB82532_ISR0_FERR 0x10
ian@0 274 #define SAB82532_ISR0_PLLA 0x08
ian@0 275 #define SAB82532_ISR0_CDSC 0x04
ian@0 276 #define SAB82532_ISR0_RFO 0x02
ian@0 277 #define SAB82532_ISR0_RPF 0x01
ian@0 278
ian@0 279 /* Interrupt Status Register 1 (ISR1) */
ian@0 280 #define SAB82532_ISR1_BRK 0x80
ian@0 281 #define SAB82532_ISR1_BRKT 0x40
ian@0 282 #define SAB82532_ISR1_ALLS 0x20
ian@0 283 #define SAB82532_ISR1_XOFF 0x10
ian@0 284 #define SAB82532_ISR1_TIN 0x08
ian@0 285 #define SAB82532_ISR1_CSC 0x04
ian@0 286 #define SAB82532_ISR1_XON 0x02
ian@0 287 #define SAB82532_ISR1_XPR 0x01
ian@0 288
ian@0 289 /* Interrupt Mask Register 0 (IMR0) */
ian@0 290 #define SAB82532_IMR0_TCD 0x80
ian@0 291 #define SAB82532_IMR0_TIME 0x40
ian@0 292 #define SAB82532_IMR0_PERR 0x20
ian@0 293 #define SAB82532_IMR0_FERR 0x10
ian@0 294 #define SAB82532_IMR0_PLLA 0x08
ian@0 295 #define SAB82532_IMR0_CDSC 0x04
ian@0 296 #define SAB82532_IMR0_RFO 0x02
ian@0 297 #define SAB82532_IMR0_RPF 0x01
ian@0 298
ian@0 299 /* Interrupt Mask Register 1 (IMR1) */
ian@0 300 #define SAB82532_IMR1_BRK 0x80
ian@0 301 #define SAB82532_IMR1_BRKT 0x40
ian@0 302 #define SAB82532_IMR1_ALLS 0x20
ian@0 303 #define SAB82532_IMR1_XOFF 0x10
ian@0 304 #define SAB82532_IMR1_TIN 0x08
ian@0 305 #define SAB82532_IMR1_CSC 0x04
ian@0 306 #define SAB82532_IMR1_XON 0x02
ian@0 307 #define SAB82532_IMR1_XPR 0x01
ian@0 308
ian@0 309 /* Port Interrupt Status Register (PIS) */
ian@0 310 #define SAB82532_PIS_SYNC_B 0x08
ian@0 311 #define SAB82532_PIS_DTR_B 0x04
ian@0 312 #define SAB82532_PIS_DTR_A 0x02
ian@0 313 #define SAB82532_PIS_SYNC_A 0x01
ian@0 314
ian@0 315 /* Channel Configuration Register 4 (CCR4) */
ian@0 316 #define SAB82532_CCR4_MCK4 0x80
ian@0 317 #define SAB82532_CCR4_EBRG 0x40
ian@0 318 #define SAB82532_CCR4_TST1 0x20
ian@0 319 #define SAB82532_CCR4_ICD 0x10
ian@0 320
ian@0 321
ian@0 322 #endif /* !(_SUNSAB_H) */