ia64/linux-2.6.18-xen.hg

annotate drivers/serial/8250_pci.c @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * linux/drivers/char/8250_pci.c
ian@0 3 *
ian@0 4 * Probe module for 8250/16550-type PCI serial ports.
ian@0 5 *
ian@0 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
ian@0 7 *
ian@0 8 * Copyright (C) 2001 Russell King, All Rights Reserved.
ian@0 9 *
ian@0 10 * This program is free software; you can redistribute it and/or modify
ian@0 11 * it under the terms of the GNU General Public License as published by
ian@0 12 * the Free Software Foundation; either version 2 of the License.
ian@0 13 *
ian@0 14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
ian@0 15 */
ian@0 16 #include <linux/module.h>
ian@0 17 #include <linux/init.h>
ian@0 18 #include <linux/pci.h>
ian@0 19 #include <linux/sched.h>
ian@0 20 #include <linux/string.h>
ian@0 21 #include <linux/kernel.h>
ian@0 22 #include <linux/slab.h>
ian@0 23 #include <linux/delay.h>
ian@0 24 #include <linux/tty.h>
ian@0 25 #include <linux/serial_core.h>
ian@0 26 #include <linux/8250_pci.h>
ian@0 27 #include <linux/bitops.h>
ian@0 28
ian@0 29 #include <asm/byteorder.h>
ian@0 30 #include <asm/io.h>
ian@0 31
ian@0 32 #include "8250.h"
ian@0 33
ian@0 34 #undef SERIAL_DEBUG_PCI
ian@0 35
ian@0 36 /*
ian@0 37 * init function returns:
ian@0 38 * > 0 - number of ports
ian@0 39 * = 0 - use board->num_ports
ian@0 40 * < 0 - error
ian@0 41 */
ian@0 42 struct pci_serial_quirk {
ian@0 43 u32 vendor;
ian@0 44 u32 device;
ian@0 45 u32 subvendor;
ian@0 46 u32 subdevice;
ian@0 47 int (*init)(struct pci_dev *dev);
ian@0 48 int (*setup)(struct serial_private *, struct pciserial_board *,
ian@0 49 struct uart_port *, int);
ian@0 50 void (*exit)(struct pci_dev *dev);
ian@0 51 };
ian@0 52
ian@0 53 #define PCI_NUM_BAR_RESOURCES 6
ian@0 54
ian@0 55 struct serial_private {
ian@0 56 struct pci_dev *dev;
ian@0 57 unsigned int nr;
ian@0 58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
ian@0 59 struct pci_serial_quirk *quirk;
ian@0 60 int line[0];
ian@0 61 };
ian@0 62
ian@0 63 static void moan_device(const char *str, struct pci_dev *dev)
ian@0 64 {
ian@0 65 printk(KERN_WARNING "%s: %s\n"
ian@0 66 KERN_WARNING "Please send the output of lspci -vv, this\n"
ian@0 67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
ian@0 68 KERN_WARNING "manufacturer and name of serial board or\n"
ian@0 69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
ian@0 70 pci_name(dev), str, dev->vendor, dev->device,
ian@0 71 dev->subsystem_vendor, dev->subsystem_device);
ian@0 72 }
ian@0 73
ian@0 74 static int
ian@0 75 setup_port(struct serial_private *priv, struct uart_port *port,
ian@0 76 int bar, int offset, int regshift)
ian@0 77 {
ian@0 78 struct pci_dev *dev = priv->dev;
ian@0 79 unsigned long base, len;
ian@0 80
ian@0 81 if (bar >= PCI_NUM_BAR_RESOURCES)
ian@0 82 return -EINVAL;
ian@0 83
ian@0 84 base = pci_resource_start(dev, bar);
ian@0 85
ian@0 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
ian@0 87 len = pci_resource_len(dev, bar);
ian@0 88
ian@0 89 if (!priv->remapped_bar[bar])
ian@0 90 priv->remapped_bar[bar] = ioremap(base, len);
ian@0 91 if (!priv->remapped_bar[bar])
ian@0 92 return -ENOMEM;
ian@0 93
ian@0 94 port->iotype = UPIO_MEM;
ian@0 95 port->iobase = 0;
ian@0 96 port->mapbase = base + offset;
ian@0 97 port->membase = priv->remapped_bar[bar] + offset;
ian@0 98 port->regshift = regshift;
ian@0 99 } else {
ian@0 100 port->iotype = UPIO_PORT;
ian@0 101 port->iobase = base + offset;
ian@0 102 port->mapbase = 0;
ian@0 103 port->membase = NULL;
ian@0 104 port->regshift = 0;
ian@0 105 }
ian@0 106 return 0;
ian@0 107 }
ian@0 108
ian@0 109 /*
ian@0 110 * AFAVLAB uses a different mixture of BARs and offsets
ian@0 111 * Not that ugly ;) -- HW
ian@0 112 */
ian@0 113 static int
ian@0 114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
ian@0 115 struct uart_port *port, int idx)
ian@0 116 {
ian@0 117 unsigned int bar, offset = board->first_offset;
ian@0 118
ian@0 119 bar = FL_GET_BASE(board->flags);
ian@0 120 if (idx < 4)
ian@0 121 bar += idx;
ian@0 122 else {
ian@0 123 bar = 4;
ian@0 124 offset += (idx - 4) * board->uart_offset;
ian@0 125 }
ian@0 126
ian@0 127 return setup_port(priv, port, bar, offset, board->reg_shift);
ian@0 128 }
ian@0 129
ian@0 130 /*
ian@0 131 * HP's Remote Management Console. The Diva chip came in several
ian@0 132 * different versions. N-class, L2000 and A500 have two Diva chips, each
ian@0 133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
ian@0 134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
ian@0 135 * one Diva chip, but it has been expanded to 5 UARTs.
ian@0 136 */
ian@0 137 static int pci_hp_diva_init(struct pci_dev *dev)
ian@0 138 {
ian@0 139 int rc = 0;
ian@0 140
ian@0 141 switch (dev->subsystem_device) {
ian@0 142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
ian@0 143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
ian@0 144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
ian@0 145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
ian@0 146 rc = 3;
ian@0 147 break;
ian@0 148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
ian@0 149 rc = 2;
ian@0 150 break;
ian@0 151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
ian@0 152 rc = 4;
ian@0 153 break;
ian@0 154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
ian@0 155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
ian@0 156 rc = 1;
ian@0 157 break;
ian@0 158 }
ian@0 159
ian@0 160 return rc;
ian@0 161 }
ian@0 162
ian@0 163 /*
ian@0 164 * HP's Diva chip puts the 4th/5th serial port further out, and
ian@0 165 * some serial ports are supposed to be hidden on certain models.
ian@0 166 */
ian@0 167 static int
ian@0 168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
ian@0 169 struct uart_port *port, int idx)
ian@0 170 {
ian@0 171 unsigned int offset = board->first_offset;
ian@0 172 unsigned int bar = FL_GET_BASE(board->flags);
ian@0 173
ian@0 174 switch (priv->dev->subsystem_device) {
ian@0 175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
ian@0 176 if (idx == 3)
ian@0 177 idx++;
ian@0 178 break;
ian@0 179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
ian@0 180 if (idx > 0)
ian@0 181 idx++;
ian@0 182 if (idx > 2)
ian@0 183 idx++;
ian@0 184 break;
ian@0 185 }
ian@0 186 if (idx > 2)
ian@0 187 offset = 0x18;
ian@0 188
ian@0 189 offset += idx * board->uart_offset;
ian@0 190
ian@0 191 return setup_port(priv, port, bar, offset, board->reg_shift);
ian@0 192 }
ian@0 193
ian@0 194 /*
ian@0 195 * Added for EKF Intel i960 serial boards
ian@0 196 */
ian@0 197 static int pci_inteli960ni_init(struct pci_dev *dev)
ian@0 198 {
ian@0 199 unsigned long oldval;
ian@0 200
ian@0 201 if (!(dev->subsystem_device & 0x1000))
ian@0 202 return -ENODEV;
ian@0 203
ian@0 204 /* is firmware started? */
ian@0 205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
ian@0 206 if (oldval == 0x00001000L) { /* RESET value */
ian@0 207 printk(KERN_DEBUG "Local i960 firmware missing");
ian@0 208 return -ENODEV;
ian@0 209 }
ian@0 210 return 0;
ian@0 211 }
ian@0 212
ian@0 213 /*
ian@0 214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
ian@0 215 * that the card interrupt be explicitly enabled or disabled. This
ian@0 216 * seems to be mainly needed on card using the PLX which also use I/O
ian@0 217 * mapped memory.
ian@0 218 */
ian@0 219 static int pci_plx9050_init(struct pci_dev *dev)
ian@0 220 {
ian@0 221 u8 irq_config;
ian@0 222 void __iomem *p;
ian@0 223
ian@0 224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
ian@0 225 moan_device("no memory in bar 0", dev);
ian@0 226 return 0;
ian@0 227 }
ian@0 228
ian@0 229 irq_config = 0x41;
ian@0 230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
ian@0 231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
ian@0 232 irq_config = 0x43;
ian@0 233 }
ian@0 234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
ian@0 235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
ian@0 236 /*
ian@0 237 * As the megawolf cards have the int pins active
ian@0 238 * high, and have 2 UART chips, both ints must be
ian@0 239 * enabled on the 9050. Also, the UARTS are set in
ian@0 240 * 16450 mode by default, so we have to enable the
ian@0 241 * 16C950 'enhanced' mode so that we can use the
ian@0 242 * deep FIFOs
ian@0 243 */
ian@0 244 irq_config = 0x5b;
ian@0 245 }
ian@0 246
ian@0 247 /*
ian@0 248 * enable/disable interrupts
ian@0 249 */
ian@0 250 p = ioremap(pci_resource_start(dev, 0), 0x80);
ian@0 251 if (p == NULL)
ian@0 252 return -ENOMEM;
ian@0 253 writel(irq_config, p + 0x4c);
ian@0 254
ian@0 255 /*
ian@0 256 * Read the register back to ensure that it took effect.
ian@0 257 */
ian@0 258 readl(p + 0x4c);
ian@0 259 iounmap(p);
ian@0 260
ian@0 261 return 0;
ian@0 262 }
ian@0 263
ian@0 264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
ian@0 265 {
ian@0 266 u8 __iomem *p;
ian@0 267
ian@0 268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
ian@0 269 return;
ian@0 270
ian@0 271 /*
ian@0 272 * disable interrupts
ian@0 273 */
ian@0 274 p = ioremap(pci_resource_start(dev, 0), 0x80);
ian@0 275 if (p != NULL) {
ian@0 276 writel(0, p + 0x4c);
ian@0 277
ian@0 278 /*
ian@0 279 * Read the register back to ensure that it took effect.
ian@0 280 */
ian@0 281 readl(p + 0x4c);
ian@0 282 iounmap(p);
ian@0 283 }
ian@0 284 }
ian@0 285
ian@0 286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
ian@0 287 static int
ian@0 288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
ian@0 289 struct uart_port *port, int idx)
ian@0 290 {
ian@0 291 unsigned int bar, offset = board->first_offset;
ian@0 292
ian@0 293 bar = 0;
ian@0 294
ian@0 295 if (idx < 4) {
ian@0 296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
ian@0 297 offset += idx * board->uart_offset;
ian@0 298 } else if (idx < 8) {
ian@0 299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
ian@0 300 offset += idx * board->uart_offset + 0xC00;
ian@0 301 } else /* we have only 8 ports on PMC-OCTALPRO */
ian@0 302 return 1;
ian@0 303
ian@0 304 return setup_port(priv, port, bar, offset, board->reg_shift);
ian@0 305 }
ian@0 306
ian@0 307 /*
ian@0 308 * This does initialization for PMC OCTALPRO cards:
ian@0 309 * maps the device memory, resets the UARTs (needed, bc
ian@0 310 * if the module is removed and inserted again, the card
ian@0 311 * is in the sleep mode) and enables global interrupt.
ian@0 312 */
ian@0 313
ian@0 314 /* global control register offset for SBS PMC-OctalPro */
ian@0 315 #define OCT_REG_CR_OFF 0x500
ian@0 316
ian@0 317 static int sbs_init(struct pci_dev *dev)
ian@0 318 {
ian@0 319 u8 __iomem *p;
ian@0 320
ian@0 321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
ian@0 322
ian@0 323 if (p == NULL)
ian@0 324 return -ENOMEM;
ian@0 325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
ian@0 326 writeb(0x10,p + OCT_REG_CR_OFF);
ian@0 327 udelay(50);
ian@0 328 writeb(0x0,p + OCT_REG_CR_OFF);
ian@0 329
ian@0 330 /* Set bit-2 (INTENABLE) of Control Register */
ian@0 331 writeb(0x4, p + OCT_REG_CR_OFF);
ian@0 332 iounmap(p);
ian@0 333
ian@0 334 return 0;
ian@0 335 }
ian@0 336
ian@0 337 /*
ian@0 338 * Disables the global interrupt of PMC-OctalPro
ian@0 339 */
ian@0 340
ian@0 341 static void __devexit sbs_exit(struct pci_dev *dev)
ian@0 342 {
ian@0 343 u8 __iomem *p;
ian@0 344
ian@0 345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
ian@0 346 if (p != NULL) {
ian@0 347 writeb(0, p + OCT_REG_CR_OFF);
ian@0 348 }
ian@0 349 iounmap(p);
ian@0 350 }
ian@0 351
ian@0 352 /*
ian@0 353 * SIIG serial cards have an PCI interface chip which also controls
ian@0 354 * the UART clocking frequency. Each UART can be clocked independently
ian@0 355 * (except cards equiped with 4 UARTs) and initial clocking settings
ian@0 356 * are stored in the EEPROM chip. It can cause problems because this
ian@0 357 * version of serial driver doesn't support differently clocked UART's
ian@0 358 * on single PCI card. To prevent this, initialization functions set
ian@0 359 * high frequency clocking for all UART's on given card. It is safe (I
ian@0 360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
ian@0 361 * with other OSes (like M$ DOS).
ian@0 362 *
ian@0 363 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
ian@0 364 *
ian@0 365 * There is two family of SIIG serial cards with different PCI
ian@0 366 * interface chip and different configuration methods:
ian@0 367 * - 10x cards have control registers in IO and/or memory space;
ian@0 368 * - 20x cards have control registers in standard PCI configuration space.
ian@0 369 *
ian@0 370 * Note: all 10x cards have PCI device ids 0x10..
ian@0 371 * all 20x cards have PCI device ids 0x20..
ian@0 372 *
ian@0 373 * There are also Quartet Serial cards which use Oxford Semiconductor
ian@0 374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
ian@0 375 *
ian@0 376 * Note: some SIIG cards are probed by the parport_serial object.
ian@0 377 */
ian@0 378
ian@0 379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
ian@0 380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
ian@0 381
ian@0 382 static int pci_siig10x_init(struct pci_dev *dev)
ian@0 383 {
ian@0 384 u16 data;
ian@0 385 void __iomem *p;
ian@0 386
ian@0 387 switch (dev->device & 0xfff8) {
ian@0 388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
ian@0 389 data = 0xffdf;
ian@0 390 break;
ian@0 391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
ian@0 392 data = 0xf7ff;
ian@0 393 break;
ian@0 394 default: /* 1S1P, 4S */
ian@0 395 data = 0xfffb;
ian@0 396 break;
ian@0 397 }
ian@0 398
ian@0 399 p = ioremap(pci_resource_start(dev, 0), 0x80);
ian@0 400 if (p == NULL)
ian@0 401 return -ENOMEM;
ian@0 402
ian@0 403 writew(readw(p + 0x28) & data, p + 0x28);
ian@0 404 readw(p + 0x28);
ian@0 405 iounmap(p);
ian@0 406 return 0;
ian@0 407 }
ian@0 408
ian@0 409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
ian@0 410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
ian@0 411
ian@0 412 static int pci_siig20x_init(struct pci_dev *dev)
ian@0 413 {
ian@0 414 u8 data;
ian@0 415
ian@0 416 /* Change clock frequency for the first UART. */
ian@0 417 pci_read_config_byte(dev, 0x6f, &data);
ian@0 418 pci_write_config_byte(dev, 0x6f, data & 0xef);
ian@0 419
ian@0 420 /* If this card has 2 UART, we have to do the same with second UART. */
ian@0 421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
ian@0 422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
ian@0 423 pci_read_config_byte(dev, 0x73, &data);
ian@0 424 pci_write_config_byte(dev, 0x73, data & 0xef);
ian@0 425 }
ian@0 426 return 0;
ian@0 427 }
ian@0 428
ian@0 429 static int pci_siig_init(struct pci_dev *dev)
ian@0 430 {
ian@0 431 unsigned int type = dev->device & 0xff00;
ian@0 432
ian@0 433 if (type == 0x1000)
ian@0 434 return pci_siig10x_init(dev);
ian@0 435 else if (type == 0x2000)
ian@0 436 return pci_siig20x_init(dev);
ian@0 437
ian@0 438 moan_device("Unknown SIIG card", dev);
ian@0 439 return -ENODEV;
ian@0 440 }
ian@0 441
ian@0 442 static int pci_siig_setup(struct serial_private *priv,
ian@0 443 struct pciserial_board *board,
ian@0 444 struct uart_port *port, int idx)
ian@0 445 {
ian@0 446 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
ian@0 447
ian@0 448 if (idx > 3) {
ian@0 449 bar = 4;
ian@0 450 offset = (idx - 4) * 8;
ian@0 451 }
ian@0 452
ian@0 453 return setup_port(priv, port, bar, offset, 0);
ian@0 454 }
ian@0 455
ian@0 456 /*
ian@0 457 * Timedia has an explosion of boards, and to avoid the PCI table from
ian@0 458 * growing *huge*, we use this function to collapse some 70 entries
ian@0 459 * in the PCI table into one, for sanity's and compactness's sake.
ian@0 460 */
ian@0 461 static const unsigned short timedia_single_port[] = {
ian@0 462 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
ian@0 463 };
ian@0 464
ian@0 465 static const unsigned short timedia_dual_port[] = {
ian@0 466 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
ian@0 467 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
ian@0 468 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
ian@0 469 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
ian@0 470 0xD079, 0
ian@0 471 };
ian@0 472
ian@0 473 static const unsigned short timedia_quad_port[] = {
ian@0 474 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
ian@0 475 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
ian@0 476 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
ian@0 477 0xB157, 0
ian@0 478 };
ian@0 479
ian@0 480 static const unsigned short timedia_eight_port[] = {
ian@0 481 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
ian@0 482 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
ian@0 483 };
ian@0 484
ian@0 485 static const struct timedia_struct {
ian@0 486 int num;
ian@0 487 const unsigned short *ids;
ian@0 488 } timedia_data[] = {
ian@0 489 { 1, timedia_single_port },
ian@0 490 { 2, timedia_dual_port },
ian@0 491 { 4, timedia_quad_port },
ian@0 492 { 8, timedia_eight_port }
ian@0 493 };
ian@0 494
ian@0 495 static int pci_timedia_init(struct pci_dev *dev)
ian@0 496 {
ian@0 497 const unsigned short *ids;
ian@0 498 int i, j;
ian@0 499
ian@0 500 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
ian@0 501 ids = timedia_data[i].ids;
ian@0 502 for (j = 0; ids[j]; j++)
ian@0 503 if (dev->subsystem_device == ids[j])
ian@0 504 return timedia_data[i].num;
ian@0 505 }
ian@0 506 return 0;
ian@0 507 }
ian@0 508
ian@0 509 /*
ian@0 510 * Timedia/SUNIX uses a mixture of BARs and offsets
ian@0 511 * Ugh, this is ugly as all hell --- TYT
ian@0 512 */
ian@0 513 static int
ian@0 514 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
ian@0 515 struct uart_port *port, int idx)
ian@0 516 {
ian@0 517 unsigned int bar = 0, offset = board->first_offset;
ian@0 518
ian@0 519 switch (idx) {
ian@0 520 case 0:
ian@0 521 bar = 0;
ian@0 522 break;
ian@0 523 case 1:
ian@0 524 offset = board->uart_offset;
ian@0 525 bar = 0;
ian@0 526 break;
ian@0 527 case 2:
ian@0 528 bar = 1;
ian@0 529 break;
ian@0 530 case 3:
ian@0 531 offset = board->uart_offset;
ian@0 532 /* FALLTHROUGH */
ian@0 533 case 4: /* BAR 2 */
ian@0 534 case 5: /* BAR 3 */
ian@0 535 case 6: /* BAR 4 */
ian@0 536 case 7: /* BAR 5 */
ian@0 537 bar = idx - 2;
ian@0 538 }
ian@0 539
ian@0 540 return setup_port(priv, port, bar, offset, board->reg_shift);
ian@0 541 }
ian@0 542
ian@0 543 /*
ian@0 544 * Some Titan cards are also a little weird
ian@0 545 */
ian@0 546 static int
ian@0 547 titan_400l_800l_setup(struct serial_private *priv,
ian@0 548 struct pciserial_board *board,
ian@0 549 struct uart_port *port, int idx)
ian@0 550 {
ian@0 551 unsigned int bar, offset = board->first_offset;
ian@0 552
ian@0 553 switch (idx) {
ian@0 554 case 0:
ian@0 555 bar = 1;
ian@0 556 break;
ian@0 557 case 1:
ian@0 558 bar = 2;
ian@0 559 break;
ian@0 560 default:
ian@0 561 bar = 4;
ian@0 562 offset = (idx - 2) * board->uart_offset;
ian@0 563 }
ian@0 564
ian@0 565 return setup_port(priv, port, bar, offset, board->reg_shift);
ian@0 566 }
ian@0 567
ian@0 568 static int pci_xircom_init(struct pci_dev *dev)
ian@0 569 {
ian@0 570 msleep(100);
ian@0 571 return 0;
ian@0 572 }
ian@0 573
ian@0 574 static int pci_netmos_init(struct pci_dev *dev)
ian@0 575 {
ian@0 576 /* subdevice 0x00PS means <P> parallel, <S> serial */
ian@0 577 unsigned int num_serial = dev->subsystem_device & 0xf;
ian@0 578
ian@0 579 if (num_serial == 0)
ian@0 580 return -ENODEV;
ian@0 581 return num_serial;
ian@0 582 }
ian@0 583
ian@0 584 static int
ian@0 585 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
ian@0 586 struct uart_port *port, int idx)
ian@0 587 {
ian@0 588 unsigned int bar, offset = board->first_offset, maxnr;
ian@0 589
ian@0 590 bar = FL_GET_BASE(board->flags);
ian@0 591 if (board->flags & FL_BASE_BARS)
ian@0 592 bar += idx;
ian@0 593 else
ian@0 594 offset += idx * board->uart_offset;
ian@0 595
ian@0 596 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
ian@0 597 (board->reg_shift + 3);
ian@0 598
ian@0 599 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
ian@0 600 return 1;
ian@0 601
ian@0 602 return setup_port(priv, port, bar, offset, board->reg_shift);
ian@0 603 }
ian@0 604
ian@0 605 /* This should be in linux/pci_ids.h */
ian@0 606 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
ian@0 607 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
ian@0 608 #define PCI_DEVICE_ID_OCTPRO 0x0001
ian@0 609 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
ian@0 610 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
ian@0 611 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
ian@0 612 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
ian@0 613
ian@0 614 /*
ian@0 615 * Master list of serial port init/setup/exit quirks.
ian@0 616 * This does not describe the general nature of the port.
ian@0 617 * (ie, baud base, number and location of ports, etc)
ian@0 618 *
ian@0 619 * This list is ordered alphabetically by vendor then device.
ian@0 620 * Specific entries must come before more generic entries.
ian@0 621 */
ian@0 622 static struct pci_serial_quirk pci_serial_quirks[] = {
ian@0 623 /*
ian@0 624 * AFAVLAB cards - these may be called via parport_serial
ian@0 625 * It is not clear whether this applies to all products.
ian@0 626 */
ian@0 627 {
ian@0 628 .vendor = PCI_VENDOR_ID_AFAVLAB,
ian@0 629 .device = PCI_ANY_ID,
ian@0 630 .subvendor = PCI_ANY_ID,
ian@0 631 .subdevice = PCI_ANY_ID,
ian@0 632 .setup = afavlab_setup,
ian@0 633 },
ian@0 634 /*
ian@0 635 * HP Diva
ian@0 636 */
ian@0 637 {
ian@0 638 .vendor = PCI_VENDOR_ID_HP,
ian@0 639 .device = PCI_DEVICE_ID_HP_DIVA,
ian@0 640 .subvendor = PCI_ANY_ID,
ian@0 641 .subdevice = PCI_ANY_ID,
ian@0 642 .init = pci_hp_diva_init,
ian@0 643 .setup = pci_hp_diva_setup,
ian@0 644 },
ian@0 645 /*
ian@0 646 * Intel
ian@0 647 */
ian@0 648 {
ian@0 649 .vendor = PCI_VENDOR_ID_INTEL,
ian@0 650 .device = PCI_DEVICE_ID_INTEL_80960_RP,
ian@0 651 .subvendor = 0xe4bf,
ian@0 652 .subdevice = PCI_ANY_ID,
ian@0 653 .init = pci_inteli960ni_init,
ian@0 654 .setup = pci_default_setup,
ian@0 655 },
ian@0 656 /*
ian@0 657 * Panacom
ian@0 658 */
ian@0 659 {
ian@0 660 .vendor = PCI_VENDOR_ID_PANACOM,
ian@0 661 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
ian@0 662 .subvendor = PCI_ANY_ID,
ian@0 663 .subdevice = PCI_ANY_ID,
ian@0 664 .init = pci_plx9050_init,
ian@0 665 .setup = pci_default_setup,
ian@0 666 .exit = __devexit_p(pci_plx9050_exit),
ian@0 667 },
ian@0 668 {
ian@0 669 .vendor = PCI_VENDOR_ID_PANACOM,
ian@0 670 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
ian@0 671 .subvendor = PCI_ANY_ID,
ian@0 672 .subdevice = PCI_ANY_ID,
ian@0 673 .init = pci_plx9050_init,
ian@0 674 .setup = pci_default_setup,
ian@0 675 .exit = __devexit_p(pci_plx9050_exit),
ian@0 676 },
ian@0 677 /*
ian@0 678 * PLX
ian@0 679 */
ian@0 680 {
ian@0 681 .vendor = PCI_VENDOR_ID_PLX,
ian@0 682 .device = PCI_DEVICE_ID_PLX_9050,
ian@0 683 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
ian@0 684 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
ian@0 685 .init = pci_plx9050_init,
ian@0 686 .setup = pci_default_setup,
ian@0 687 .exit = __devexit_p(pci_plx9050_exit),
ian@0 688 },
ian@0 689 {
ian@0 690 .vendor = PCI_VENDOR_ID_PLX,
ian@0 691 .device = PCI_DEVICE_ID_PLX_9050,
ian@0 692 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
ian@0 693 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
ian@0 694 .init = pci_plx9050_init,
ian@0 695 .setup = pci_default_setup,
ian@0 696 .exit = __devexit_p(pci_plx9050_exit),
ian@0 697 },
ian@0 698 {
ian@0 699 .vendor = PCI_VENDOR_ID_PLX,
ian@0 700 .device = PCI_DEVICE_ID_PLX_ROMULUS,
ian@0 701 .subvendor = PCI_VENDOR_ID_PLX,
ian@0 702 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
ian@0 703 .init = pci_plx9050_init,
ian@0 704 .setup = pci_default_setup,
ian@0 705 .exit = __devexit_p(pci_plx9050_exit),
ian@0 706 },
ian@0 707 /*
ian@0 708 * SBS Technologies, Inc., PMC-OCTALPRO 232
ian@0 709 */
ian@0 710 {
ian@0 711 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
ian@0 712 .device = PCI_DEVICE_ID_OCTPRO,
ian@0 713 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
ian@0 714 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
ian@0 715 .init = sbs_init,
ian@0 716 .setup = sbs_setup,
ian@0 717 .exit = __devexit_p(sbs_exit),
ian@0 718 },
ian@0 719 /*
ian@0 720 * SBS Technologies, Inc., PMC-OCTALPRO 422
ian@0 721 */
ian@0 722 {
ian@0 723 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
ian@0 724 .device = PCI_DEVICE_ID_OCTPRO,
ian@0 725 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
ian@0 726 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
ian@0 727 .init = sbs_init,
ian@0 728 .setup = sbs_setup,
ian@0 729 .exit = __devexit_p(sbs_exit),
ian@0 730 },
ian@0 731 /*
ian@0 732 * SBS Technologies, Inc., P-Octal 232
ian@0 733 */
ian@0 734 {
ian@0 735 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
ian@0 736 .device = PCI_DEVICE_ID_OCTPRO,
ian@0 737 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
ian@0 738 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
ian@0 739 .init = sbs_init,
ian@0 740 .setup = sbs_setup,
ian@0 741 .exit = __devexit_p(sbs_exit),
ian@0 742 },
ian@0 743 /*
ian@0 744 * SBS Technologies, Inc., P-Octal 422
ian@0 745 */
ian@0 746 {
ian@0 747 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
ian@0 748 .device = PCI_DEVICE_ID_OCTPRO,
ian@0 749 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
ian@0 750 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
ian@0 751 .init = sbs_init,
ian@0 752 .setup = sbs_setup,
ian@0 753 .exit = __devexit_p(sbs_exit),
ian@0 754 },
ian@0 755 /*
ian@0 756 * SIIG cards - these may be called via parport_serial
ian@0 757 */
ian@0 758 {
ian@0 759 .vendor = PCI_VENDOR_ID_SIIG,
ian@0 760 .device = PCI_ANY_ID,
ian@0 761 .subvendor = PCI_ANY_ID,
ian@0 762 .subdevice = PCI_ANY_ID,
ian@0 763 .init = pci_siig_init,
ian@0 764 .setup = pci_siig_setup,
ian@0 765 },
ian@0 766 /*
ian@0 767 * Titan cards
ian@0 768 */
ian@0 769 {
ian@0 770 .vendor = PCI_VENDOR_ID_TITAN,
ian@0 771 .device = PCI_DEVICE_ID_TITAN_400L,
ian@0 772 .subvendor = PCI_ANY_ID,
ian@0 773 .subdevice = PCI_ANY_ID,
ian@0 774 .setup = titan_400l_800l_setup,
ian@0 775 },
ian@0 776 {
ian@0 777 .vendor = PCI_VENDOR_ID_TITAN,
ian@0 778 .device = PCI_DEVICE_ID_TITAN_800L,
ian@0 779 .subvendor = PCI_ANY_ID,
ian@0 780 .subdevice = PCI_ANY_ID,
ian@0 781 .setup = titan_400l_800l_setup,
ian@0 782 },
ian@0 783 /*
ian@0 784 * Timedia cards
ian@0 785 */
ian@0 786 {
ian@0 787 .vendor = PCI_VENDOR_ID_TIMEDIA,
ian@0 788 .device = PCI_DEVICE_ID_TIMEDIA_1889,
ian@0 789 .subvendor = PCI_VENDOR_ID_TIMEDIA,
ian@0 790 .subdevice = PCI_ANY_ID,
ian@0 791 .init = pci_timedia_init,
ian@0 792 .setup = pci_timedia_setup,
ian@0 793 },
ian@0 794 {
ian@0 795 .vendor = PCI_VENDOR_ID_TIMEDIA,
ian@0 796 .device = PCI_ANY_ID,
ian@0 797 .subvendor = PCI_ANY_ID,
ian@0 798 .subdevice = PCI_ANY_ID,
ian@0 799 .setup = pci_timedia_setup,
ian@0 800 },
ian@0 801 /*
ian@0 802 * Xircom cards
ian@0 803 */
ian@0 804 {
ian@0 805 .vendor = PCI_VENDOR_ID_XIRCOM,
ian@0 806 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
ian@0 807 .subvendor = PCI_ANY_ID,
ian@0 808 .subdevice = PCI_ANY_ID,
ian@0 809 .init = pci_xircom_init,
ian@0 810 .setup = pci_default_setup,
ian@0 811 },
ian@0 812 /*
ian@0 813 * Netmos cards - these may be called via parport_serial
ian@0 814 */
ian@0 815 {
ian@0 816 .vendor = PCI_VENDOR_ID_NETMOS,
ian@0 817 .device = PCI_ANY_ID,
ian@0 818 .subvendor = PCI_ANY_ID,
ian@0 819 .subdevice = PCI_ANY_ID,
ian@0 820 .init = pci_netmos_init,
ian@0 821 .setup = pci_default_setup,
ian@0 822 },
ian@0 823 /*
ian@0 824 * Default "match everything" terminator entry
ian@0 825 */
ian@0 826 {
ian@0 827 .vendor = PCI_ANY_ID,
ian@0 828 .device = PCI_ANY_ID,
ian@0 829 .subvendor = PCI_ANY_ID,
ian@0 830 .subdevice = PCI_ANY_ID,
ian@0 831 .setup = pci_default_setup,
ian@0 832 }
ian@0 833 };
ian@0 834
ian@0 835 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
ian@0 836 {
ian@0 837 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
ian@0 838 }
ian@0 839
ian@0 840 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
ian@0 841 {
ian@0 842 struct pci_serial_quirk *quirk;
ian@0 843
ian@0 844 for (quirk = pci_serial_quirks; ; quirk++)
ian@0 845 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
ian@0 846 quirk_id_matches(quirk->device, dev->device) &&
ian@0 847 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
ian@0 848 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
ian@0 849 break;
ian@0 850 return quirk;
ian@0 851 }
ian@0 852
ian@0 853 static inline int get_pci_irq(struct pci_dev *dev,
ian@0 854 struct pciserial_board *board)
ian@0 855 {
ian@0 856 if (board->flags & FL_NOIRQ)
ian@0 857 return 0;
ian@0 858 else
ian@0 859 return dev->irq;
ian@0 860 }
ian@0 861
ian@0 862 /*
ian@0 863 * This is the configuration table for all of the PCI serial boards
ian@0 864 * which we support. It is directly indexed by the pci_board_num_t enum
ian@0 865 * value, which is encoded in the pci_device_id PCI probe table's
ian@0 866 * driver_data member.
ian@0 867 *
ian@0 868 * The makeup of these names are:
ian@0 869 * pbn_bn{_bt}_n_baud{_offsetinhex}
ian@0 870 *
ian@0 871 * bn = PCI BAR number
ian@0 872 * bt = Index using PCI BARs
ian@0 873 * n = number of serial ports
ian@0 874 * baud = baud rate
ian@0 875 * offsetinhex = offset for each sequential port (in hex)
ian@0 876 *
ian@0 877 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
ian@0 878 *
ian@0 879 * Please note: in theory if n = 1, _bt infix should make no difference.
ian@0 880 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
ian@0 881 */
ian@0 882 enum pci_board_num_t {
ian@0 883 pbn_default = 0,
ian@0 884
ian@0 885 pbn_b0_1_115200,
ian@0 886 pbn_b0_2_115200,
ian@0 887 pbn_b0_4_115200,
ian@0 888 pbn_b0_5_115200,
ian@0 889
ian@0 890 pbn_b0_1_921600,
ian@0 891 pbn_b0_2_921600,
ian@0 892 pbn_b0_4_921600,
ian@0 893
ian@0 894 pbn_b0_2_1130000,
ian@0 895
ian@0 896 pbn_b0_4_1152000,
ian@0 897
ian@0 898 pbn_b0_2_1843200,
ian@0 899 pbn_b0_4_1843200,
ian@0 900
ian@0 901 pbn_b0_2_1843200_200,
ian@0 902 pbn_b0_4_1843200_200,
ian@0 903 pbn_b0_8_1843200_200,
ian@0 904
ian@0 905 pbn_b0_bt_1_115200,
ian@0 906 pbn_b0_bt_2_115200,
ian@0 907 pbn_b0_bt_8_115200,
ian@0 908
ian@0 909 pbn_b0_bt_1_460800,
ian@0 910 pbn_b0_bt_2_460800,
ian@0 911 pbn_b0_bt_4_460800,
ian@0 912
ian@0 913 pbn_b0_bt_1_921600,
ian@0 914 pbn_b0_bt_2_921600,
ian@0 915 pbn_b0_bt_4_921600,
ian@0 916 pbn_b0_bt_8_921600,
ian@0 917
ian@0 918 pbn_b1_1_115200,
ian@0 919 pbn_b1_2_115200,
ian@0 920 pbn_b1_4_115200,
ian@0 921 pbn_b1_8_115200,
ian@0 922
ian@0 923 pbn_b1_1_921600,
ian@0 924 pbn_b1_2_921600,
ian@0 925 pbn_b1_4_921600,
ian@0 926 pbn_b1_8_921600,
ian@0 927
ian@0 928 pbn_b1_2_1250000,
ian@0 929
ian@0 930 pbn_b1_bt_2_921600,
ian@0 931
ian@0 932 pbn_b1_1_1382400,
ian@0 933 pbn_b1_2_1382400,
ian@0 934 pbn_b1_4_1382400,
ian@0 935 pbn_b1_8_1382400,
ian@0 936
ian@0 937 pbn_b2_1_115200,
ian@0 938 pbn_b2_2_115200,
ian@0 939 pbn_b2_8_115200,
ian@0 940
ian@0 941 pbn_b2_1_460800,
ian@0 942 pbn_b2_4_460800,
ian@0 943 pbn_b2_8_460800,
ian@0 944 pbn_b2_16_460800,
ian@0 945
ian@0 946 pbn_b2_1_921600,
ian@0 947 pbn_b2_4_921600,
ian@0 948 pbn_b2_8_921600,
ian@0 949
ian@0 950 pbn_b2_bt_1_115200,
ian@0 951 pbn_b2_bt_2_115200,
ian@0 952 pbn_b2_bt_4_115200,
ian@0 953
ian@0 954 pbn_b2_bt_2_921600,
ian@0 955 pbn_b2_bt_4_921600,
ian@0 956
ian@0 957 pbn_b3_2_115200,
ian@0 958 pbn_b3_4_115200,
ian@0 959 pbn_b3_8_115200,
ian@0 960
ian@0 961 /*
ian@0 962 * Board-specific versions.
ian@0 963 */
ian@0 964 pbn_panacom,
ian@0 965 pbn_panacom2,
ian@0 966 pbn_panacom4,
ian@0 967 pbn_exsys_4055,
ian@0 968 pbn_plx_romulus,
ian@0 969 pbn_oxsemi,
ian@0 970 pbn_intel_i960,
ian@0 971 pbn_sgi_ioc3,
ian@0 972 pbn_nec_nile4,
ian@0 973 pbn_computone_4,
ian@0 974 pbn_computone_6,
ian@0 975 pbn_computone_8,
ian@0 976 pbn_sbsxrsio,
ian@0 977 pbn_exar_XR17C152,
ian@0 978 pbn_exar_XR17C154,
ian@0 979 pbn_exar_XR17C158,
ian@0 980 };
ian@0 981
ian@0 982 /*
ian@0 983 * uart_offset - the space between channels
ian@0 984 * reg_shift - describes how the UART registers are mapped
ian@0 985 * to PCI memory by the card.
ian@0 986 * For example IER register on SBS, Inc. PMC-OctPro is located at
ian@0 987 * offset 0x10 from the UART base, while UART_IER is defined as 1
ian@0 988 * in include/linux/serial_reg.h,
ian@0 989 * see first lines of serial_in() and serial_out() in 8250.c
ian@0 990 */
ian@0 991
ian@0 992 static struct pciserial_board pci_boards[] __devinitdata = {
ian@0 993 [pbn_default] = {
ian@0 994 .flags = FL_BASE0,
ian@0 995 .num_ports = 1,
ian@0 996 .base_baud = 115200,
ian@0 997 .uart_offset = 8,
ian@0 998 },
ian@0 999 [pbn_b0_1_115200] = {
ian@0 1000 .flags = FL_BASE0,
ian@0 1001 .num_ports = 1,
ian@0 1002 .base_baud = 115200,
ian@0 1003 .uart_offset = 8,
ian@0 1004 },
ian@0 1005 [pbn_b0_2_115200] = {
ian@0 1006 .flags = FL_BASE0,
ian@0 1007 .num_ports = 2,
ian@0 1008 .base_baud = 115200,
ian@0 1009 .uart_offset = 8,
ian@0 1010 },
ian@0 1011 [pbn_b0_4_115200] = {
ian@0 1012 .flags = FL_BASE0,
ian@0 1013 .num_ports = 4,
ian@0 1014 .base_baud = 115200,
ian@0 1015 .uart_offset = 8,
ian@0 1016 },
ian@0 1017 [pbn_b0_5_115200] = {
ian@0 1018 .flags = FL_BASE0,
ian@0 1019 .num_ports = 5,
ian@0 1020 .base_baud = 115200,
ian@0 1021 .uart_offset = 8,
ian@0 1022 },
ian@0 1023
ian@0 1024 [pbn_b0_1_921600] = {
ian@0 1025 .flags = FL_BASE0,
ian@0 1026 .num_ports = 1,
ian@0 1027 .base_baud = 921600,
ian@0 1028 .uart_offset = 8,
ian@0 1029 },
ian@0 1030 [pbn_b0_2_921600] = {
ian@0 1031 .flags = FL_BASE0,
ian@0 1032 .num_ports = 2,
ian@0 1033 .base_baud = 921600,
ian@0 1034 .uart_offset = 8,
ian@0 1035 },
ian@0 1036 [pbn_b0_4_921600] = {
ian@0 1037 .flags = FL_BASE0,
ian@0 1038 .num_ports = 4,
ian@0 1039 .base_baud = 921600,
ian@0 1040 .uart_offset = 8,
ian@0 1041 },
ian@0 1042
ian@0 1043 [pbn_b0_2_1130000] = {
ian@0 1044 .flags = FL_BASE0,
ian@0 1045 .num_ports = 2,
ian@0 1046 .base_baud = 1130000,
ian@0 1047 .uart_offset = 8,
ian@0 1048 },
ian@0 1049
ian@0 1050 [pbn_b0_4_1152000] = {
ian@0 1051 .flags = FL_BASE0,
ian@0 1052 .num_ports = 4,
ian@0 1053 .base_baud = 1152000,
ian@0 1054 .uart_offset = 8,
ian@0 1055 },
ian@0 1056
ian@0 1057 [pbn_b0_2_1843200] = {
ian@0 1058 .flags = FL_BASE0,
ian@0 1059 .num_ports = 2,
ian@0 1060 .base_baud = 1843200,
ian@0 1061 .uart_offset = 8,
ian@0 1062 },
ian@0 1063 [pbn_b0_4_1843200] = {
ian@0 1064 .flags = FL_BASE0,
ian@0 1065 .num_ports = 4,
ian@0 1066 .base_baud = 1843200,
ian@0 1067 .uart_offset = 8,
ian@0 1068 },
ian@0 1069
ian@0 1070 [pbn_b0_2_1843200_200] = {
ian@0 1071 .flags = FL_BASE0,
ian@0 1072 .num_ports = 2,
ian@0 1073 .base_baud = 1843200,
ian@0 1074 .uart_offset = 0x200,
ian@0 1075 },
ian@0 1076 [pbn_b0_4_1843200_200] = {
ian@0 1077 .flags = FL_BASE0,
ian@0 1078 .num_ports = 4,
ian@0 1079 .base_baud = 1843200,
ian@0 1080 .uart_offset = 0x200,
ian@0 1081 },
ian@0 1082 [pbn_b0_8_1843200_200] = {
ian@0 1083 .flags = FL_BASE0,
ian@0 1084 .num_ports = 8,
ian@0 1085 .base_baud = 1843200,
ian@0 1086 .uart_offset = 0x200,
ian@0 1087 },
ian@0 1088
ian@0 1089 [pbn_b0_bt_1_115200] = {
ian@0 1090 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1091 .num_ports = 1,
ian@0 1092 .base_baud = 115200,
ian@0 1093 .uart_offset = 8,
ian@0 1094 },
ian@0 1095 [pbn_b0_bt_2_115200] = {
ian@0 1096 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1097 .num_ports = 2,
ian@0 1098 .base_baud = 115200,
ian@0 1099 .uart_offset = 8,
ian@0 1100 },
ian@0 1101 [pbn_b0_bt_8_115200] = {
ian@0 1102 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1103 .num_ports = 8,
ian@0 1104 .base_baud = 115200,
ian@0 1105 .uart_offset = 8,
ian@0 1106 },
ian@0 1107
ian@0 1108 [pbn_b0_bt_1_460800] = {
ian@0 1109 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1110 .num_ports = 1,
ian@0 1111 .base_baud = 460800,
ian@0 1112 .uart_offset = 8,
ian@0 1113 },
ian@0 1114 [pbn_b0_bt_2_460800] = {
ian@0 1115 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1116 .num_ports = 2,
ian@0 1117 .base_baud = 460800,
ian@0 1118 .uart_offset = 8,
ian@0 1119 },
ian@0 1120 [pbn_b0_bt_4_460800] = {
ian@0 1121 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1122 .num_ports = 4,
ian@0 1123 .base_baud = 460800,
ian@0 1124 .uart_offset = 8,
ian@0 1125 },
ian@0 1126
ian@0 1127 [pbn_b0_bt_1_921600] = {
ian@0 1128 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1129 .num_ports = 1,
ian@0 1130 .base_baud = 921600,
ian@0 1131 .uart_offset = 8,
ian@0 1132 },
ian@0 1133 [pbn_b0_bt_2_921600] = {
ian@0 1134 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1135 .num_ports = 2,
ian@0 1136 .base_baud = 921600,
ian@0 1137 .uart_offset = 8,
ian@0 1138 },
ian@0 1139 [pbn_b0_bt_4_921600] = {
ian@0 1140 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1141 .num_ports = 4,
ian@0 1142 .base_baud = 921600,
ian@0 1143 .uart_offset = 8,
ian@0 1144 },
ian@0 1145 [pbn_b0_bt_8_921600] = {
ian@0 1146 .flags = FL_BASE0|FL_BASE_BARS,
ian@0 1147 .num_ports = 8,
ian@0 1148 .base_baud = 921600,
ian@0 1149 .uart_offset = 8,
ian@0 1150 },
ian@0 1151
ian@0 1152 [pbn_b1_1_115200] = {
ian@0 1153 .flags = FL_BASE1,
ian@0 1154 .num_ports = 1,
ian@0 1155 .base_baud = 115200,
ian@0 1156 .uart_offset = 8,
ian@0 1157 },
ian@0 1158 [pbn_b1_2_115200] = {
ian@0 1159 .flags = FL_BASE1,
ian@0 1160 .num_ports = 2,
ian@0 1161 .base_baud = 115200,
ian@0 1162 .uart_offset = 8,
ian@0 1163 },
ian@0 1164 [pbn_b1_4_115200] = {
ian@0 1165 .flags = FL_BASE1,
ian@0 1166 .num_ports = 4,
ian@0 1167 .base_baud = 115200,
ian@0 1168 .uart_offset = 8,
ian@0 1169 },
ian@0 1170 [pbn_b1_8_115200] = {
ian@0 1171 .flags = FL_BASE1,
ian@0 1172 .num_ports = 8,
ian@0 1173 .base_baud = 115200,
ian@0 1174 .uart_offset = 8,
ian@0 1175 },
ian@0 1176
ian@0 1177 [pbn_b1_1_921600] = {
ian@0 1178 .flags = FL_BASE1,
ian@0 1179 .num_ports = 1,
ian@0 1180 .base_baud = 921600,
ian@0 1181 .uart_offset = 8,
ian@0 1182 },
ian@0 1183 [pbn_b1_2_921600] = {
ian@0 1184 .flags = FL_BASE1,
ian@0 1185 .num_ports = 2,
ian@0 1186 .base_baud = 921600,
ian@0 1187 .uart_offset = 8,
ian@0 1188 },
ian@0 1189 [pbn_b1_4_921600] = {
ian@0 1190 .flags = FL_BASE1,
ian@0 1191 .num_ports = 4,
ian@0 1192 .base_baud = 921600,
ian@0 1193 .uart_offset = 8,
ian@0 1194 },
ian@0 1195 [pbn_b1_8_921600] = {
ian@0 1196 .flags = FL_BASE1,
ian@0 1197 .num_ports = 8,
ian@0 1198 .base_baud = 921600,
ian@0 1199 .uart_offset = 8,
ian@0 1200 },
ian@0 1201 [pbn_b1_2_1250000] = {
ian@0 1202 .flags = FL_BASE1,
ian@0 1203 .num_ports = 2,
ian@0 1204 .base_baud = 1250000,
ian@0 1205 .uart_offset = 8,
ian@0 1206 },
ian@0 1207
ian@0 1208 [pbn_b1_bt_2_921600] = {
ian@0 1209 .flags = FL_BASE1|FL_BASE_BARS,
ian@0 1210 .num_ports = 2,
ian@0 1211 .base_baud = 921600,
ian@0 1212 .uart_offset = 8,
ian@0 1213 },
ian@0 1214
ian@0 1215 [pbn_b1_1_1382400] = {
ian@0 1216 .flags = FL_BASE1,
ian@0 1217 .num_ports = 1,
ian@0 1218 .base_baud = 1382400,
ian@0 1219 .uart_offset = 8,
ian@0 1220 },
ian@0 1221 [pbn_b1_2_1382400] = {
ian@0 1222 .flags = FL_BASE1,
ian@0 1223 .num_ports = 2,
ian@0 1224 .base_baud = 1382400,
ian@0 1225 .uart_offset = 8,
ian@0 1226 },
ian@0 1227 [pbn_b1_4_1382400] = {
ian@0 1228 .flags = FL_BASE1,
ian@0 1229 .num_ports = 4,
ian@0 1230 .base_baud = 1382400,
ian@0 1231 .uart_offset = 8,
ian@0 1232 },
ian@0 1233 [pbn_b1_8_1382400] = {
ian@0 1234 .flags = FL_BASE1,
ian@0 1235 .num_ports = 8,
ian@0 1236 .base_baud = 1382400,
ian@0 1237 .uart_offset = 8,
ian@0 1238 },
ian@0 1239
ian@0 1240 [pbn_b2_1_115200] = {
ian@0 1241 .flags = FL_BASE2,
ian@0 1242 .num_ports = 1,
ian@0 1243 .base_baud = 115200,
ian@0 1244 .uart_offset = 8,
ian@0 1245 },
ian@0 1246 [pbn_b2_2_115200] = {
ian@0 1247 .flags = FL_BASE2,
ian@0 1248 .num_ports = 2,
ian@0 1249 .base_baud = 115200,
ian@0 1250 .uart_offset = 8,
ian@0 1251 },
ian@0 1252 [pbn_b2_8_115200] = {
ian@0 1253 .flags = FL_BASE2,
ian@0 1254 .num_ports = 8,
ian@0 1255 .base_baud = 115200,
ian@0 1256 .uart_offset = 8,
ian@0 1257 },
ian@0 1258
ian@0 1259 [pbn_b2_1_460800] = {
ian@0 1260 .flags = FL_BASE2,
ian@0 1261 .num_ports = 1,
ian@0 1262 .base_baud = 460800,
ian@0 1263 .uart_offset = 8,
ian@0 1264 },
ian@0 1265 [pbn_b2_4_460800] = {
ian@0 1266 .flags = FL_BASE2,
ian@0 1267 .num_ports = 4,
ian@0 1268 .base_baud = 460800,
ian@0 1269 .uart_offset = 8,
ian@0 1270 },
ian@0 1271 [pbn_b2_8_460800] = {
ian@0 1272 .flags = FL_BASE2,
ian@0 1273 .num_ports = 8,
ian@0 1274 .base_baud = 460800,
ian@0 1275 .uart_offset = 8,
ian@0 1276 },
ian@0 1277 [pbn_b2_16_460800] = {
ian@0 1278 .flags = FL_BASE2,
ian@0 1279 .num_ports = 16,
ian@0 1280 .base_baud = 460800,
ian@0 1281 .uart_offset = 8,
ian@0 1282 },
ian@0 1283
ian@0 1284 [pbn_b2_1_921600] = {
ian@0 1285 .flags = FL_BASE2,
ian@0 1286 .num_ports = 1,
ian@0 1287 .base_baud = 921600,
ian@0 1288 .uart_offset = 8,
ian@0 1289 },
ian@0 1290 [pbn_b2_4_921600] = {
ian@0 1291 .flags = FL_BASE2,
ian@0 1292 .num_ports = 4,
ian@0 1293 .base_baud = 921600,
ian@0 1294 .uart_offset = 8,
ian@0 1295 },
ian@0 1296 [pbn_b2_8_921600] = {
ian@0 1297 .flags = FL_BASE2,
ian@0 1298 .num_ports = 8,
ian@0 1299 .base_baud = 921600,
ian@0 1300 .uart_offset = 8,
ian@0 1301 },
ian@0 1302
ian@0 1303 [pbn_b2_bt_1_115200] = {
ian@0 1304 .flags = FL_BASE2|FL_BASE_BARS,
ian@0 1305 .num_ports = 1,
ian@0 1306 .base_baud = 115200,
ian@0 1307 .uart_offset = 8,
ian@0 1308 },
ian@0 1309 [pbn_b2_bt_2_115200] = {
ian@0 1310 .flags = FL_BASE2|FL_BASE_BARS,
ian@0 1311 .num_ports = 2,
ian@0 1312 .base_baud = 115200,
ian@0 1313 .uart_offset = 8,
ian@0 1314 },
ian@0 1315 [pbn_b2_bt_4_115200] = {
ian@0 1316 .flags = FL_BASE2|FL_BASE_BARS,
ian@0 1317 .num_ports = 4,
ian@0 1318 .base_baud = 115200,
ian@0 1319 .uart_offset = 8,
ian@0 1320 },
ian@0 1321
ian@0 1322 [pbn_b2_bt_2_921600] = {
ian@0 1323 .flags = FL_BASE2|FL_BASE_BARS,
ian@0 1324 .num_ports = 2,
ian@0 1325 .base_baud = 921600,
ian@0 1326 .uart_offset = 8,
ian@0 1327 },
ian@0 1328 [pbn_b2_bt_4_921600] = {
ian@0 1329 .flags = FL_BASE2|FL_BASE_BARS,
ian@0 1330 .num_ports = 4,
ian@0 1331 .base_baud = 921600,
ian@0 1332 .uart_offset = 8,
ian@0 1333 },
ian@0 1334
ian@0 1335 [pbn_b3_2_115200] = {
ian@0 1336 .flags = FL_BASE3,
ian@0 1337 .num_ports = 2,
ian@0 1338 .base_baud = 115200,
ian@0 1339 .uart_offset = 8,
ian@0 1340 },
ian@0 1341 [pbn_b3_4_115200] = {
ian@0 1342 .flags = FL_BASE3,
ian@0 1343 .num_ports = 4,
ian@0 1344 .base_baud = 115200,
ian@0 1345 .uart_offset = 8,
ian@0 1346 },
ian@0 1347 [pbn_b3_8_115200] = {
ian@0 1348 .flags = FL_BASE3,
ian@0 1349 .num_ports = 8,
ian@0 1350 .base_baud = 115200,
ian@0 1351 .uart_offset = 8,
ian@0 1352 },
ian@0 1353
ian@0 1354 /*
ian@0 1355 * Entries following this are board-specific.
ian@0 1356 */
ian@0 1357
ian@0 1358 /*
ian@0 1359 * Panacom - IOMEM
ian@0 1360 */
ian@0 1361 [pbn_panacom] = {
ian@0 1362 .flags = FL_BASE2,
ian@0 1363 .num_ports = 2,
ian@0 1364 .base_baud = 921600,
ian@0 1365 .uart_offset = 0x400,
ian@0 1366 .reg_shift = 7,
ian@0 1367 },
ian@0 1368 [pbn_panacom2] = {
ian@0 1369 .flags = FL_BASE2|FL_BASE_BARS,
ian@0 1370 .num_ports = 2,
ian@0 1371 .base_baud = 921600,
ian@0 1372 .uart_offset = 0x400,
ian@0 1373 .reg_shift = 7,
ian@0 1374 },
ian@0 1375 [pbn_panacom4] = {
ian@0 1376 .flags = FL_BASE2|FL_BASE_BARS,
ian@0 1377 .num_ports = 4,
ian@0 1378 .base_baud = 921600,
ian@0 1379 .uart_offset = 0x400,
ian@0 1380 .reg_shift = 7,
ian@0 1381 },
ian@0 1382
ian@0 1383 [pbn_exsys_4055] = {
ian@0 1384 .flags = FL_BASE2,
ian@0 1385 .num_ports = 4,
ian@0 1386 .base_baud = 115200,
ian@0 1387 .uart_offset = 8,
ian@0 1388 },
ian@0 1389
ian@0 1390 /* I think this entry is broken - the first_offset looks wrong --rmk */
ian@0 1391 [pbn_plx_romulus] = {
ian@0 1392 .flags = FL_BASE2,
ian@0 1393 .num_ports = 4,
ian@0 1394 .base_baud = 921600,
ian@0 1395 .uart_offset = 8 << 2,
ian@0 1396 .reg_shift = 2,
ian@0 1397 .first_offset = 0x03,
ian@0 1398 },
ian@0 1399
ian@0 1400 /*
ian@0 1401 * This board uses the size of PCI Base region 0 to
ian@0 1402 * signal now many ports are available
ian@0 1403 */
ian@0 1404 [pbn_oxsemi] = {
ian@0 1405 .flags = FL_BASE0|FL_REGION_SZ_CAP,
ian@0 1406 .num_ports = 32,
ian@0 1407 .base_baud = 115200,
ian@0 1408 .uart_offset = 8,
ian@0 1409 },
ian@0 1410
ian@0 1411 /*
ian@0 1412 * EKF addition for i960 Boards form EKF with serial port.
ian@0 1413 * Max 256 ports.
ian@0 1414 */
ian@0 1415 [pbn_intel_i960] = {
ian@0 1416 .flags = FL_BASE0,
ian@0 1417 .num_ports = 32,
ian@0 1418 .base_baud = 921600,
ian@0 1419 .uart_offset = 8 << 2,
ian@0 1420 .reg_shift = 2,
ian@0 1421 .first_offset = 0x10000,
ian@0 1422 },
ian@0 1423 [pbn_sgi_ioc3] = {
ian@0 1424 .flags = FL_BASE0|FL_NOIRQ,
ian@0 1425 .num_ports = 1,
ian@0 1426 .base_baud = 458333,
ian@0 1427 .uart_offset = 8,
ian@0 1428 .reg_shift = 0,
ian@0 1429 .first_offset = 0x20178,
ian@0 1430 },
ian@0 1431
ian@0 1432 /*
ian@0 1433 * NEC Vrc-5074 (Nile 4) builtin UART.
ian@0 1434 */
ian@0 1435 [pbn_nec_nile4] = {
ian@0 1436 .flags = FL_BASE0,
ian@0 1437 .num_ports = 1,
ian@0 1438 .base_baud = 520833,
ian@0 1439 .uart_offset = 8 << 3,
ian@0 1440 .reg_shift = 3,
ian@0 1441 .first_offset = 0x300,
ian@0 1442 },
ian@0 1443
ian@0 1444 /*
ian@0 1445 * Computone - uses IOMEM.
ian@0 1446 */
ian@0 1447 [pbn_computone_4] = {
ian@0 1448 .flags = FL_BASE0,
ian@0 1449 .num_ports = 4,
ian@0 1450 .base_baud = 921600,
ian@0 1451 .uart_offset = 0x40,
ian@0 1452 .reg_shift = 2,
ian@0 1453 .first_offset = 0x200,
ian@0 1454 },
ian@0 1455 [pbn_computone_6] = {
ian@0 1456 .flags = FL_BASE0,
ian@0 1457 .num_ports = 6,
ian@0 1458 .base_baud = 921600,
ian@0 1459 .uart_offset = 0x40,
ian@0 1460 .reg_shift = 2,
ian@0 1461 .first_offset = 0x200,
ian@0 1462 },
ian@0 1463 [pbn_computone_8] = {
ian@0 1464 .flags = FL_BASE0,
ian@0 1465 .num_ports = 8,
ian@0 1466 .base_baud = 921600,
ian@0 1467 .uart_offset = 0x40,
ian@0 1468 .reg_shift = 2,
ian@0 1469 .first_offset = 0x200,
ian@0 1470 },
ian@0 1471 [pbn_sbsxrsio] = {
ian@0 1472 .flags = FL_BASE0,
ian@0 1473 .num_ports = 8,
ian@0 1474 .base_baud = 460800,
ian@0 1475 .uart_offset = 256,
ian@0 1476 .reg_shift = 4,
ian@0 1477 },
ian@0 1478 /*
ian@0 1479 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
ian@0 1480 * Only basic 16550A support.
ian@0 1481 * XR17C15[24] are not tested, but they should work.
ian@0 1482 */
ian@0 1483 [pbn_exar_XR17C152] = {
ian@0 1484 .flags = FL_BASE0,
ian@0 1485 .num_ports = 2,
ian@0 1486 .base_baud = 921600,
ian@0 1487 .uart_offset = 0x200,
ian@0 1488 },
ian@0 1489 [pbn_exar_XR17C154] = {
ian@0 1490 .flags = FL_BASE0,
ian@0 1491 .num_ports = 4,
ian@0 1492 .base_baud = 921600,
ian@0 1493 .uart_offset = 0x200,
ian@0 1494 },
ian@0 1495 [pbn_exar_XR17C158] = {
ian@0 1496 .flags = FL_BASE0,
ian@0 1497 .num_ports = 8,
ian@0 1498 .base_baud = 921600,
ian@0 1499 .uart_offset = 0x200,
ian@0 1500 },
ian@0 1501 };
ian@0 1502
ian@0 1503 /*
ian@0 1504 * Given a complete unknown PCI device, try to use some heuristics to
ian@0 1505 * guess what the configuration might be, based on the pitiful PCI
ian@0 1506 * serial specs. Returns 0 on success, 1 on failure.
ian@0 1507 */
ian@0 1508 static int __devinit
ian@0 1509 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
ian@0 1510 {
ian@0 1511 int num_iomem, num_port, first_port = -1, i;
ian@0 1512
ian@0 1513 /*
ian@0 1514 * If it is not a communications device or the programming
ian@0 1515 * interface is greater than 6, give up.
ian@0 1516 *
ian@0 1517 * (Should we try to make guesses for multiport serial devices
ian@0 1518 * later?)
ian@0 1519 */
ian@0 1520 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
ian@0 1521 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
ian@0 1522 (dev->class & 0xff) > 6)
ian@0 1523 return -ENODEV;
ian@0 1524
ian@0 1525 num_iomem = num_port = 0;
ian@0 1526 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
ian@0 1527 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
ian@0 1528 num_port++;
ian@0 1529 if (first_port == -1)
ian@0 1530 first_port = i;
ian@0 1531 }
ian@0 1532 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
ian@0 1533 num_iomem++;
ian@0 1534 }
ian@0 1535
ian@0 1536 /*
ian@0 1537 * If there is 1 or 0 iomem regions, and exactly one port,
ian@0 1538 * use it. We guess the number of ports based on the IO
ian@0 1539 * region size.
ian@0 1540 */
ian@0 1541 if (num_iomem <= 1 && num_port == 1) {
ian@0 1542 board->flags = first_port;
ian@0 1543 board->num_ports = pci_resource_len(dev, first_port) / 8;
ian@0 1544 return 0;
ian@0 1545 }
ian@0 1546
ian@0 1547 /*
ian@0 1548 * Now guess if we've got a board which indexes by BARs.
ian@0 1549 * Each IO BAR should be 8 bytes, and they should follow
ian@0 1550 * consecutively.
ian@0 1551 */
ian@0 1552 first_port = -1;
ian@0 1553 num_port = 0;
ian@0 1554 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
ian@0 1555 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
ian@0 1556 pci_resource_len(dev, i) == 8 &&
ian@0 1557 (first_port == -1 || (first_port + num_port) == i)) {
ian@0 1558 num_port++;
ian@0 1559 if (first_port == -1)
ian@0 1560 first_port = i;
ian@0 1561 }
ian@0 1562 }
ian@0 1563
ian@0 1564 if (num_port > 1) {
ian@0 1565 board->flags = first_port | FL_BASE_BARS;
ian@0 1566 board->num_ports = num_port;
ian@0 1567 return 0;
ian@0 1568 }
ian@0 1569
ian@0 1570 return -ENODEV;
ian@0 1571 }
ian@0 1572
ian@0 1573 static inline int
ian@0 1574 serial_pci_matches(struct pciserial_board *board,
ian@0 1575 struct pciserial_board *guessed)
ian@0 1576 {
ian@0 1577 return
ian@0 1578 board->num_ports == guessed->num_ports &&
ian@0 1579 board->base_baud == guessed->base_baud &&
ian@0 1580 board->uart_offset == guessed->uart_offset &&
ian@0 1581 board->reg_shift == guessed->reg_shift &&
ian@0 1582 board->first_offset == guessed->first_offset;
ian@0 1583 }
ian@0 1584
ian@0 1585 struct serial_private *
ian@0 1586 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
ian@0 1587 {
ian@0 1588 struct uart_port serial_port;
ian@0 1589 struct serial_private *priv;
ian@0 1590 struct pci_serial_quirk *quirk;
ian@0 1591 int rc, nr_ports, i;
ian@0 1592
ian@0 1593 nr_ports = board->num_ports;
ian@0 1594
ian@0 1595 /*
ian@0 1596 * Find an init and setup quirks.
ian@0 1597 */
ian@0 1598 quirk = find_quirk(dev);
ian@0 1599
ian@0 1600 /*
ian@0 1601 * Run the new-style initialization function.
ian@0 1602 * The initialization function returns:
ian@0 1603 * <0 - error
ian@0 1604 * 0 - use board->num_ports
ian@0 1605 * >0 - number of ports
ian@0 1606 */
ian@0 1607 if (quirk->init) {
ian@0 1608 rc = quirk->init(dev);
ian@0 1609 if (rc < 0) {
ian@0 1610 priv = ERR_PTR(rc);
ian@0 1611 goto err_out;
ian@0 1612 }
ian@0 1613 if (rc)
ian@0 1614 nr_ports = rc;
ian@0 1615 }
ian@0 1616
ian@0 1617 priv = kmalloc(sizeof(struct serial_private) +
ian@0 1618 sizeof(unsigned int) * nr_ports,
ian@0 1619 GFP_KERNEL);
ian@0 1620 if (!priv) {
ian@0 1621 priv = ERR_PTR(-ENOMEM);
ian@0 1622 goto err_deinit;
ian@0 1623 }
ian@0 1624
ian@0 1625 memset(priv, 0, sizeof(struct serial_private) +
ian@0 1626 sizeof(unsigned int) * nr_ports);
ian@0 1627
ian@0 1628 priv->dev = dev;
ian@0 1629 priv->quirk = quirk;
ian@0 1630
ian@0 1631 memset(&serial_port, 0, sizeof(struct uart_port));
ian@0 1632 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
ian@0 1633 serial_port.uartclk = board->base_baud * 16;
ian@0 1634 serial_port.irq = get_pci_irq(dev, board);
ian@0 1635 serial_port.dev = &dev->dev;
ian@0 1636
ian@0 1637 for (i = 0; i < nr_ports; i++) {
ian@0 1638 if (quirk->setup(priv, board, &serial_port, i))
ian@0 1639 break;
ian@0 1640
ian@0 1641 #ifdef SERIAL_DEBUG_PCI
ian@0 1642 printk("Setup PCI port: port %x, irq %d, type %d\n",
ian@0 1643 serial_port.iobase, serial_port.irq, serial_port.iotype);
ian@0 1644 #endif
ian@0 1645
ian@0 1646 priv->line[i] = serial8250_register_port(&serial_port);
ian@0 1647 if (priv->line[i] < 0) {
ian@0 1648 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
ian@0 1649 break;
ian@0 1650 }
ian@0 1651 }
ian@0 1652
ian@0 1653 priv->nr = i;
ian@0 1654
ian@0 1655 return priv;
ian@0 1656
ian@0 1657 err_deinit:
ian@0 1658 if (quirk->exit)
ian@0 1659 quirk->exit(dev);
ian@0 1660 err_out:
ian@0 1661 return priv;
ian@0 1662 }
ian@0 1663 EXPORT_SYMBOL_GPL(pciserial_init_ports);
ian@0 1664
ian@0 1665 void pciserial_remove_ports(struct serial_private *priv)
ian@0 1666 {
ian@0 1667 struct pci_serial_quirk *quirk;
ian@0 1668 int i;
ian@0 1669
ian@0 1670 for (i = 0; i < priv->nr; i++)
ian@0 1671 serial8250_unregister_port(priv->line[i]);
ian@0 1672
ian@0 1673 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
ian@0 1674 if (priv->remapped_bar[i])
ian@0 1675 iounmap(priv->remapped_bar[i]);
ian@0 1676 priv->remapped_bar[i] = NULL;
ian@0 1677 }
ian@0 1678
ian@0 1679 /*
ian@0 1680 * Find the exit quirks.
ian@0 1681 */
ian@0 1682 quirk = find_quirk(priv->dev);
ian@0 1683 if (quirk->exit)
ian@0 1684 quirk->exit(priv->dev);
ian@0 1685
ian@0 1686 kfree(priv);
ian@0 1687 }
ian@0 1688 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
ian@0 1689
ian@0 1690 void pciserial_suspend_ports(struct serial_private *priv)
ian@0 1691 {
ian@0 1692 int i;
ian@0 1693
ian@0 1694 for (i = 0; i < priv->nr; i++)
ian@0 1695 if (priv->line[i] >= 0)
ian@0 1696 serial8250_suspend_port(priv->line[i]);
ian@0 1697 }
ian@0 1698 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
ian@0 1699
ian@0 1700 void pciserial_resume_ports(struct serial_private *priv)
ian@0 1701 {
ian@0 1702 int i;
ian@0 1703
ian@0 1704 /*
ian@0 1705 * Ensure that the board is correctly configured.
ian@0 1706 */
ian@0 1707 if (priv->quirk->init)
ian@0 1708 priv->quirk->init(priv->dev);
ian@0 1709
ian@0 1710 for (i = 0; i < priv->nr; i++)
ian@0 1711 if (priv->line[i] >= 0)
ian@0 1712 serial8250_resume_port(priv->line[i]);
ian@0 1713 }
ian@0 1714 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
ian@0 1715
ian@0 1716 /*
ian@0 1717 * Probe one serial board. Unfortunately, there is no rhyme nor reason
ian@0 1718 * to the arrangement of serial ports on a PCI card.
ian@0 1719 */
ian@0 1720 static int __devinit
ian@0 1721 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
ian@0 1722 {
ian@0 1723 struct serial_private *priv;
ian@0 1724 struct pciserial_board *board, tmp;
ian@0 1725 int rc;
ian@0 1726
ian@0 1727 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
ian@0 1728 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
ian@0 1729 ent->driver_data);
ian@0 1730 return -EINVAL;
ian@0 1731 }
ian@0 1732
ian@0 1733 board = &pci_boards[ent->driver_data];
ian@0 1734
ian@0 1735 rc = pci_enable_device(dev);
ian@0 1736 if (rc)
ian@0 1737 return rc;
ian@0 1738
ian@0 1739 if (ent->driver_data == pbn_default) {
ian@0 1740 /*
ian@0 1741 * Use a copy of the pci_board entry for this;
ian@0 1742 * avoid changing entries in the table.
ian@0 1743 */
ian@0 1744 memcpy(&tmp, board, sizeof(struct pciserial_board));
ian@0 1745 board = &tmp;
ian@0 1746
ian@0 1747 /*
ian@0 1748 * We matched one of our class entries. Try to
ian@0 1749 * determine the parameters of this board.
ian@0 1750 */
ian@0 1751 rc = serial_pci_guess_board(dev, board);
ian@0 1752 if (rc)
ian@0 1753 goto disable;
ian@0 1754 } else {
ian@0 1755 /*
ian@0 1756 * We matched an explicit entry. If we are able to
ian@0 1757 * detect this boards settings with our heuristic,
ian@0 1758 * then we no longer need this entry.
ian@0 1759 */
ian@0 1760 memcpy(&tmp, &pci_boards[pbn_default],
ian@0 1761 sizeof(struct pciserial_board));
ian@0 1762 rc = serial_pci_guess_board(dev, &tmp);
ian@0 1763 if (rc == 0 && serial_pci_matches(board, &tmp))
ian@0 1764 moan_device("Redundant entry in serial pci_table.",
ian@0 1765 dev);
ian@0 1766 }
ian@0 1767
ian@0 1768 priv = pciserial_init_ports(dev, board);
ian@0 1769 if (!IS_ERR(priv)) {
ian@0 1770 pci_set_drvdata(dev, priv);
ian@0 1771 return 0;
ian@0 1772 }
ian@0 1773
ian@0 1774 rc = PTR_ERR(priv);
ian@0 1775
ian@0 1776 disable:
ian@0 1777 pci_disable_device(dev);
ian@0 1778 return rc;
ian@0 1779 }
ian@0 1780
ian@0 1781 static void __devexit pciserial_remove_one(struct pci_dev *dev)
ian@0 1782 {
ian@0 1783 struct serial_private *priv = pci_get_drvdata(dev);
ian@0 1784
ian@0 1785 pci_set_drvdata(dev, NULL);
ian@0 1786
ian@0 1787 pciserial_remove_ports(priv);
ian@0 1788
ian@0 1789 pci_disable_device(dev);
ian@0 1790 }
ian@0 1791
ian@0 1792 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
ian@0 1793 {
ian@0 1794 struct serial_private *priv = pci_get_drvdata(dev);
ian@0 1795
ian@0 1796 if (priv)
ian@0 1797 pciserial_suspend_ports(priv);
ian@0 1798
ian@0 1799 pci_save_state(dev);
ian@0 1800 pci_set_power_state(dev, pci_choose_state(dev, state));
ian@0 1801 return 0;
ian@0 1802 }
ian@0 1803
ian@0 1804 static int pciserial_resume_one(struct pci_dev *dev)
ian@0 1805 {
ian@0 1806 struct serial_private *priv = pci_get_drvdata(dev);
ian@0 1807
ian@0 1808 pci_set_power_state(dev, PCI_D0);
ian@0 1809 pci_restore_state(dev);
ian@0 1810
ian@0 1811 if (priv) {
ian@0 1812 /*
ian@0 1813 * The device may have been disabled. Re-enable it.
ian@0 1814 */
ian@0 1815 pci_enable_device(dev);
ian@0 1816
ian@0 1817 pciserial_resume_ports(priv);
ian@0 1818 }
ian@0 1819 return 0;
ian@0 1820 }
ian@0 1821
ian@0 1822 static struct pci_device_id serial_pci_tbl[] = {
ian@0 1823 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
ian@0 1824 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1825 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
ian@0 1826 pbn_b1_8_1382400 },
ian@0 1827 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
ian@0 1828 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1829 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
ian@0 1830 pbn_b1_4_1382400 },
ian@0 1831 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
ian@0 1832 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1833 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
ian@0 1834 pbn_b1_2_1382400 },
ian@0 1835 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1836 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1837 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
ian@0 1838 pbn_b1_8_1382400 },
ian@0 1839 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1840 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1841 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
ian@0 1842 pbn_b1_4_1382400 },
ian@0 1843 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1844 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1845 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
ian@0 1846 pbn_b1_2_1382400 },
ian@0 1847 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1848 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1849 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
ian@0 1850 pbn_b1_8_921600 },
ian@0 1851 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1852 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1853 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
ian@0 1854 pbn_b1_8_921600 },
ian@0 1855 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1856 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1857 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
ian@0 1858 pbn_b1_4_921600 },
ian@0 1859 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1860 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1861 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
ian@0 1862 pbn_b1_4_921600 },
ian@0 1863 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1864 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1865 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
ian@0 1866 pbn_b1_2_921600 },
ian@0 1867 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1868 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1869 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
ian@0 1870 pbn_b1_8_921600 },
ian@0 1871 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1872 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1873 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
ian@0 1874 pbn_b1_8_921600 },
ian@0 1875 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1876 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1877 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
ian@0 1878 pbn_b1_4_921600 },
ian@0 1879 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
ian@0 1880 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1881 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
ian@0 1882 pbn_b1_2_1250000 },
ian@0 1883 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
ian@0 1884 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1885 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
ian@0 1886 pbn_b0_2_1843200 },
ian@0 1887 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
ian@0 1888 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1889 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
ian@0 1890 pbn_b0_4_1843200 },
ian@0 1891 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
ian@0 1892 PCI_VENDOR_ID_AFAVLAB,
ian@0 1893 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
ian@0 1894 pbn_b0_4_1152000 },
ian@0 1895 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
ian@0 1896 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1897 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
ian@0 1898 pbn_b0_2_1843200_200 },
ian@0 1899 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
ian@0 1900 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1901 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
ian@0 1902 pbn_b0_4_1843200_200 },
ian@0 1903 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
ian@0 1904 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1905 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
ian@0 1906 pbn_b0_8_1843200_200 },
ian@0 1907 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
ian@0 1908 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1909 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
ian@0 1910 pbn_b0_2_1843200_200 },
ian@0 1911 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
ian@0 1912 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1913 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
ian@0 1914 pbn_b0_4_1843200_200 },
ian@0 1915 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
ian@0 1916 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1917 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
ian@0 1918 pbn_b0_8_1843200_200 },
ian@0 1919 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
ian@0 1920 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1921 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
ian@0 1922 pbn_b0_2_1843200_200 },
ian@0 1923 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
ian@0 1924 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1925 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
ian@0 1926 pbn_b0_4_1843200_200 },
ian@0 1927 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
ian@0 1928 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1929 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
ian@0 1930 pbn_b0_8_1843200_200 },
ian@0 1931 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
ian@0 1932 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1933 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
ian@0 1934 pbn_b0_2_1843200_200 },
ian@0 1935 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
ian@0 1936 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1937 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
ian@0 1938 pbn_b0_4_1843200_200 },
ian@0 1939 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
ian@0 1940 PCI_SUBVENDOR_ID_CONNECT_TECH,
ian@0 1941 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
ian@0 1942 pbn_b0_8_1843200_200 },
ian@0 1943
ian@0 1944 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
ian@0 1945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1946 pbn_b2_bt_1_115200 },
ian@0 1947 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
ian@0 1948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1949 pbn_b2_bt_2_115200 },
ian@0 1950 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
ian@0 1951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1952 pbn_b2_bt_4_115200 },
ian@0 1953 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
ian@0 1954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1955 pbn_b2_bt_2_115200 },
ian@0 1956 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
ian@0 1957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1958 pbn_b2_bt_4_115200 },
ian@0 1959 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
ian@0 1960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1961 pbn_b2_8_115200 },
ian@0 1962 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
ian@0 1963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1964 pbn_b2_8_115200 },
ian@0 1965
ian@0 1966 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
ian@0 1967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1968 pbn_b2_bt_2_115200 },
ian@0 1969 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
ian@0 1970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1971 pbn_b2_bt_2_921600 },
ian@0 1972 /*
ian@0 1973 * VScom SPCOM800, from sl@s.pl
ian@0 1974 */
ian@0 1975 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
ian@0 1976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1977 pbn_b2_8_921600 },
ian@0 1978 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
ian@0 1979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1980 pbn_b2_4_921600 },
ian@0 1981 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 1982 PCI_SUBVENDOR_ID_KEYSPAN,
ian@0 1983 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
ian@0 1984 pbn_panacom },
ian@0 1985 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
ian@0 1986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1987 pbn_panacom4 },
ian@0 1988 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
ian@0 1989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 1990 pbn_panacom2 },
ian@0 1991 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 1992 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
ian@0 1993 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
ian@0 1994 pbn_b2_4_460800 },
ian@0 1995 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 1996 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
ian@0 1997 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
ian@0 1998 pbn_b2_8_460800 },
ian@0 1999 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 2000 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
ian@0 2001 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
ian@0 2002 pbn_b2_16_460800 },
ian@0 2003 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 2004 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
ian@0 2005 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
ian@0 2006 pbn_b2_16_460800 },
ian@0 2007 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 2008 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
ian@0 2009 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
ian@0 2010 pbn_b2_4_460800 },
ian@0 2011 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 2012 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
ian@0 2013 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
ian@0 2014 pbn_b2_8_460800 },
ian@0 2015 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
ian@0 2016 PCI_SUBVENDOR_ID_EXSYS,
ian@0 2017 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ian@0 2018 pbn_exsys_4055 },
ian@0 2019 /*
ian@0 2020 * Megawolf Romulus PCI Serial Card, from Mike Hudson
ian@0 2021 * (Exoray@isys.ca)
ian@0 2022 */
ian@0 2023 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
ian@0 2024 0x10b5, 0x106a, 0, 0,
ian@0 2025 pbn_plx_romulus },
ian@0 2026 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
ian@0 2027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2028 pbn_b1_4_115200 },
ian@0 2029 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
ian@0 2030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2031 pbn_b1_2_115200 },
ian@0 2032 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
ian@0 2033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2034 pbn_b1_8_115200 },
ian@0 2035 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
ian@0 2036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2037 pbn_b1_8_115200 },
ian@0 2038 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
ian@0 2039 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
ian@0 2040 pbn_b0_4_921600 },
ian@0 2041 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
ian@0 2042 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
ian@0 2043 pbn_b0_4_1152000 },
ian@0 2044
ian@0 2045 /*
ian@0 2046 * The below card is a little controversial since it is the
ian@0 2047 * subject of a PCI vendor/device ID clash. (See
ian@0 2048 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
ian@0 2049 * For now just used the hex ID 0x950a.
ian@0 2050 */
ian@0 2051 { PCI_VENDOR_ID_OXSEMI, 0x950a,
ian@0 2052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2053 pbn_b0_2_1130000 },
ian@0 2054 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
ian@0 2055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2056 pbn_b0_4_115200 },
ian@0 2057 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
ian@0 2058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2059 pbn_b0_bt_2_921600 },
ian@0 2060
ian@0 2061 /*
ian@0 2062 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
ian@0 2063 * from skokodyn@yahoo.com
ian@0 2064 */
ian@0 2065 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
ian@0 2066 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
ian@0 2067 pbn_sbsxrsio },
ian@0 2068 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
ian@0 2069 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
ian@0 2070 pbn_sbsxrsio },
ian@0 2071 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
ian@0 2072 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
ian@0 2073 pbn_sbsxrsio },
ian@0 2074 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
ian@0 2075 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
ian@0 2076 pbn_sbsxrsio },
ian@0 2077
ian@0 2078 /*
ian@0 2079 * Digitan DS560-558, from jimd@esoft.com
ian@0 2080 */
ian@0 2081 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
ian@0 2082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2083 pbn_b1_1_115200 },
ian@0 2084
ian@0 2085 /*
ian@0 2086 * Titan Electronic cards
ian@0 2087 * The 400L and 800L have a custom setup quirk.
ian@0 2088 */
ian@0 2089 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
ian@0 2090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2091 pbn_b0_1_921600 },
ian@0 2092 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
ian@0 2093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2094 pbn_b0_2_921600 },
ian@0 2095 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
ian@0 2096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2097 pbn_b0_4_921600 },
ian@0 2098 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
ian@0 2099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2100 pbn_b0_4_921600 },
ian@0 2101 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
ian@0 2102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2103 pbn_b1_1_921600 },
ian@0 2104 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
ian@0 2105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2106 pbn_b1_bt_2_921600 },
ian@0 2107 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
ian@0 2108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2109 pbn_b0_bt_4_921600 },
ian@0 2110 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
ian@0 2111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2112 pbn_b0_bt_8_921600 },
ian@0 2113
ian@0 2114 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
ian@0 2115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2116 pbn_b2_1_460800 },
ian@0 2117 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
ian@0 2118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2119 pbn_b2_1_460800 },
ian@0 2120 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
ian@0 2121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2122 pbn_b2_1_460800 },
ian@0 2123 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
ian@0 2124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2125 pbn_b2_bt_2_921600 },
ian@0 2126 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
ian@0 2127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2128 pbn_b2_bt_2_921600 },
ian@0 2129 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
ian@0 2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2131 pbn_b2_bt_2_921600 },
ian@0 2132 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
ian@0 2133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2134 pbn_b2_bt_4_921600 },
ian@0 2135 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
ian@0 2136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2137 pbn_b2_bt_4_921600 },
ian@0 2138 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
ian@0 2139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2140 pbn_b2_bt_4_921600 },
ian@0 2141 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
ian@0 2142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2143 pbn_b0_1_921600 },
ian@0 2144 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
ian@0 2145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2146 pbn_b0_1_921600 },
ian@0 2147 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
ian@0 2148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2149 pbn_b0_1_921600 },
ian@0 2150 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
ian@0 2151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2152 pbn_b0_bt_2_921600 },
ian@0 2153 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
ian@0 2154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2155 pbn_b0_bt_2_921600 },
ian@0 2156 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
ian@0 2157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2158 pbn_b0_bt_2_921600 },
ian@0 2159 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
ian@0 2160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2161 pbn_b0_bt_4_921600 },
ian@0 2162 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
ian@0 2163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2164 pbn_b0_bt_4_921600 },
ian@0 2165 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
ian@0 2166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2167 pbn_b0_bt_4_921600 },
ian@0 2168 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
ian@0 2169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2170 pbn_b0_bt_8_921600 },
ian@0 2171 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
ian@0 2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2173 pbn_b0_bt_8_921600 },
ian@0 2174 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
ian@0 2175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2176 pbn_b0_bt_8_921600 },
ian@0 2177
ian@0 2178 /*
ian@0 2179 * Computone devices submitted by Doug McNash dmcnash@computone.com
ian@0 2180 */
ian@0 2181 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
ian@0 2182 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
ian@0 2183 0, 0, pbn_computone_4 },
ian@0 2184 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
ian@0 2185 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
ian@0 2186 0, 0, pbn_computone_8 },
ian@0 2187 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
ian@0 2188 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
ian@0 2189 0, 0, pbn_computone_6 },
ian@0 2190
ian@0 2191 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
ian@0 2192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2193 pbn_oxsemi },
ian@0 2194 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
ian@0 2195 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
ian@0 2196 pbn_b0_bt_1_921600 },
ian@0 2197
ian@0 2198 /*
ian@0 2199 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
ian@0 2200 */
ian@0 2201 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
ian@0 2202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2203 pbn_b0_bt_8_115200 },
ian@0 2204 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
ian@0 2205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2206 pbn_b0_bt_8_115200 },
ian@0 2207
ian@0 2208 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
ian@0 2209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2210 pbn_b0_bt_2_115200 },
ian@0 2211 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
ian@0 2212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2213 pbn_b0_bt_2_115200 },
ian@0 2214 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
ian@0 2215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2216 pbn_b0_bt_2_115200 },
ian@0 2217 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
ian@0 2218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2219 pbn_b0_bt_4_460800 },
ian@0 2220 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
ian@0 2221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2222 pbn_b0_bt_4_460800 },
ian@0 2223 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
ian@0 2224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2225 pbn_b0_bt_2_460800 },
ian@0 2226 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
ian@0 2227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2228 pbn_b0_bt_2_460800 },
ian@0 2229 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
ian@0 2230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2231 pbn_b0_bt_2_460800 },
ian@0 2232 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
ian@0 2233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2234 pbn_b0_bt_1_115200 },
ian@0 2235 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
ian@0 2236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2237 pbn_b0_bt_1_460800 },
ian@0 2238
ian@0 2239 /*
ian@0 2240 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
ian@0 2241 */
ian@0 2242 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
ian@0 2243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2244 pbn_b1_1_1382400 },
ian@0 2245
ian@0 2246 /*
ian@0 2247 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
ian@0 2248 */
ian@0 2249 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
ian@0 2250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2251 pbn_b1_1_1382400 },
ian@0 2252
ian@0 2253 /*
ian@0 2254 * RAStel 2 port modem, gerg@moreton.com.au
ian@0 2255 */
ian@0 2256 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
ian@0 2257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2258 pbn_b2_bt_2_115200 },
ian@0 2259
ian@0 2260 /*
ian@0 2261 * EKF addition for i960 Boards form EKF with serial port
ian@0 2262 */
ian@0 2263 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
ian@0 2264 0xE4BF, PCI_ANY_ID, 0, 0,
ian@0 2265 pbn_intel_i960 },
ian@0 2266
ian@0 2267 /*
ian@0 2268 * Xircom Cardbus/Ethernet combos
ian@0 2269 */
ian@0 2270 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
ian@0 2271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2272 pbn_b0_1_115200 },
ian@0 2273 /*
ian@0 2274 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
ian@0 2275 */
ian@0 2276 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
ian@0 2277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2278 pbn_b0_1_115200 },
ian@0 2279
ian@0 2280 /*
ian@0 2281 * Untested PCI modems, sent in from various folks...
ian@0 2282 */
ian@0 2283
ian@0 2284 /*
ian@0 2285 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
ian@0 2286 */
ian@0 2287 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
ian@0 2288 0x1048, 0x1500, 0, 0,
ian@0 2289 pbn_b1_1_115200 },
ian@0 2290
ian@0 2291 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
ian@0 2292 0xFF00, 0, 0, 0,
ian@0 2293 pbn_sgi_ioc3 },
ian@0 2294
ian@0 2295 /*
ian@0 2296 * HP Diva card
ian@0 2297 */
ian@0 2298 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
ian@0 2299 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
ian@0 2300 pbn_b1_1_115200 },
ian@0 2301 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
ian@0 2302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2303 pbn_b0_5_115200 },
ian@0 2304 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
ian@0 2305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2306 pbn_b2_1_115200 },
ian@0 2307
ian@0 2308 /*
ian@0 2309 * NEC Vrc-5074 (Nile 4) builtin UART.
ian@0 2310 */
ian@0 2311 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
ian@0 2312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2313 pbn_nec_nile4 },
ian@0 2314
ian@0 2315 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
ian@0 2316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2317 pbn_b3_2_115200 },
ian@0 2318 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
ian@0 2319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2320 pbn_b3_4_115200 },
ian@0 2321 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
ian@0 2322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2323 pbn_b3_8_115200 },
ian@0 2324
ian@0 2325 /*
ian@0 2326 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
ian@0 2327 */
ian@0 2328 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
ian@0 2329 PCI_ANY_ID, PCI_ANY_ID,
ian@0 2330 0,
ian@0 2331 0, pbn_exar_XR17C152 },
ian@0 2332 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
ian@0 2333 PCI_ANY_ID, PCI_ANY_ID,
ian@0 2334 0,
ian@0 2335 0, pbn_exar_XR17C154 },
ian@0 2336 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
ian@0 2337 PCI_ANY_ID, PCI_ANY_ID,
ian@0 2338 0,
ian@0 2339 0, pbn_exar_XR17C158 },
ian@0 2340
ian@0 2341 /*
ian@0 2342 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
ian@0 2343 */
ian@0 2344 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
ian@0 2345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
ian@0 2346 pbn_b0_1_115200 },
ian@0 2347
ian@0 2348 /*
ian@0 2349 * IntaShield IS-200
ian@0 2350 */
ian@0 2351 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
ian@0 2352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
ian@0 2353 pbn_b2_2_115200 },
ian@0 2354
ian@0 2355 /*
ian@0 2356 * These entries match devices with class COMMUNICATION_SERIAL,
ian@0 2357 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
ian@0 2358 */
ian@0 2359 { PCI_ANY_ID, PCI_ANY_ID,
ian@0 2360 PCI_ANY_ID, PCI_ANY_ID,
ian@0 2361 PCI_CLASS_COMMUNICATION_SERIAL << 8,
ian@0 2362 0xffff00, pbn_default },
ian@0 2363 { PCI_ANY_ID, PCI_ANY_ID,
ian@0 2364 PCI_ANY_ID, PCI_ANY_ID,
ian@0 2365 PCI_CLASS_COMMUNICATION_MODEM << 8,
ian@0 2366 0xffff00, pbn_default },
ian@0 2367 { PCI_ANY_ID, PCI_ANY_ID,
ian@0 2368 PCI_ANY_ID, PCI_ANY_ID,
ian@0 2369 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
ian@0 2370 0xffff00, pbn_default },
ian@0 2371 { 0, }
ian@0 2372 };
ian@0 2373
ian@0 2374 static struct pci_driver serial_pci_driver = {
ian@0 2375 .name = "serial",
ian@0 2376 .probe = pciserial_init_one,
ian@0 2377 .remove = __devexit_p(pciserial_remove_one),
ian@0 2378 .suspend = pciserial_suspend_one,
ian@0 2379 .resume = pciserial_resume_one,
ian@0 2380 .id_table = serial_pci_tbl,
ian@0 2381 };
ian@0 2382
ian@0 2383 static int __init serial8250_pci_init(void)
ian@0 2384 {
ian@0 2385 return pci_register_driver(&serial_pci_driver);
ian@0 2386 }
ian@0 2387
ian@0 2388 static void __exit serial8250_pci_exit(void)
ian@0 2389 {
ian@0 2390 pci_unregister_driver(&serial_pci_driver);
ian@0 2391 }
ian@0 2392
ian@0 2393 module_init(serial8250_pci_init);
ian@0 2394 module_exit(serial8250_pci_exit);
ian@0 2395
ian@0 2396 MODULE_LICENSE("GPL");
ian@0 2397 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
ian@0 2398 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);