ia64/linux-2.6.18-xen.hg

annotate drivers/char/rio/rioboard.h @ 893:f994bfe9b93b

linux/blktap2: reduce TLB flush scope

c/s 885 added very coarse TLB flushing. Since these flushes always
follow single page updates, single page flushes (when available) are
sufficient.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 04 10:32:57 2009 +0100 (2009-06-04)
parents 831230e53067
children
rev   line source
ian@0 1 /************************************************************************/
ian@0 2 /* */
ian@0 3 /* Title : RIO Host Card Hardware Definitions */
ian@0 4 /* */
ian@0 5 /* Author : N.P.Vassallo */
ian@0 6 /* */
ian@0 7 /* Creation : 26th April 1999 */
ian@0 8 /* */
ian@0 9 /* Version : 1.0.0 */
ian@0 10 /* */
ian@0 11 /* Copyright : (c) Specialix International Ltd. 1999 *
ian@0 12 *
ian@0 13 * This program is free software; you can redistribute it and/or modify
ian@0 14 * it under the terms of the GNU General Public License as published by
ian@0 15 * the Free Software Foundation; either version 2 of the License, or
ian@0 16 * (at your option) any later version.
ian@0 17 *
ian@0 18 * This program is distributed in the hope that it will be useful,
ian@0 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
ian@0 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ian@0 21 * GNU General Public License for more details.
ian@0 22 *
ian@0 23 * You should have received a copy of the GNU General Public License
ian@0 24 * along with this program; if not, write to the Free Software
ian@0 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
ian@0 26 * */
ian@0 27 /* Description : Prototypes, structures and definitions */
ian@0 28 /* describing the RIO board hardware */
ian@0 29 /* */
ian@0 30 /************************************************************************/
ian@0 31
ian@0 32 /* History...
ian@0 33
ian@0 34 1.0.0 26/04/99 NPV Creation.
ian@0 35
ian@0 36 */
ian@0 37
ian@0 38 #ifndef _rioboard_h /* If RIOBOARD.H not already defined */
ian@0 39 #define _rioboard_h 1
ian@0 40
ian@0 41 /*****************************************************************************
ian@0 42 *********************** ***********************
ian@0 43 *********************** Hardware Control Registers ***********************
ian@0 44 *********************** ***********************
ian@0 45 *****************************************************************************/
ian@0 46
ian@0 47 /* Hardware Registers... */
ian@0 48
ian@0 49 #define RIO_REG_BASE 0x7C00 /* Base of control registers */
ian@0 50
ian@0 51 #define RIO_CONFIG RIO_REG_BASE + 0x0000 /* WRITE: Configuration Register */
ian@0 52 #define RIO_INTSET RIO_REG_BASE + 0x0080 /* WRITE: Interrupt Set */
ian@0 53 #define RIO_RESET RIO_REG_BASE + 0x0100 /* WRITE: Host Reset */
ian@0 54 #define RIO_INTRESET RIO_REG_BASE + 0x0180 /* WRITE: Interrupt Reset */
ian@0 55
ian@0 56 #define RIO_VPD_ROM RIO_REG_BASE + 0x0000 /* READ: Vital Product Data ROM */
ian@0 57 #define RIO_INTSTAT RIO_REG_BASE + 0x0080 /* READ: Interrupt Status (Jet boards only) */
ian@0 58 #define RIO_RESETSTAT RIO_REG_BASE + 0x0100 /* READ: Reset Status (Jet boards only) */
ian@0 59
ian@0 60 /* RIO_VPD_ROM definitions... */
ian@0 61 #define VPD_SLX_ID1 0x00 /* READ: Specialix Identifier #1 */
ian@0 62 #define VPD_SLX_ID2 0x01 /* READ: Specialix Identifier #2 */
ian@0 63 #define VPD_HW_REV 0x02 /* READ: Hardware Revision */
ian@0 64 #define VPD_HW_ASSEM 0x03 /* READ: Hardware Assembly Level */
ian@0 65 #define VPD_UNIQUEID4 0x04 /* READ: Unique Identifier #4 */
ian@0 66 #define VPD_UNIQUEID3 0x05 /* READ: Unique Identifier #3 */
ian@0 67 #define VPD_UNIQUEID2 0x06 /* READ: Unique Identifier #2 */
ian@0 68 #define VPD_UNIQUEID1 0x07 /* READ: Unique Identifier #1 */
ian@0 69 #define VPD_MANU_YEAR 0x08 /* READ: Year Of Manufacture (0 = 1970) */
ian@0 70 #define VPD_MANU_WEEK 0x09 /* READ: Week Of Manufacture (0 = week 1 Jan) */
ian@0 71 #define VPD_HWFEATURE1 0x0A /* READ: Hardware Feature Byte 1 */
ian@0 72 #define VPD_HWFEATURE2 0x0B /* READ: Hardware Feature Byte 2 */
ian@0 73 #define VPD_HWFEATURE3 0x0C /* READ: Hardware Feature Byte 3 */
ian@0 74 #define VPD_HWFEATURE4 0x0D /* READ: Hardware Feature Byte 4 */
ian@0 75 #define VPD_HWFEATURE5 0x0E /* READ: Hardware Feature Byte 5 */
ian@0 76 #define VPD_OEMID 0x0F /* READ: OEM Identifier */
ian@0 77 #define VPD_IDENT 0x10 /* READ: Identifier string (16 bytes) */
ian@0 78 #define VPD_IDENT_LEN 0x10
ian@0 79
ian@0 80 /* VPD ROM Definitions... */
ian@0 81 #define SLX_ID1 0x4D
ian@0 82 #define SLX_ID2 0x98
ian@0 83
ian@0 84 #define PRODUCT_ID(a) ((a>>4)&0xF) /* Use to obtain Product ID from VPD_UNIQUEID1 */
ian@0 85
ian@0 86 #define ID_SX_ISA 0x2
ian@0 87 #define ID_RIO_EISA 0x3
ian@0 88 #define ID_SX_PCI 0x5
ian@0 89 #define ID_SX_EISA 0x7
ian@0 90 #define ID_RIO_RTA16 0x9
ian@0 91 #define ID_RIO_ISA 0xA
ian@0 92 #define ID_RIO_MCA 0xB
ian@0 93 #define ID_RIO_SBUS 0xC
ian@0 94 #define ID_RIO_PCI 0xD
ian@0 95 #define ID_RIO_RTA8 0xE
ian@0 96
ian@0 97 /* Transputer bootstrap definitions... */
ian@0 98
ian@0 99 #define BOOTLOADADDR (0x8000 - 6)
ian@0 100 #define BOOTINDICATE (0x8000 - 2)
ian@0 101
ian@0 102 /* Firmware load position... */
ian@0 103
ian@0 104 #define FIRMWARELOADADDR 0x7C00 /* Firmware is loaded _before_ this address */
ian@0 105
ian@0 106 /*****************************************************************************
ian@0 107 ***************************** *****************************
ian@0 108 ***************************** RIO (Rev1) ISA *****************************
ian@0 109 ***************************** *****************************
ian@0 110 *****************************************************************************/
ian@0 111
ian@0 112 /* Control Register Definitions... */
ian@0 113 #define RIO_ISA_IDENT "JBJGPGGHINSMJPJR"
ian@0 114
ian@0 115 #define RIO_ISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
ian@0 116 #define RIO_ISA_CFG_BUSENABLE 0x02 /* Enable processor bus */
ian@0 117 #define RIO_ISA_CFG_IRQMASK 0x30 /* Interrupt mask */
ian@0 118 #define RIO_ISA_CFG_IRQ12 0x10 /* Interrupt Level 12 */
ian@0 119 #define RIO_ISA_CFG_IRQ11 0x20 /* Interrupt Level 11 */
ian@0 120 #define RIO_ISA_CFG_IRQ9 0x30 /* Interrupt Level 9 */
ian@0 121 #define RIO_ISA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
ian@0 122 #define RIO_ISA_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */
ian@0 123
ian@0 124 /*****************************************************************************
ian@0 125 ***************************** *****************************
ian@0 126 ***************************** RIO (Rev2) ISA *****************************
ian@0 127 ***************************** *****************************
ian@0 128 *****************************************************************************/
ian@0 129
ian@0 130 /* Control Register Definitions... */
ian@0 131 #define RIO_ISA2_IDENT "JBJGPGGHINSMJPJR"
ian@0 132
ian@0 133 #define RIO_ISA2_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
ian@0 134 #define RIO_ISA2_CFG_BUSENABLE 0x02 /* Enable processor bus */
ian@0 135 #define RIO_ISA2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
ian@0 136 #define RIO_ISA2_CFG_16BIT 0x08 /* 16bit mode, else 8bit */
ian@0 137 #define RIO_ISA2_CFG_IRQMASK 0x30 /* Interrupt mask */
ian@0 138 #define RIO_ISA2_CFG_IRQ15 0x00 /* Interrupt Level 15 */
ian@0 139 #define RIO_ISA2_CFG_IRQ12 0x10 /* Interrupt Level 12 */
ian@0 140 #define RIO_ISA2_CFG_IRQ11 0x20 /* Interrupt Level 11 */
ian@0 141 #define RIO_ISA2_CFG_IRQ9 0x30 /* Interrupt Level 9 */
ian@0 142 #define RIO_ISA2_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
ian@0 143 #define RIO_ISA2_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */
ian@0 144
ian@0 145 /*****************************************************************************
ian@0 146 ***************************** ******************************
ian@0 147 ***************************** RIO (Jet) ISA ******************************
ian@0 148 ***************************** ******************************
ian@0 149 *****************************************************************************/
ian@0 150
ian@0 151 /* Control Register Definitions... */
ian@0 152 #define RIO_ISA3_IDENT "JET HOST BY KEV#"
ian@0 153
ian@0 154 #define RIO_ISA3_CFG_BUSENABLE 0x02 /* Enable processor bus */
ian@0 155 #define RIO_ISA3_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
ian@0 156 #define RIO_ISA32_CFG_IRQMASK 0xF30 /* Interrupt mask */
ian@0 157 #define RIO_ISA3_CFG_IRQ15 0xF0 /* Interrupt Level 15 */
ian@0 158 #define RIO_ISA3_CFG_IRQ12 0xC0 /* Interrupt Level 12 */
ian@0 159 #define RIO_ISA3_CFG_IRQ11 0xB0 /* Interrupt Level 11 */
ian@0 160 #define RIO_ISA3_CFG_IRQ10 0xA0 /* Interrupt Level 10 */
ian@0 161 #define RIO_ISA3_CFG_IRQ9 0x90 /* Interrupt Level 9 */
ian@0 162
ian@0 163 /*****************************************************************************
ian@0 164 ********************************* ********************************
ian@0 165 ********************************* RIO MCA ********************************
ian@0 166 ********************************* ********************************
ian@0 167 *****************************************************************************/
ian@0 168
ian@0 169 /* Control Register Definitions... */
ian@0 170 #define RIO_MCA_IDENT "JBJGPGGHINSMJPJR"
ian@0 171
ian@0 172 #define RIO_MCA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
ian@0 173 #define RIO_MCA_CFG_BUSENABLE 0x02 /* Enable processor bus */
ian@0 174 #define RIO_MCA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
ian@0 175
ian@0 176 /*****************************************************************************
ian@0 177 ******************************** ********************************
ian@0 178 ******************************** RIO EISA ********************************
ian@0 179 ******************************** ********************************
ian@0 180 *****************************************************************************/
ian@0 181
ian@0 182 /* EISA Configuration Space Definitions... */
ian@0 183 #define EISA_PRODUCT_ID1 0xC80
ian@0 184 #define EISA_PRODUCT_ID2 0xC81
ian@0 185 #define EISA_PRODUCT_NUMBER 0xC82
ian@0 186 #define EISA_REVISION_NUMBER 0xC83
ian@0 187 #define EISA_CARD_ENABLE 0xC84
ian@0 188 #define EISA_VPD_UNIQUEID4 0xC88 /* READ: Unique Identifier #4 */
ian@0 189 #define EISA_VPD_UNIQUEID3 0xC8A /* READ: Unique Identifier #3 */
ian@0 190 #define EISA_VPD_UNIQUEID2 0xC90 /* READ: Unique Identifier #2 */
ian@0 191 #define EISA_VPD_UNIQUEID1 0xC92 /* READ: Unique Identifier #1 */
ian@0 192 #define EISA_VPD_MANU_YEAR 0xC98 /* READ: Year Of Manufacture (0 = 1970) */
ian@0 193 #define EISA_VPD_MANU_WEEK 0xC9A /* READ: Week Of Manufacture (0 = week 1 Jan) */
ian@0 194 #define EISA_MEM_ADDR_23_16 0xC00
ian@0 195 #define EISA_MEM_ADDR_31_24 0xC01
ian@0 196 #define EISA_RIO_CONFIG 0xC02 /* WRITE: Configuration Register */
ian@0 197 #define EISA_RIO_INTSET 0xC03 /* WRITE: Interrupt Set */
ian@0 198 #define EISA_RIO_INTRESET 0xC03 /* READ: Interrupt Reset */
ian@0 199
ian@0 200 /* Control Register Definitions... */
ian@0 201 #define RIO_EISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
ian@0 202 #define RIO_EISA_CFG_LINK20 0x02 /* 20Mbps link, else 10Mbps */
ian@0 203 #define RIO_EISA_CFG_BUSENABLE 0x04 /* Enable processor bus */
ian@0 204 #define RIO_EISA_CFG_PROCRUN 0x08 /* Processor running, else reset */
ian@0 205 #define RIO_EISA_CFG_IRQMASK 0xF0 /* Interrupt mask */
ian@0 206 #define RIO_EISA_CFG_IRQ15 0xF0 /* Interrupt Level 15 */
ian@0 207 #define RIO_EISA_CFG_IRQ14 0xE0 /* Interrupt Level 14 */
ian@0 208 #define RIO_EISA_CFG_IRQ12 0xC0 /* Interrupt Level 12 */
ian@0 209 #define RIO_EISA_CFG_IRQ11 0xB0 /* Interrupt Level 11 */
ian@0 210 #define RIO_EISA_CFG_IRQ10 0xA0 /* Interrupt Level 10 */
ian@0 211 #define RIO_EISA_CFG_IRQ9 0x90 /* Interrupt Level 9 */
ian@0 212 #define RIO_EISA_CFG_IRQ7 0x70 /* Interrupt Level 7 */
ian@0 213 #define RIO_EISA_CFG_IRQ6 0x60 /* Interrupt Level 6 */
ian@0 214 #define RIO_EISA_CFG_IRQ5 0x50 /* Interrupt Level 5 */
ian@0 215 #define RIO_EISA_CFG_IRQ4 0x40 /* Interrupt Level 4 */
ian@0 216 #define RIO_EISA_CFG_IRQ3 0x30 /* Interrupt Level 3 */
ian@0 217
ian@0 218 /*****************************************************************************
ian@0 219 ******************************** ********************************
ian@0 220 ******************************** RIO SBus ********************************
ian@0 221 ******************************** ********************************
ian@0 222 *****************************************************************************/
ian@0 223
ian@0 224 /* Control Register Definitions... */
ian@0 225 #define RIO_SBUS_IDENT "JBPGK#\0\0\0\0\0\0\0\0\0\0"
ian@0 226
ian@0 227 #define RIO_SBUS_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
ian@0 228 #define RIO_SBUS_CFG_BUSENABLE 0x02 /* Enable processor bus */
ian@0 229 #define RIO_SBUS_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
ian@0 230 #define RIO_SBUS_CFG_IRQMASK 0x38 /* Interrupt mask */
ian@0 231 #define RIO_SBUS_CFG_IRQNONE 0x00 /* No Interrupt */
ian@0 232 #define RIO_SBUS_CFG_IRQ7 0x38 /* Interrupt Level 7 */
ian@0 233 #define RIO_SBUS_CFG_IRQ6 0x30 /* Interrupt Level 6 */
ian@0 234 #define RIO_SBUS_CFG_IRQ5 0x28 /* Interrupt Level 5 */
ian@0 235 #define RIO_SBUS_CFG_IRQ4 0x20 /* Interrupt Level 4 */
ian@0 236 #define RIO_SBUS_CFG_IRQ3 0x18 /* Interrupt Level 3 */
ian@0 237 #define RIO_SBUS_CFG_IRQ2 0x10 /* Interrupt Level 2 */
ian@0 238 #define RIO_SBUS_CFG_IRQ1 0x08 /* Interrupt Level 1 */
ian@0 239 #define RIO_SBUS_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
ian@0 240 #define RIO_SBUS_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */
ian@0 241
ian@0 242 /*****************************************************************************
ian@0 243 ********************************* ********************************
ian@0 244 ********************************* RIO PCI ********************************
ian@0 245 ********************************* ********************************
ian@0 246 *****************************************************************************/
ian@0 247
ian@0 248 /* Control Register Definitions... */
ian@0 249 #define RIO_PCI_IDENT "ECDDPGJGJHJRGSK#"
ian@0 250
ian@0 251 #define RIO_PCI_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */
ian@0 252 #define RIO_PCI_CFG_BUSENABLE 0x02 /* Enable processor bus */
ian@0 253 #define RIO_PCI_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
ian@0 254 #define RIO_PCI_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */
ian@0 255 #define RIO_PCI_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */
ian@0 256
ian@0 257 /* PCI Definitions... */
ian@0 258 #define SPX_VENDOR_ID 0x11CB /* Assigned by the PCI SIG */
ian@0 259 #define SPX_DEVICE_ID 0x8000 /* RIO bridge boards */
ian@0 260 #define SPX_PLXDEVICE_ID 0x2000 /* PLX bridge boards */
ian@0 261 #define SPX_SUB_VENDOR_ID SPX_VENDOR_ID /* Same as vendor id */
ian@0 262 #define RIO_SUB_SYS_ID 0x0800 /* RIO PCI board */
ian@0 263
ian@0 264 /*****************************************************************************
ian@0 265 ***************************** ******************************
ian@0 266 ***************************** RIO (Jet) PCI ******************************
ian@0 267 ***************************** ******************************
ian@0 268 *****************************************************************************/
ian@0 269
ian@0 270 /* Control Register Definitions... */
ian@0 271 #define RIO_PCI2_IDENT "JET HOST BY KEV#"
ian@0 272
ian@0 273 #define RIO_PCI2_CFG_BUSENABLE 0x02 /* Enable processor bus */
ian@0 274 #define RIO_PCI2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */
ian@0 275
ian@0 276 /* PCI Definitions... */
ian@0 277 #define RIO2_SUB_SYS_ID 0x0100 /* RIO (Jet) PCI board */
ian@0 278
ian@0 279 #endif /*_rioboard_h */
ian@0 280
ian@0 281 /* End of RIOBOARD.H */