ia64/linux-2.6.18-xen.hg

annotate drivers/net/hp100.h @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * hp100.h: Hewlett Packard HP10/100VG ANY LAN ethernet driver for Linux.
ian@0 3 *
ian@0 4 * $Id: hp100.h,v 1.51 1997/04/08 14:26:42 floeff Exp floeff $
ian@0 5 *
ian@0 6 * Authors: Jaroslav Kysela, <perex@pf.jcu.cz>
ian@0 7 * Siegfried Loeffler <floeff@tunix.mathematik.uni-stuttgart.de>
ian@0 8 *
ian@0 9 * This driver is based on the 'hpfepkt' crynwr packet driver.
ian@0 10 *
ian@0 11 * This source/code is public free; you can distribute it and/or modify
ian@0 12 * it under terms of the GNU General Public License (published by the
ian@0 13 * Free Software Foundation) either version two of this License, or any
ian@0 14 * later version.
ian@0 15 */
ian@0 16
ian@0 17 /****************************************************************************
ian@0 18 * Hardware Constants
ian@0 19 ****************************************************************************/
ian@0 20
ian@0 21 /*
ian@0 22 * Page Identifiers
ian@0 23 * (Swap Paging Register, PAGING, bits 3:0, Offset 0x02)
ian@0 24 */
ian@0 25
ian@0 26 #define HP100_PAGE_PERFORMANCE 0x0 /* Page 0 */
ian@0 27 #define HP100_PAGE_MAC_ADDRESS 0x1 /* Page 1 */
ian@0 28 #define HP100_PAGE_HW_MAP 0x2 /* Page 2 */
ian@0 29 #define HP100_PAGE_EEPROM_CTRL 0x3 /* Page 3 */
ian@0 30 #define HP100_PAGE_MAC_CTRL 0x4 /* Page 4 */
ian@0 31 #define HP100_PAGE_MMU_CFG 0x5 /* Page 5 */
ian@0 32 #define HP100_PAGE_ID_MAC_ADDR 0x6 /* Page 6 */
ian@0 33 #define HP100_PAGE_MMU_POINTER 0x7 /* Page 7 */
ian@0 34
ian@0 35
ian@0 36 /* Registers that are present on all pages */
ian@0 37
ian@0 38 #define HP100_REG_HW_ID 0x00 /* R: (16) Unique card ID */
ian@0 39 #define HP100_REG_TRACE 0x00 /* W: (16) Used for debug output */
ian@0 40 #define HP100_REG_PAGING 0x02 /* R: (16),15:4 Card ID */
ian@0 41 /* W: (16),3:0 Switch pages */
ian@0 42 #define HP100_REG_OPTION_LSW 0x04 /* RW: (16) Select card functions */
ian@0 43 #define HP100_REG_OPTION_MSW 0x06 /* RW: (16) Select card functions */
ian@0 44
ian@0 45 /* Page 0 - Performance */
ian@0 46
ian@0 47 #define HP100_REG_IRQ_STATUS 0x08 /* RW: (16) Which ints are pending */
ian@0 48 #define HP100_REG_IRQ_MASK 0x0a /* RW: (16) Select ints to allow */
ian@0 49 #define HP100_REG_FRAGMENT_LEN 0x0c /* W: (16)12:0 Current fragment len */
ian@0 50 /* Note: For 32 bit systems, fragment len and offset registers are available */
ian@0 51 /* at offset 0x28 and 0x2c, where they can be written as 32bit values. */
ian@0 52 #define HP100_REG_OFFSET 0x0e /* RW: (16)12:0 Offset to start read */
ian@0 53 #define HP100_REG_DATA32 0x10 /* RW: (32) I/O mode data port */
ian@0 54 #define HP100_REG_DATA16 0x12 /* RW: WORDs must be read from here */
ian@0 55 #define HP100_REG_TX_MEM_FREE 0x14 /* RD: (32) Amount of free Tx mem */
ian@0 56 #define HP100_REG_TX_PDA_L 0x14 /* W: (32) BM: Ptr to PDL, Low Pri */
ian@0 57 #define HP100_REG_TX_PDA_H 0x1c /* W: (32) BM: Ptr to PDL, High Pri */
ian@0 58 #define HP100_REG_RX_PKT_CNT 0x18 /* RD: (8) Rx count of pkts on card */
ian@0 59 #define HP100_REG_TX_PKT_CNT 0x19 /* RD: (8) Tx count of pkts on card */
ian@0 60 #define HP100_REG_RX_PDL 0x1a /* R: (8) BM: # rx pdl not executed */
ian@0 61 #define HP100_REG_TX_PDL 0x1b /* R: (8) BM: # tx pdl not executed */
ian@0 62 #define HP100_REG_RX_PDA 0x18 /* W: (32) BM: Up to 31 addresses */
ian@0 63 /* which point to a PDL */
ian@0 64 #define HP100_REG_SL_EARLY 0x1c /* (32) Enhanced Slave Early Rx */
ian@0 65 #define HP100_REG_STAT_DROPPED 0x20 /* R (12) Dropped Packet Counter */
ian@0 66 #define HP100_REG_STAT_ERRORED 0x22 /* R (8) Errored Packet Counter */
ian@0 67 #define HP100_REG_STAT_ABORT 0x23 /* R (8) Abort Counter/OW Coll. Flag */
ian@0 68 #define HP100_REG_RX_RING 0x24 /* W (32) Slave: RX Ring Pointers */
ian@0 69 #define HP100_REG_32_FRAGMENT_LEN 0x28 /* W (13) Slave: Fragment Length Reg */
ian@0 70 #define HP100_REG_32_OFFSET 0x2c /* W (16) Slave: Offset Register */
ian@0 71
ian@0 72 /* Page 1 - MAC Address/Hash Table */
ian@0 73
ian@0 74 #define HP100_REG_MAC_ADDR 0x08 /* RW: (8) Cards MAC address */
ian@0 75 #define HP100_REG_HASH_BYTE0 0x10 /* RW: (8) Cards multicast filter */
ian@0 76
ian@0 77 /* Page 2 - Hardware Mapping */
ian@0 78
ian@0 79 #define HP100_REG_MEM_MAP_LSW 0x08 /* RW: (16) LSW of cards mem addr */
ian@0 80 #define HP100_REG_MEM_MAP_MSW 0x0a /* RW: (16) MSW of cards mem addr */
ian@0 81 #define HP100_REG_IO_MAP 0x0c /* RW: (8) Cards I/O address */
ian@0 82 #define HP100_REG_IRQ_CHANNEL 0x0d /* RW: (8) IRQ and edge/level int */
ian@0 83 #define HP100_REG_SRAM 0x0e /* RW: (8) How much RAM on card */
ian@0 84 #define HP100_REG_BM 0x0f /* RW: (8) Controls BM functions */
ian@0 85
ian@0 86 /* New on Page 2 for ETR chips: */
ian@0 87 #define HP100_REG_MODECTRL1 0x10 /* RW: (8) Mode Control 1 */
ian@0 88 #define HP100_REG_MODECTRL2 0x11 /* RW: (8) Mode Control 2 */
ian@0 89 #define HP100_REG_PCICTRL1 0x12 /* RW: (8) PCI Cfg 1 */
ian@0 90 #define HP100_REG_PCICTRL2 0x13 /* RW: (8) PCI Cfg 2 */
ian@0 91 #define HP100_REG_PCIBUSMLAT 0x15 /* RW: (8) PCI Bus Master Latency */
ian@0 92 #define HP100_REG_EARLYTXCFG 0x16 /* RW: (16) Early TX Cfg/Cntrl Reg */
ian@0 93 #define HP100_REG_EARLYRXCFG 0x18 /* RW: (8) Early RX Cfg/Cntrl Reg */
ian@0 94 #define HP100_REG_ISAPNPCFG1 0x1a /* RW: (8) ISA PnP Cfg/Cntrl Reg 1 */
ian@0 95 #define HP100_REG_ISAPNPCFG2 0x1b /* RW: (8) ISA PnP Cfg/Cntrl Reg 2 */
ian@0 96
ian@0 97 /* Page 3 - EEPROM/Boot ROM */
ian@0 98
ian@0 99 #define HP100_REG_EEPROM_CTRL 0x08 /* RW: (16) Used to load EEPROM */
ian@0 100 #define HP100_REG_BOOTROM_CTRL 0x0a
ian@0 101
ian@0 102 /* Page 4 - LAN Configuration (MAC_CTRL) */
ian@0 103
ian@0 104 #define HP100_REG_10_LAN_CFG_1 0x08 /* RW: (8) Set 10M XCVR functions */
ian@0 105 #define HP100_REG_10_LAN_CFG_2 0x09 /* RW: (8) 10M XCVR functions */
ian@0 106 #define HP100_REG_VG_LAN_CFG_1 0x0a /* RW: (8) Set 100M XCVR functions */
ian@0 107 #define HP100_REG_VG_LAN_CFG_2 0x0b /* RW: (8) 100M LAN Training cfgregs */
ian@0 108 #define HP100_REG_MAC_CFG_1 0x0c /* RW: (8) Types of pkts to accept */
ian@0 109 #define HP100_REG_MAC_CFG_2 0x0d /* RW: (8) Misc MAC functions */
ian@0 110 #define HP100_REG_MAC_CFG_3 0x0e /* RW: (8) Misc MAC functions */
ian@0 111 #define HP100_REG_MAC_CFG_4 0x0f /* R: (8) Misc MAC states */
ian@0 112 #define HP100_REG_DROPPED 0x10 /* R: (16),11:0 Pkts cant fit in mem */
ian@0 113 #define HP100_REG_CRC 0x12 /* R: (8) Pkts with CRC */
ian@0 114 #define HP100_REG_ABORT 0x13 /* R: (8) Aborted Tx pkts */
ian@0 115 #define HP100_REG_TRAIN_REQUEST 0x14 /* RW: (16) Endnode MAC register. */
ian@0 116 #define HP100_REG_TRAIN_ALLOW 0x16 /* R: (16) Hub allowed register */
ian@0 117
ian@0 118 /* Page 5 - MMU */
ian@0 119
ian@0 120 #define HP100_REG_RX_MEM_STOP 0x0c /* RW: (16) End of Rx ring addr */
ian@0 121 #define HP100_REG_TX_MEM_STOP 0x0e /* RW: (16) End of Tx ring addr */
ian@0 122 #define HP100_REG_PDL_MEM_STOP 0x10 /* Not used by 802.12 devices */
ian@0 123 #define HP100_REG_ECB_MEM_STOP 0x14 /* I've no idea what this is */
ian@0 124
ian@0 125 /* Page 6 - Card ID/Physical LAN Address */
ian@0 126
ian@0 127 #define HP100_REG_BOARD_ID 0x08 /* R: (8) EISA/ISA card ID */
ian@0 128 #define HP100_REG_BOARD_IO_CHCK 0x0c /* R: (8) Added to ID to get FFh */
ian@0 129 #define HP100_REG_SOFT_MODEL 0x0d /* R: (8) Config program defined */
ian@0 130 #define HP100_REG_LAN_ADDR 0x10 /* R: (8) MAC addr of card */
ian@0 131 #define HP100_REG_LAN_ADDR_CHCK 0x16 /* R: (8) Added to addr to get FFh */
ian@0 132
ian@0 133 /* Page 7 - MMU Current Pointers */
ian@0 134
ian@0 135 #define HP100_REG_PTR_RXSTART 0x08 /* R: (16) Current begin of Rx ring */
ian@0 136 #define HP100_REG_PTR_RXEND 0x0a /* R: (16) Current end of Rx ring */
ian@0 137 #define HP100_REG_PTR_TXSTART 0x0c /* R: (16) Current begin of Tx ring */
ian@0 138 #define HP100_REG_PTR_TXEND 0x0e /* R: (16) Current end of Rx ring */
ian@0 139 #define HP100_REG_PTR_RPDLSTART 0x10
ian@0 140 #define HP100_REG_PTR_RPDLEND 0x12
ian@0 141 #define HP100_REG_PTR_RINGPTRS 0x14
ian@0 142 #define HP100_REG_PTR_MEMDEBUG 0x1a
ian@0 143 /* ------------------------------------------------------------------------ */
ian@0 144
ian@0 145
ian@0 146 /*
ian@0 147 * Hardware ID Register I (Always available, HW_ID, Offset 0x00)
ian@0 148 */
ian@0 149 #define HP100_HW_ID_CASCADE 0x4850 /* Identifies Cascade Chip */
ian@0 150
ian@0 151 /*
ian@0 152 * Hardware ID Register 2 & Paging Register
ian@0 153 * (Always available, PAGING, Offset 0x02)
ian@0 154 * Bits 15:4 are for the Chip ID
ian@0 155 */
ian@0 156 #define HP100_CHIPID_MASK 0xFFF0
ian@0 157 #define HP100_CHIPID_SHASTA 0x5350 /* Not 802.12 compliant */
ian@0 158 /* EISA BM/SL, MCA16/32 SL, ISA SL */
ian@0 159 #define HP100_CHIPID_RAINIER 0x5360 /* Not 802.12 compliant EISA BM, */
ian@0 160 /* PCI SL, MCA16/32 SL, ISA SL */
ian@0 161 #define HP100_CHIPID_LASSEN 0x5370 /* 802.12 compliant PCI BM, PCI SL */
ian@0 162 /* LRF supported */
ian@0 163
ian@0 164 /*
ian@0 165 * Option Registers I and II
ian@0 166 * (Always available, OPTION_LSW, Offset 0x04-0x05)
ian@0 167 */
ian@0 168 #define HP100_DEBUG_EN 0x8000 /* 0:Dis., 1:Enable Debug Dump Ptr. */
ian@0 169 #define HP100_RX_HDR 0x4000 /* 0:Dis., 1:Enable putting pkt into */
ian@0 170 /* system mem. before Rx interrupt */
ian@0 171 #define HP100_MMAP_DIS 0x2000 /* 0:Enable, 1:Disable mem.mapping. */
ian@0 172 /* MMAP_DIS must be 0 and MEM_EN */
ian@0 173 /* must be 1 for memory-mapped */
ian@0 174 /* mode to be enabled */
ian@0 175 #define HP100_EE_EN 0x1000 /* 0:Disable,1:Enable EEPROM writing */
ian@0 176 #define HP100_BM_WRITE 0x0800 /* 0:Slave, 1:Bus Master for Tx data */
ian@0 177 #define HP100_BM_READ 0x0400 /* 0:Slave, 1:Bus Master for Rx data */
ian@0 178 #define HP100_TRI_INT 0x0200 /* 0:Don't, 1:Do tri-state the int */
ian@0 179 #define HP100_MEM_EN 0x0040 /* Config program set this to */
ian@0 180 /* 0:Disable, 1:Enable mem map. */
ian@0 181 /* See MMAP_DIS. */
ian@0 182 #define HP100_IO_EN 0x0020 /* 1:Enable I/O transfers */
ian@0 183 #define HP100_BOOT_EN 0x0010 /* 1:Enable boot ROM access */
ian@0 184 #define HP100_FAKE_INT 0x0008 /* 1:int */
ian@0 185 #define HP100_INT_EN 0x0004 /* 1:Enable ints from card */
ian@0 186 #define HP100_HW_RST 0x0002 /* 0:Reset, 1:Out of reset */
ian@0 187 /* NIC reset on 0 to 1 transition */
ian@0 188
ian@0 189 /*
ian@0 190 * Option Register III
ian@0 191 * (Always available, OPTION_MSW, Offset 0x06)
ian@0 192 */
ian@0 193 #define HP100_PRIORITY_TX 0x0080 /* 1:Do all Tx pkts as priority */
ian@0 194 #define HP100_EE_LOAD 0x0040 /* 1:EEPROM loading, 0 when done */
ian@0 195 #define HP100_ADV_NXT_PKT 0x0004 /* 1:Advance to next pkt in Rx queue */
ian@0 196 /* h/w will set to 0 when done */
ian@0 197 #define HP100_TX_CMD 0x0002 /* 1:Tell h/w download done, h/w */
ian@0 198 /* will set to 0 when done */
ian@0 199
ian@0 200 /*
ian@0 201 * Interrupt Status Registers I and II
ian@0 202 * (Page PERFORMANCE, IRQ_STATUS, Offset 0x08-0x09)
ian@0 203 * Note: With old chips, these Registers will clear when 1 is written to them
ian@0 204 * with new chips this depends on setting of CLR_ISMODE
ian@0 205 */
ian@0 206 #define HP100_RX_EARLY_INT 0x2000
ian@0 207 #define HP100_RX_PDA_ZERO 0x1000
ian@0 208 #define HP100_RX_PDL_FILL_COMPL 0x0800
ian@0 209 #define HP100_RX_PACKET 0x0400 /* 0:No, 1:Yes pkt has been Rx */
ian@0 210 #define HP100_RX_ERROR 0x0200 /* 0:No, 1:Yes Rx pkt had error */
ian@0 211 #define HP100_TX_PDA_ZERO 0x0020 /* 1 when PDA count goes to zero */
ian@0 212 #define HP100_TX_SPACE_AVAIL 0x0010 /* 0:<8192, 1:>=8192 Tx free bytes */
ian@0 213 #define HP100_TX_COMPLETE 0x0008 /* 0:No, 1:Yes a Tx has completed */
ian@0 214 #define HP100_MISC_ERROR 0x0004 /* 0:No, 1:Lan Link down or bus error */
ian@0 215 #define HP100_TX_ERROR 0x0002 /* 0:No, 1:Yes Tx pkt had error */
ian@0 216
ian@0 217 /*
ian@0 218 * Xmit Memory Free Count
ian@0 219 * (Page PERFORMANCE, TX_MEM_FREE, Offset 0x14) (Read only, 32bit)
ian@0 220 */
ian@0 221 #define HP100_AUTO_COMPARE 0x80000000 /* Tx Space avail & pkts<255 */
ian@0 222 #define HP100_FREE_SPACE 0x7fffffe0 /* Tx free memory */
ian@0 223
ian@0 224 /*
ian@0 225 * IRQ Channel
ian@0 226 * (Page HW_MAP, IRQ_CHANNEL, Offset 0x0d)
ian@0 227 */
ian@0 228 #define HP100_ZERO_WAIT_EN 0x80 /* 0:No, 1:Yes asserts NOWS signal */
ian@0 229 #define HP100_IRQ_SCRAMBLE 0x40
ian@0 230 #define HP100_BOND_HP 0x20
ian@0 231 #define HP100_LEVEL_IRQ 0x10 /* 0:Edge, 1:Level type interrupts. */
ian@0 232 /* (Only valid on EISA cards) */
ian@0 233 #define HP100_IRQMASK 0x0F /* Isolate the IRQ bits */
ian@0 234
ian@0 235 /*
ian@0 236 * SRAM Parameters
ian@0 237 * (Page HW_MAP, SRAM, Offset 0x0e)
ian@0 238 */
ian@0 239 #define HP100_RAM_SIZE_MASK 0xe0 /* AND to get SRAM size index */
ian@0 240 #define HP100_RAM_SIZE_SHIFT 0x05 /* Shift count(put index in lwr bits) */
ian@0 241
ian@0 242 /*
ian@0 243 * Bus Master Register
ian@0 244 * (Page HW_MAP, BM, Offset 0x0f)
ian@0 245 */
ian@0 246 #define HP100_BM_BURST_RD 0x01 /* EISA only: 1=Use burst trans. fm system */
ian@0 247 /* memory to chip (tx) */
ian@0 248 #define HP100_BM_BURST_WR 0x02 /* EISA only: 1=Use burst trans. fm system */
ian@0 249 /* memory to chip (rx) */
ian@0 250 #define HP100_BM_MASTER 0x04 /* 0:Slave, 1:BM mode */
ian@0 251 #define HP100_BM_PAGE_CK 0x08 /* This bit should be set whenever in */
ian@0 252 /* an EISA system */
ian@0 253 #define HP100_BM_PCI_8CLK 0x40 /* ... cycles 8 clocks apart */
ian@0 254
ian@0 255
ian@0 256 /*
ian@0 257 * Mode Control Register I
ian@0 258 * (Page HW_MAP, MODECTRL1, Offset0x10)
ian@0 259 */
ian@0 260 #define HP100_TX_DUALQ 0x10
ian@0 261 /* If set and BM -> dual tx pda queues */
ian@0 262 #define HP100_ISR_CLRMODE 0x02 /* If set ISR will clear all pending */
ian@0 263 /* interrupts on read (etr only?) */
ian@0 264 #define HP100_EE_NOLOAD 0x04 /* Status whether res will be loaded */
ian@0 265 /* from the eeprom */
ian@0 266 #define HP100_TX_CNT_FLG 0x08 /* Controls Early TX Reg Cnt Field */
ian@0 267 #define HP100_PDL_USE3 0x10 /* If set BM engine will read only */
ian@0 268 /* first three data elements of a PDL */
ian@0 269 /* on the first access. */
ian@0 270 #define HP100_BUSTYPE_MASK 0xe0 /* Three bit bus type info */
ian@0 271
ian@0 272 /*
ian@0 273 * Mode Control Register II
ian@0 274 * (Page HW_MAP, MODECTRL2, Offset0x11)
ian@0 275 */
ian@0 276 #define HP100_EE_MASK 0x0f /* Tell EEPROM circuit not to load */
ian@0 277 /* certain resources */
ian@0 278 #define HP100_DIS_CANCEL 0x20 /* For tx dualq mode operation */
ian@0 279 #define HP100_EN_PDL_WB 0x40 /* 1: Status of PDL completion may be */
ian@0 280 /* written back to system mem */
ian@0 281 #define HP100_EN_BUS_FAIL 0x80 /* Enables bus-fail portion of misc */
ian@0 282 /* interrupt */
ian@0 283
ian@0 284 /*
ian@0 285 * PCI Configuration and Control Register I
ian@0 286 * (Page HW_MAP, PCICTRL1, Offset 0x12)
ian@0 287 */
ian@0 288 #define HP100_LO_MEM 0x01 /* 1: Mapped Mem requested below 1MB */
ian@0 289 #define HP100_NO_MEM 0x02 /* 1: Disables Req for sysmem to PCI */
ian@0 290 /* bios */
ian@0 291 #define HP100_USE_ISA 0x04 /* 1: isa type decodes will occur */
ian@0 292 /* simultaneously with PCI decodes */
ian@0 293 #define HP100_IRQ_HI_MASK 0xf0 /* pgmed by pci bios */
ian@0 294 #define HP100_PCI_IRQ_HI_MASK 0x78 /* Isolate 4 bits for PCI IRQ */
ian@0 295
ian@0 296 /*
ian@0 297 * PCI Configuration and Control Register II
ian@0 298 * (Page HW_MAP, PCICTRL2, Offset 0x13)
ian@0 299 */
ian@0 300 #define HP100_RD_LINE_PDL 0x01 /* 1: PCI command Memory Read Line en */
ian@0 301 #define HP100_RD_TX_DATA_MASK 0x06 /* choose PCI memread cmds for TX */
ian@0 302 #define HP100_MWI 0x08 /* 1: en. PCI memory write invalidate */
ian@0 303 #define HP100_ARB_MODE 0x10 /* Select PCI arbitor type */
ian@0 304 #define HP100_STOP_EN 0x20 /* Enables PCI state machine to issue */
ian@0 305 /* pci stop if cascade not ready */
ian@0 306 #define HP100_IGNORE_PAR 0x40 /* 1: PCI state machine ignores parity */
ian@0 307 #define HP100_PCI_RESET 0x80 /* 0->1: Reset PCI block */
ian@0 308
ian@0 309 /*
ian@0 310 * Early TX Configuration and Control Register
ian@0 311 * (Page HW_MAP, EARLYTXCFG, Offset 0x16)
ian@0 312 */
ian@0 313 #define HP100_EN_EARLY_TX 0x8000 /* 1=Enable Early TX */
ian@0 314 #define HP100_EN_ADAPTIVE 0x4000 /* 1=Enable adaptive mode */
ian@0 315 #define HP100_EN_TX_UR_IRQ 0x2000 /* reserved, must be 0 */
ian@0 316 #define HP100_EN_LOW_TX 0x1000 /* reserved, must be 0 */
ian@0 317 #define HP100_ET_CNT_MASK 0x0fff /* bits 11..0: ET counters */
ian@0 318
ian@0 319 /*
ian@0 320 * Early RX Configuration and Control Register
ian@0 321 * (Page HW_MAP, EARLYRXCFG, Offset 0x18)
ian@0 322 */
ian@0 323 #define HP100_EN_EARLY_RX 0x80 /* 1=Enable Early RX */
ian@0 324 #define HP100_EN_LOW_RX 0x40 /* reserved, must be 0 */
ian@0 325 #define HP100_RX_TRIP_MASK 0x1f /* bits 4..0: threshold at which the
ian@0 326 * early rx circuit will start the
ian@0 327 * dma of received packet into system
ian@0 328 * memory for BM */
ian@0 329
ian@0 330 /*
ian@0 331 * Serial Devices Control Register
ian@0 332 * (Page EEPROM_CTRL, EEPROM_CTRL, Offset 0x08)
ian@0 333 */
ian@0 334 #define HP100_EEPROM_LOAD 0x0001 /* 0->1 loads EEPROM into registers. */
ian@0 335 /* When it goes back to 0, load is */
ian@0 336 /* complete. This should take ~600us. */
ian@0 337
ian@0 338 /*
ian@0 339 * 10MB LAN Control and Configuration Register I
ian@0 340 * (Page MAC_CTRL, 10_LAN_CFG_1, Offset 0x08)
ian@0 341 */
ian@0 342 #define HP100_MAC10_SEL 0xc0 /* Get bits to indicate MAC */
ian@0 343 #define HP100_AUI_SEL 0x20 /* Status of AUI selection */
ian@0 344 #define HP100_LOW_TH 0x10 /* 0:No, 1:Yes allow better cabling */
ian@0 345 #define HP100_LINK_BEAT_DIS 0x08 /* 0:Enable, 1:Disable link beat */
ian@0 346 #define HP100_LINK_BEAT_ST 0x04 /* 0:No, 1:Yes link beat being Rx */
ian@0 347 #define HP100_R_ROL_ST 0x02 /* 0:No, 1:Yes Rx twisted pair has */
ian@0 348 /* been reversed */
ian@0 349 #define HP100_AUI_ST 0x01 /* 0:No, 1:Yes use AUI on TP card */
ian@0 350
ian@0 351 /*
ian@0 352 * 10 MB LAN Control and Configuration Register II
ian@0 353 * (Page MAC_CTRL, 10_LAN_CFG_2, Offset 0x09)
ian@0 354 */
ian@0 355 #define HP100_SQU_ST 0x01 /* 0:No, 1:Yes collision signal sent */
ian@0 356 /* after Tx.Only used for AUI. */
ian@0 357 #define HP100_FULLDUP 0x02 /* 1: LXT901 XCVR fullduplx enabled */
ian@0 358 #define HP100_DOT3_MAC 0x04 /* 1: DOT 3 Mac sel. unless Autosel */
ian@0 359
ian@0 360 /*
ian@0 361 * MAC Selection, use with MAC10_SEL bits
ian@0 362 */
ian@0 363 #define HP100_AUTO_SEL_10 0x0 /* Auto select */
ian@0 364 #define HP100_XCVR_LXT901_10 0x1 /* LXT901 10BaseT transceiver */
ian@0 365 #define HP100_XCVR_7213 0x2 /* 7213 transceiver */
ian@0 366 #define HP100_XCVR_82503 0x3 /* 82503 transceiver */
ian@0 367
ian@0 368 /*
ian@0 369 * 100MB LAN Training Register
ian@0 370 * (Page MAC_CTRL, VG_LAN_CFG_2, Offset 0x0b) (old, pre 802.12)
ian@0 371 */
ian@0 372 #define HP100_FRAME_FORMAT 0x08 /* 0:802.3, 1:802.5 frames */
ian@0 373 #define HP100_BRIDGE 0x04 /* 0:No, 1:Yes tell hub i am a bridge */
ian@0 374 #define HP100_PROM_MODE 0x02 /* 0:No, 1:Yes tell hub card is */
ian@0 375 /* promiscuous */
ian@0 376 #define HP100_REPEATER 0x01 /* 0:No, 1:Yes tell hub MAC wants to */
ian@0 377 /* be a cascaded repeater */
ian@0 378
ian@0 379 /*
ian@0 380 * 100MB LAN Control and Configuration Register
ian@0 381 * (Page MAC_CTRL, VG_LAN_CFG_1, Offset 0x0a)
ian@0 382 */
ian@0 383 #define HP100_VG_SEL 0x80 /* 0:No, 1:Yes use 100 Mbit MAC */
ian@0 384 #define HP100_LINK_UP_ST 0x40 /* 0:No, 1:Yes endnode logged in */
ian@0 385 #define HP100_LINK_CABLE_ST 0x20 /* 0:No, 1:Yes cable can hear tones */
ian@0 386 /* from hub */
ian@0 387 #define HP100_LOAD_ADDR 0x10 /* 0->1 card addr will be sent */
ian@0 388 /* 100ms later the link status */
ian@0 389 /* bits are valid */
ian@0 390 #define HP100_LINK_CMD 0x08 /* 0->1 link will attempt to log in. */
ian@0 391 /* 100ms later the link status */
ian@0 392 /* bits are valid */
ian@0 393 #define HP100_TRN_DONE 0x04 /* NEW ETR-Chips only: Will be reset */
ian@0 394 /* after LinkUp Cmd is given and set */
ian@0 395 /* when training has completed. */
ian@0 396 #define HP100_LINK_GOOD_ST 0x02 /* 0:No, 1:Yes cable passed training */
ian@0 397 #define HP100_VG_RESET 0x01 /* 0:Yes, 1:No reset the 100VG MAC */
ian@0 398
ian@0 399
ian@0 400 /*
ian@0 401 * MAC Configuration Register I
ian@0 402 * (Page MAC_CTRL, MAC_CFG_1, Offset 0x0c)
ian@0 403 */
ian@0 404 #define HP100_RX_IDLE 0x80 /* 0:Yes, 1:No currently receiving pkts */
ian@0 405 #define HP100_TX_IDLE 0x40 /* 0:Yes, 1:No currently Txing pkts */
ian@0 406 #define HP100_RX_EN 0x20 /* 1: allow receiving of pkts */
ian@0 407 #define HP100_TX_EN 0x10 /* 1: allow transmitting of pkts */
ian@0 408 #define HP100_ACC_ERRORED 0x08 /* 0:No, 1:Yes allow Rx of errored pkts */
ian@0 409 #define HP100_ACC_MC 0x04 /* 0:No, 1:Yes allow Rx of multicast pkts */
ian@0 410 #define HP100_ACC_BC 0x02 /* 0:No, 1:Yes allow Rx of broadcast pkts */
ian@0 411 #define HP100_ACC_PHY 0x01 /* 0:No, 1:Yes allow Rx of ALL phys. pkts */
ian@0 412 #define HP100_MAC1MODEMASK 0xf0 /* Hide ACC bits */
ian@0 413 #define HP100_MAC1MODE1 0x00 /* Receive nothing, must also disable RX */
ian@0 414 #define HP100_MAC1MODE2 0x00
ian@0 415 #define HP100_MAC1MODE3 HP100_MAC1MODE2 | HP100_ACC_BC
ian@0 416 #define HP100_MAC1MODE4 HP100_MAC1MODE3 | HP100_ACC_MC
ian@0 417 #define HP100_MAC1MODE5 HP100_MAC1MODE4 /* set mc hash to all ones also */
ian@0 418 #define HP100_MAC1MODE6 HP100_MAC1MODE5 | HP100_ACC_PHY /* Promiscuous */
ian@0 419 /* Note MODE6 will receive all GOOD packets on the LAN. This really needs
ian@0 420 a mode 7 defined to be LAN Analyzer mode, which will receive errored and
ian@0 421 runt packets, and keep the CRC bytes. */
ian@0 422 #define HP100_MAC1MODE7 HP100_MAC1MODE6 | HP100_ACC_ERRORED
ian@0 423
ian@0 424 /*
ian@0 425 * MAC Configuration Register II
ian@0 426 * (Page MAC_CTRL, MAC_CFG_2, Offset 0x0d)
ian@0 427 */
ian@0 428 #define HP100_TR_MODE 0x80 /* 0:No, 1:Yes support Token Ring formats */
ian@0 429 #define HP100_TX_SAME 0x40 /* 0:No, 1:Yes Tx same packet continuous */
ian@0 430 #define HP100_LBK_XCVR 0x20 /* 0:No, 1:Yes loopback through MAC & */
ian@0 431 /* transceiver */
ian@0 432 #define HP100_LBK_MAC 0x10 /* 0:No, 1:Yes loopback through MAC */
ian@0 433 #define HP100_CRC_I 0x08 /* 0:No, 1:Yes inhibit CRC on Tx packets */
ian@0 434 #define HP100_ACCNA 0x04 /* 1: For 802.5: Accept only token ring
ian@0 435 * group addr that maches NA mask */
ian@0 436 #define HP100_KEEP_CRC 0x02 /* 0:No, 1:Yes keep CRC on Rx packets. */
ian@0 437 /* The length will reflect this. */
ian@0 438 #define HP100_ACCFA 0x01 /* 1: For 802.5: Accept only functional
ian@0 439 * addrs that match FA mask (page1) */
ian@0 440 #define HP100_MAC2MODEMASK 0x02
ian@0 441 #define HP100_MAC2MODE1 0x00
ian@0 442 #define HP100_MAC2MODE2 0x00
ian@0 443 #define HP100_MAC2MODE3 0x00
ian@0 444 #define HP100_MAC2MODE4 0x00
ian@0 445 #define HP100_MAC2MODE5 0x00
ian@0 446 #define HP100_MAC2MODE6 0x00
ian@0 447 #define HP100_MAC2MODE7 KEEP_CRC
ian@0 448
ian@0 449 /*
ian@0 450 * MAC Configuration Register III
ian@0 451 * (Page MAC_CTRL, MAC_CFG_3, Offset 0x0e)
ian@0 452 */
ian@0 453 #define HP100_PACKET_PACE 0x03 /* Packet Pacing:
ian@0 454 * 00: No packet pacing
ian@0 455 * 01: 8 to 16 uS delay
ian@0 456 * 10: 16 to 32 uS delay
ian@0 457 * 11: 32 to 64 uS delay
ian@0 458 */
ian@0 459 #define HP100_LRF_EN 0x04 /* 1: External LAN Rcv Filter and
ian@0 460 * TCP/IP Checksumming enabled. */
ian@0 461 #define HP100_AUTO_MODE 0x10 /* 1: AutoSelect between 10/100 */
ian@0 462
ian@0 463 /*
ian@0 464 * MAC Configuration Register IV
ian@0 465 * (Page MAC_CTRL, MAC_CFG_4, Offset 0x0f)
ian@0 466 */
ian@0 467 #define HP100_MAC_SEL_ST 0x01 /* (R): Status of external VGSEL
ian@0 468 * Signal, 1=100VG, 0=10Mbit sel. */
ian@0 469 #define HP100_LINK_FAIL_ST 0x02 /* (R): Status of Link Fail portion
ian@0 470 * of the Misc. Interrupt */
ian@0 471
ian@0 472 /*
ian@0 473 * 100 MB LAN Training Request/Allowed Registers
ian@0 474 * (Page MAC_CTRL, TRAIN_REQUEST and TRAIN_ALLOW, Offset 0x14-0x16)(ETR parts only)
ian@0 475 */
ian@0 476 #define HP100_MACRQ_REPEATER 0x0001 /* 1: MAC tells HUB it wants to be
ian@0 477 * a cascaded repeater
ian@0 478 * 0: ... wants to be a DTE */
ian@0 479 #define HP100_MACRQ_PROMSC 0x0006 /* 2 bits: Promiscious mode
ian@0 480 * 00: Rcv only unicast packets
ian@0 481 * specifically addr to this
ian@0 482 * endnode
ian@0 483 * 10: Rcv all pckts fwded by
ian@0 484 * the local repeater */
ian@0 485 #define HP100_MACRQ_FRAMEFMT_EITHER 0x0018 /* 11: either format allowed */
ian@0 486 #define HP100_MACRQ_FRAMEFMT_802_3 0x0000 /* 00: 802.3 is requested */
ian@0 487 #define HP100_MACRQ_FRAMEFMT_802_5 0x0010 /* 10: 802.5 format is requested */
ian@0 488 #define HP100_CARD_MACVER 0xe000 /* R: 3 bit Cards 100VG MAC version */
ian@0 489 #define HP100_MALLOW_REPEATER 0x0001 /* If reset, requested access as an
ian@0 490 * end node is allowed */
ian@0 491 #define HP100_MALLOW_PROMSC 0x0004 /* 2 bits: Promiscious mode
ian@0 492 * 00: Rcv only unicast packets
ian@0 493 * specifically addr to this
ian@0 494 * endnode
ian@0 495 * 10: Rcv all pckts fwded by
ian@0 496 * the local repeater */
ian@0 497 #define HP100_MALLOW_FRAMEFMT 0x00e0 /* 2 bits: Frame Format
ian@0 498 * 00: 802.3 format will be used
ian@0 499 * 10: 802.5 format will be used */
ian@0 500 #define HP100_MALLOW_ACCDENIED 0x0400 /* N bit */
ian@0 501 #define HP100_MALLOW_CONFIGURE 0x0f00 /* C bit */
ian@0 502 #define HP100_MALLOW_DUPADDR 0x1000 /* D bit */
ian@0 503 #define HP100_HUB_MACVER 0xe000 /* R: 3 bit 802.12 MAC/RMAC training */
ian@0 504 /* protocol of repeater */
ian@0 505
ian@0 506 /* ****************************************************************************** */
ian@0 507
ian@0 508 /*
ian@0 509 * Set/Reset bits
ian@0 510 */
ian@0 511 #define HP100_SET_HB 0x0100 /* 0:Set fields to 0 whose mask is 1 */
ian@0 512 #define HP100_SET_LB 0x0001 /* HB sets upper byte, LB sets lower byte */
ian@0 513 #define HP100_RESET_HB 0x0000 /* For readability when resetting bits */
ian@0 514 #define HP100_RESET_LB 0x0000 /* For readability when resetting bits */
ian@0 515
ian@0 516 /*
ian@0 517 * Misc. Constants
ian@0 518 */
ian@0 519 #define HP100_LAN_100 100 /* lan_type value for VG */
ian@0 520 #define HP100_LAN_10 10 /* lan_type value for 10BaseT */
ian@0 521 #define HP100_LAN_COAX 9 /* lan_type value for Coax */
ian@0 522 #define HP100_LAN_ERR (-1) /* lan_type value for link down */
ian@0 523
ian@0 524 /*
ian@0 525 * Bus Master Data Structures ----------------------------------------------
ian@0 526 */
ian@0 527
ian@0 528 #define MAX_RX_PDL 30 /* Card limit = 31 */
ian@0 529 #define MAX_RX_FRAG 2 /* Don't need more... */
ian@0 530 #define MAX_TX_PDL 29
ian@0 531 #define MAX_TX_FRAG 2 /* Limit = 31 */
ian@0 532
ian@0 533 /* Define total PDL area size in bytes (should be 4096) */
ian@0 534 /* This is the size of kernel (dma) memory that will be allocated. */
ian@0 535 #define MAX_RINGSIZE ((MAX_RX_FRAG*8+4+4)*MAX_RX_PDL+(MAX_TX_FRAG*8+4+4)*MAX_TX_PDL)+16
ian@0 536
ian@0 537 /* Ethernet Packet Sizes */
ian@0 538 #define MIN_ETHER_SIZE 60
ian@0 539 #define MAX_ETHER_SIZE 1514 /* Needed for preallocation of */
ian@0 540 /* skb buffer when busmastering */
ian@0 541
ian@0 542 /* Tx or Rx Ring Entry */
ian@0 543 typedef struct hp100_ring {
ian@0 544 u_int *pdl; /* Address of PDLs PDH, dword before
ian@0 545 * this address is used for rx hdr */
ian@0 546 u_int pdl_paddr; /* Physical address of PDL */
ian@0 547 struct sk_buff *skb;
ian@0 548 struct hp100_ring *next;
ian@0 549 } hp100_ring_t;
ian@0 550
ian@0 551
ian@0 552
ian@0 553 /* Mask for Header Descriptor */
ian@0 554 #define HP100_PKT_LEN_MASK 0x1FFF /* AND with RxLength to get length */
ian@0 555
ian@0 556
ian@0 557 /* Receive Packet Status. Note, the error bits are only valid if ACC_ERRORED
ian@0 558 bit in the MAC Configuration Register 1 is set. */
ian@0 559 #define HP100_RX_PRI 0x8000 /* 0:No, 1:Yes packet is priority */
ian@0 560 #define HP100_SDF_ERR 0x4000 /* 0:No, 1:Yes start of frame error */
ian@0 561 #define HP100_SKEW_ERR 0x2000 /* 0:No, 1:Yes skew out of range */
ian@0 562 #define HP100_BAD_SYMBOL_ERR 0x1000 /* 0:No, 1:Yes invalid symbol received */
ian@0 563 #define HP100_RCV_IPM_ERR 0x0800 /* 0:No, 1:Yes pkt had an invalid packet */
ian@0 564 /* marker */
ian@0 565 #define HP100_SYMBOL_BAL_ERR 0x0400 /* 0:No, 1:Yes symbol balance error */
ian@0 566 #define HP100_VG_ALN_ERR 0x0200 /* 0:No, 1:Yes non-octet received */
ian@0 567 #define HP100_TRUNC_ERR 0x0100 /* 0:No, 1:Yes the packet was truncated */
ian@0 568 #define HP100_RUNT_ERR 0x0040 /* 0:No, 1:Yes pkt length < Min Pkt */
ian@0 569 /* Length Reg. */
ian@0 570 #define HP100_ALN_ERR 0x0010 /* 0:No, 1:Yes align error. */
ian@0 571 #define HP100_CRC_ERR 0x0008 /* 0:No, 1:Yes CRC occurred. */
ian@0 572
ian@0 573 /* The last three bits indicate the type of destination address */
ian@0 574
ian@0 575 #define HP100_MULTI_ADDR_HASH 0x0006 /* 110: Addr multicast, matched hash */
ian@0 576 #define HP100_BROADCAST_ADDR 0x0003 /* x11: Addr broadcast */
ian@0 577 #define HP100_MULTI_ADDR_NO_HASH 0x0002 /* 010: Addr multicast, didn't match hash */
ian@0 578 #define HP100_PHYS_ADDR_MATCH 0x0001 /* x01: Addr was physical and mine */
ian@0 579 #define HP100_PHYS_ADDR_NO_MATCH 0x0000 /* x00: Addr was physical but not mine */
ian@0 580
ian@0 581 /*
ian@0 582 * macros
ian@0 583 */
ian@0 584
ian@0 585 #define hp100_inb( reg ) \
ian@0 586 inb( ioaddr + HP100_REG_##reg )
ian@0 587 #define hp100_inw( reg ) \
ian@0 588 inw( ioaddr + HP100_REG_##reg )
ian@0 589 #define hp100_inl( reg ) \
ian@0 590 inl( ioaddr + HP100_REG_##reg )
ian@0 591 #define hp100_outb( data, reg ) \
ian@0 592 outb( data, ioaddr + HP100_REG_##reg )
ian@0 593 #define hp100_outw( data, reg ) \
ian@0 594 outw( data, ioaddr + HP100_REG_##reg )
ian@0 595 #define hp100_outl( data, reg ) \
ian@0 596 outl( data, ioaddr + HP100_REG_##reg )
ian@0 597 #define hp100_orb( data, reg ) \
ian@0 598 outb( inb( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg )
ian@0 599 #define hp100_orw( data, reg ) \
ian@0 600 outw( inw( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg )
ian@0 601 #define hp100_andb( data, reg ) \
ian@0 602 outb( inb( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg )
ian@0 603 #define hp100_andw( data, reg ) \
ian@0 604 outw( inw( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg )
ian@0 605
ian@0 606 #define hp100_page( page ) \
ian@0 607 outw( HP100_PAGE_##page, ioaddr + HP100_REG_PAGING )
ian@0 608 #define hp100_ints_off() \
ian@0 609 outw( HP100_INT_EN | HP100_RESET_LB, ioaddr + HP100_REG_OPTION_LSW )
ian@0 610 #define hp100_ints_on() \
ian@0 611 outw( HP100_INT_EN | HP100_SET_LB, ioaddr + HP100_REG_OPTION_LSW )
ian@0 612 #define hp100_mem_map_enable() \
ian@0 613 outw( HP100_MMAP_DIS | HP100_RESET_HB, ioaddr + HP100_REG_OPTION_LSW )
ian@0 614 #define hp100_mem_map_disable() \
ian@0 615 outw( HP100_MMAP_DIS | HP100_SET_HB, ioaddr + HP100_REG_OPTION_LSW )