ia64/linux-2.6.18-xen.hg

annotate drivers/net/cs89x0.h @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents 831230e53067
children
rev   line source
ian@0 1 /* Copyright, 1988-1992, Russell Nelson, Crynwr Software
ian@0 2
ian@0 3 This program is free software; you can redistribute it and/or modify
ian@0 4 it under the terms of the GNU General Public License as published by
ian@0 5 the Free Software Foundation, version 1.
ian@0 6
ian@0 7 This program is distributed in the hope that it will be useful,
ian@0 8 but WITHOUT ANY WARRANTY; without even the implied warranty of
ian@0 9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ian@0 10 GNU General Public License for more details.
ian@0 11
ian@0 12 You should have received a copy of the GNU General Public License
ian@0 13 along with this program; if not, write to the Free Software
ian@0 14 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
ian@0 15 */
ian@0 16
ian@0 17
ian@0 18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
ian@0 19 /* offset 2h -> Model/Product Number */
ian@0 20 /* offset 3h -> Chip Revision Number */
ian@0 21
ian@0 22 #define PP_ISAIOB 0x0020 /* IO base address */
ian@0 23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
ian@0 24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
ian@0 25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
ian@0 26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
ian@0 27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
ian@0 28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
ian@0 29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
ian@0 30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
ian@0 31 #define PP_CS8920_ISAMemB 0x0348 /* */
ian@0 32
ian@0 33 #define PP_ISABootBase 0x0030 /* Boot Prom base */
ian@0 34 #define PP_ISABootMask 0x0034 /* Boot Prom Mask */
ian@0 35
ian@0 36 /* EEPROM data and command registers */
ian@0 37 #define PP_EECMD 0x0040 /* NVR Interface Command register */
ian@0 38 #define PP_EEData 0x0042 /* NVR Interface Data Register */
ian@0 39 #define PP_DebugReg 0x0044 /* Debug Register */
ian@0 40
ian@0 41 #define PP_RxCFG 0x0102 /* Rx Bus config */
ian@0 42 #define PP_RxCTL 0x0104 /* Receive Control Register */
ian@0 43 #define PP_TxCFG 0x0106 /* Transmit Config Register */
ian@0 44 #define PP_TxCMD 0x0108 /* Transmit Command Register */
ian@0 45 #define PP_BufCFG 0x010A /* Bus configuration Register */
ian@0 46 #define PP_LineCTL 0x0112 /* Line Config Register */
ian@0 47 #define PP_SelfCTL 0x0114 /* Self Command Register */
ian@0 48 #define PP_BusCTL 0x0116 /* ISA bus control Register */
ian@0 49 #define PP_TestCTL 0x0118 /* Test Register */
ian@0 50 #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
ian@0 51
ian@0 52 #define PP_ISQ 0x0120 /* Interrupt Status */
ian@0 53 #define PP_RxEvent 0x0124 /* Rx Event Register */
ian@0 54 #define PP_TxEvent 0x0128 /* Tx Event Register */
ian@0 55 #define PP_BufEvent 0x012C /* Bus Event Register */
ian@0 56 #define PP_RxMiss 0x0130 /* Receive Miss Count */
ian@0 57 #define PP_TxCol 0x0132 /* Transmit Collision Count */
ian@0 58 #define PP_LineST 0x0134 /* Line State Register */
ian@0 59 #define PP_SelfST 0x0136 /* Self State register */
ian@0 60 #define PP_BusST 0x0138 /* Bus Status */
ian@0 61 #define PP_TDR 0x013C /* Time Domain Reflectometry */
ian@0 62 #define PP_AutoNegST 0x013E /* Auto Neg Status */
ian@0 63 #define PP_TxCommand 0x0144 /* Tx Command */
ian@0 64 #define PP_TxLength 0x0146 /* Tx Length */
ian@0 65 #define PP_LAF 0x0150 /* Hash Table */
ian@0 66 #define PP_IA 0x0158 /* Physical Address Register */
ian@0 67
ian@0 68 #define PP_RxStatus 0x0400 /* Receive start of frame */
ian@0 69 #define PP_RxLength 0x0402 /* Receive Length of frame */
ian@0 70 #define PP_RxFrame 0x0404 /* Receive frame pointer */
ian@0 71 #define PP_TxFrame 0x0A00 /* Transmit frame pointer */
ian@0 72
ian@0 73 /* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
ian@0 74 /* can be used as the default I/O base to access the PacketPage Area. */
ian@0 75 #define DEFAULTIOBASE 0x0300
ian@0 76 #define FIRST_IO 0x020C /* First I/O port to check */
ian@0 77 #define LAST_IO 0x037C /* Last I/O port to check (+10h) */
ian@0 78 #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
ian@0 79 #define ADD_SIG 0x3000 /* Expected ID signature */
ian@0 80
ian@0 81 /* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */
ian@0 82 #ifdef CONFIG_MAC
ian@0 83 #define LCSLOTBASE 0xfee00000
ian@0 84 #define MMIOBASE 0x40000
ian@0 85 #endif
ian@0 86
ian@0 87 #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
ian@0 88 #define CHIP_EISA_ID_SIG_STR "0x630E"
ian@0 89
ian@0 90 #ifdef IBMEIPKT
ian@0 91 #define EISA_ID_SIG 0x4D24 /* IBM */
ian@0 92 #define PART_NO_SIG 0x1010 /* IBM */
ian@0 93 #define MONGOOSE_BIT 0x0000 /* IBM */
ian@0 94 #else
ian@0 95 #define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
ian@0 96 #define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
ian@0 97 #define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
ian@0 98 #endif
ian@0 99
ian@0 100 #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
ian@0 101
ian@0 102 /* Mask to find out the types of registers */
ian@0 103 #define REG_TYPE_MASK 0x001F
ian@0 104
ian@0 105 /* Eeprom Commands */
ian@0 106 #define ERSE_WR_ENBL 0x00F0
ian@0 107 #define ERSE_WR_DISABLE 0x0000
ian@0 108
ian@0 109 /* Defines Control/Config register quintuplet numbers */
ian@0 110 #define RX_BUF_CFG 0x0003
ian@0 111 #define RX_CONTROL 0x0005
ian@0 112 #define TX_CFG 0x0007
ian@0 113 #define TX_COMMAND 0x0009
ian@0 114 #define BUF_CFG 0x000B
ian@0 115 #define LINE_CONTROL 0x0013
ian@0 116 #define SELF_CONTROL 0x0015
ian@0 117 #define BUS_CONTROL 0x0017
ian@0 118 #define TEST_CONTROL 0x0019
ian@0 119
ian@0 120 /* Defines Status/Count registers quintuplet numbers */
ian@0 121 #define RX_EVENT 0x0004
ian@0 122 #define TX_EVENT 0x0008
ian@0 123 #define BUF_EVENT 0x000C
ian@0 124 #define RX_MISS_COUNT 0x0010
ian@0 125 #define TX_COL_COUNT 0x0012
ian@0 126 #define LINE_STATUS 0x0014
ian@0 127 #define SELF_STATUS 0x0016
ian@0 128 #define BUS_STATUS 0x0018
ian@0 129 #define TDR 0x001C
ian@0 130
ian@0 131 /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
ian@0 132 #define SKIP_1 0x0040
ian@0 133 #define RX_STREAM_ENBL 0x0080
ian@0 134 #define RX_OK_ENBL 0x0100
ian@0 135 #define RX_DMA_ONLY 0x0200
ian@0 136 #define AUTO_RX_DMA 0x0400
ian@0 137 #define BUFFER_CRC 0x0800
ian@0 138 #define RX_CRC_ERROR_ENBL 0x1000
ian@0 139 #define RX_RUNT_ENBL 0x2000
ian@0 140 #define RX_EXTRA_DATA_ENBL 0x4000
ian@0 141
ian@0 142 /* PP_RxCTL - Receive Control bit definition - Read/write */
ian@0 143 #define RX_IA_HASH_ACCEPT 0x0040
ian@0 144 #define RX_PROM_ACCEPT 0x0080
ian@0 145 #define RX_OK_ACCEPT 0x0100
ian@0 146 #define RX_MULTCAST_ACCEPT 0x0200
ian@0 147 #define RX_IA_ACCEPT 0x0400
ian@0 148 #define RX_BROADCAST_ACCEPT 0x0800
ian@0 149 #define RX_BAD_CRC_ACCEPT 0x1000
ian@0 150 #define RX_RUNT_ACCEPT 0x2000
ian@0 151 #define RX_EXTRA_DATA_ACCEPT 0x4000
ian@0 152 #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
ian@0 153 /* Default receive mode - individually addressed, broadcast, and error free */
ian@0 154 #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
ian@0 155
ian@0 156 /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
ian@0 157 #define TX_LOST_CRS_ENBL 0x0040
ian@0 158 #define TX_SQE_ERROR_ENBL 0x0080
ian@0 159 #define TX_OK_ENBL 0x0100
ian@0 160 #define TX_LATE_COL_ENBL 0x0200
ian@0 161 #define TX_JBR_ENBL 0x0400
ian@0 162 #define TX_ANY_COL_ENBL 0x0800
ian@0 163 #define TX_16_COL_ENBL 0x8000
ian@0 164
ian@0 165 /* PP_TxCMD - Transmit Command bit definition - Read-only */
ian@0 166 #define TX_START_4_BYTES 0x0000
ian@0 167 #define TX_START_64_BYTES 0x0040
ian@0 168 #define TX_START_128_BYTES 0x0080
ian@0 169 #define TX_START_ALL_BYTES 0x00C0
ian@0 170 #define TX_FORCE 0x0100
ian@0 171 #define TX_ONE_COL 0x0200
ian@0 172 #define TX_TWO_PART_DEFF_DISABLE 0x0400
ian@0 173 #define TX_NO_CRC 0x1000
ian@0 174 #define TX_RUNT 0x2000
ian@0 175
ian@0 176 /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
ian@0 177 #define GENERATE_SW_INTERRUPT 0x0040
ian@0 178 #define RX_DMA_ENBL 0x0080
ian@0 179 #define READY_FOR_TX_ENBL 0x0100
ian@0 180 #define TX_UNDERRUN_ENBL 0x0200
ian@0 181 #define RX_MISS_ENBL 0x0400
ian@0 182 #define RX_128_BYTE_ENBL 0x0800
ian@0 183 #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
ian@0 184 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
ian@0 185 #define RX_DEST_MATCH_ENBL 0x8000
ian@0 186
ian@0 187 /* PP_LineCTL - Line Control bit definition - Read/write */
ian@0 188 #define SERIAL_RX_ON 0x0040
ian@0 189 #define SERIAL_TX_ON 0x0080
ian@0 190 #define AUI_ONLY 0x0100
ian@0 191 #define AUTO_AUI_10BASET 0x0200
ian@0 192 #define MODIFIED_BACKOFF 0x0800
ian@0 193 #define NO_AUTO_POLARITY 0x1000
ian@0 194 #define TWO_PART_DEFDIS 0x2000
ian@0 195 #define LOW_RX_SQUELCH 0x4000
ian@0 196
ian@0 197 /* PP_SelfCTL - Software Self Control bit definition - Read/write */
ian@0 198 #define POWER_ON_RESET 0x0040
ian@0 199 #define SW_STOP 0x0100
ian@0 200 #define SLEEP_ON 0x0200
ian@0 201 #define AUTO_WAKEUP 0x0400
ian@0 202 #define HCB0_ENBL 0x1000
ian@0 203 #define HCB1_ENBL 0x2000
ian@0 204 #define HCB0 0x4000
ian@0 205 #define HCB1 0x8000
ian@0 206
ian@0 207 /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
ian@0 208 #define RESET_RX_DMA 0x0040
ian@0 209 #define MEMORY_ON 0x0400
ian@0 210 #define DMA_BURST_MODE 0x0800
ian@0 211 #define IO_CHANNEL_READY_ON 0x1000
ian@0 212 #define RX_DMA_SIZE_64K 0x2000
ian@0 213 #define ENABLE_IRQ 0x8000
ian@0 214
ian@0 215 /* PP_TestCTL - Test Control bit definition - Read/write */
ian@0 216 #define LINK_OFF 0x0080
ian@0 217 #define ENDEC_LOOPBACK 0x0200
ian@0 218 #define AUI_LOOPBACK 0x0400
ian@0 219 #define BACKOFF_OFF 0x0800
ian@0 220 #define FDX_8900 0x4000
ian@0 221 #define FAST_TEST 0x8000
ian@0 222
ian@0 223 /* PP_RxEvent - Receive Event Bit definition - Read-only */
ian@0 224 #define RX_IA_HASHED 0x0040
ian@0 225 #define RX_DRIBBLE 0x0080
ian@0 226 #define RX_OK 0x0100
ian@0 227 #define RX_HASHED 0x0200
ian@0 228 #define RX_IA 0x0400
ian@0 229 #define RX_BROADCAST 0x0800
ian@0 230 #define RX_CRC_ERROR 0x1000
ian@0 231 #define RX_RUNT 0x2000
ian@0 232 #define RX_EXTRA_DATA 0x4000
ian@0 233
ian@0 234 #define HASH_INDEX_MASK 0x0FC00
ian@0 235
ian@0 236 /* PP_TxEvent - Transmit Event Bit definition - Read-only */
ian@0 237 #define TX_LOST_CRS 0x0040
ian@0 238 #define TX_SQE_ERROR 0x0080
ian@0 239 #define TX_OK 0x0100
ian@0 240 #define TX_LATE_COL 0x0200
ian@0 241 #define TX_JBR 0x0400
ian@0 242 #define TX_16_COL 0x8000
ian@0 243 #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
ian@0 244 #define TX_COL_COUNT_MASK 0x7800
ian@0 245
ian@0 246 /* PP_BufEvent - Buffer Event Bit definition - Read-only */
ian@0 247 #define SW_INTERRUPT 0x0040
ian@0 248 #define RX_DMA 0x0080
ian@0 249 #define READY_FOR_TX 0x0100
ian@0 250 #define TX_UNDERRUN 0x0200
ian@0 251 #define RX_MISS 0x0400
ian@0 252 #define RX_128_BYTE 0x0800
ian@0 253 #define TX_COL_OVRFLW 0x1000
ian@0 254 #define RX_MISS_OVRFLW 0x2000
ian@0 255 #define RX_DEST_MATCH 0x8000
ian@0 256
ian@0 257 /* PP_LineST - Ethernet Line Status bit definition - Read-only */
ian@0 258 #define LINK_OK 0x0080
ian@0 259 #define AUI_ON 0x0100
ian@0 260 #define TENBASET_ON 0x0200
ian@0 261 #define POLARITY_OK 0x1000
ian@0 262 #define CRS_OK 0x4000
ian@0 263
ian@0 264 /* PP_SelfST - Chip Software Status bit definition */
ian@0 265 #define ACTIVE_33V 0x0040
ian@0 266 #define INIT_DONE 0x0080
ian@0 267 #define SI_BUSY 0x0100
ian@0 268 #define EEPROM_PRESENT 0x0200
ian@0 269 #define EEPROM_OK 0x0400
ian@0 270 #define EL_PRESENT 0x0800
ian@0 271 #define EE_SIZE_64 0x1000
ian@0 272
ian@0 273 /* PP_BusST - ISA Bus Status bit definition */
ian@0 274 #define TX_BID_ERROR 0x0080
ian@0 275 #define READY_FOR_TX_NOW 0x0100
ian@0 276
ian@0 277 /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
ian@0 278 #define RE_NEG_NOW 0x0040
ian@0 279 #define ALLOW_FDX 0x0080
ian@0 280 #define AUTO_NEG_ENABLE 0x0100
ian@0 281 #define NLP_ENABLE 0x0200
ian@0 282 #define FORCE_FDX 0x8000
ian@0 283 #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
ian@0 284 #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
ian@0 285
ian@0 286 /* PP_AutoNegST - Auto Negotiation Status bit definition */
ian@0 287 #define AUTO_NEG_BUSY 0x0080
ian@0 288 #define FLP_LINK 0x0100
ian@0 289 #define FLP_LINK_GOOD 0x0800
ian@0 290 #define LINK_FAULT 0x1000
ian@0 291 #define HDX_ACTIVE 0x4000
ian@0 292 #define FDX_ACTIVE 0x8000
ian@0 293
ian@0 294 /* The following block defines the ISQ event types */
ian@0 295 #define ISQ_RECEIVER_EVENT 0x04
ian@0 296 #define ISQ_TRANSMITTER_EVENT 0x08
ian@0 297 #define ISQ_BUFFER_EVENT 0x0c
ian@0 298 #define ISQ_RX_MISS_EVENT 0x10
ian@0 299 #define ISQ_TX_COL_EVENT 0x12
ian@0 300
ian@0 301 #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
ian@0 302 #define ISQ_HIST 16 /* small history buffer */
ian@0 303 #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
ian@0 304
ian@0 305 #define TXRXBUFSIZE 0x0600
ian@0 306 #define RXDMABUFSIZE 0x8000
ian@0 307 #define RXDMASIZE 0x4000
ian@0 308 #define TXRX_LENGTH_MASK 0x07FF
ian@0 309
ian@0 310 /* rx options bits */
ian@0 311 #define RCV_WITH_RXON 1 /* Set SerRx ON */
ian@0 312 #define RCV_COUNTS 2 /* Use Framecnt1 */
ian@0 313 #define RCV_PONG 4 /* Pong respondent */
ian@0 314 #define RCV_DONG 8 /* Dong operation */
ian@0 315 #define RCV_POLLING 0x10 /* Poll RxEvent */
ian@0 316 #define RCV_ISQ 0x20 /* Use ISQ, int */
ian@0 317 #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
ian@0 318 #define RCV_DMA 0x200 /* Set RxDMA only */
ian@0 319 #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
ian@0 320 #define RCV_FIXED_DATA 0x800 /* Every frame same */
ian@0 321 #define RCV_IO 0x1000 /* Use ISA IO only */
ian@0 322 #define RCV_MEMORY 0x2000 /* Use ISA Memory */
ian@0 323
ian@0 324 #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
ian@0 325 #define PKT_START PP_TxFrame /* Start of packet RAM */
ian@0 326
ian@0 327 #define RX_FRAME_PORT 0x0000
ian@0 328 #define TX_FRAME_PORT RX_FRAME_PORT
ian@0 329 #define TX_CMD_PORT 0x0004
ian@0 330 #define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
ian@0 331 #define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
ian@0 332 #define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */
ian@0 333 #define TX_LEN_PORT 0x0006
ian@0 334 #define ISQ_PORT 0x0008
ian@0 335 #define ADD_PORT 0x000A
ian@0 336 #define DATA_PORT 0x000C
ian@0 337
ian@0 338 #define EEPROM_WRITE_EN 0x00F0
ian@0 339 #define EEPROM_WRITE_DIS 0x0000
ian@0 340 #define EEPROM_WRITE_CMD 0x0100
ian@0 341 #define EEPROM_READ_CMD 0x0200
ian@0 342
ian@0 343 /* Receive Header */
ian@0 344 /* Description of header of each packet in receive area of memory */
ian@0 345 #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
ian@0 346 #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
ian@0 347 #define RBUF_LEN_LOW 2 /* Length of received data - low byte */
ian@0 348 #define RBUF_LEN_HI 3 /* Length of received data - high byte */
ian@0 349 #define RBUF_HEAD_LEN 4 /* Length of this header */
ian@0 350
ian@0 351 #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
ian@0 352 #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
ian@0 353
ian@0 354 /* for bios scan */
ian@0 355 /* */
ian@0 356 #ifdef CSDEBUG
ian@0 357 /* use these values for debugging bios scan */
ian@0 358 #define BIOS_START_SEG 0x00000
ian@0 359 #define BIOS_OFFSET_INC 0x0010
ian@0 360 #else
ian@0 361 #define BIOS_START_SEG 0x0c000
ian@0 362 #define BIOS_OFFSET_INC 0x0200
ian@0 363 #endif
ian@0 364
ian@0 365 #define BIOS_LAST_OFFSET 0x0fc00
ian@0 366
ian@0 367 /* Byte offsets into the EEPROM configuration buffer */
ian@0 368 #define ISA_CNF_OFFSET 0x6
ian@0 369 #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
ian@0 370 #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
ian@0 371
ian@0 372 /* the assumption here is that the bits in the eeprom are generally */
ian@0 373 /* in the same position as those in the autonegctl register. */
ian@0 374 /* Of course the IMM bit is not in that register so it must be */
ian@0 375 /* masked out */
ian@0 376 #define EE_FORCE_FDX 0x8000
ian@0 377 #define EE_NLP_ENABLE 0x0200
ian@0 378 #define EE_AUTO_NEG_ENABLE 0x0100
ian@0 379 #define EE_ALLOW_FDX 0x0080
ian@0 380 #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
ian@0 381
ian@0 382 #define IMM_BIT 0x0040 /* ignore missing media */
ian@0 383
ian@0 384 #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
ian@0 385 #define A_CNF_10B_T 0x0001
ian@0 386 #define A_CNF_AUI 0x0002
ian@0 387 #define A_CNF_10B_2 0x0004
ian@0 388 #define A_CNF_MEDIA_TYPE 0x0070
ian@0 389 #define A_CNF_MEDIA_AUTO 0x0070
ian@0 390 #define A_CNF_MEDIA_10B_T 0x0020
ian@0 391 #define A_CNF_MEDIA_AUI 0x0040
ian@0 392 #define A_CNF_MEDIA_10B_2 0x0010
ian@0 393 #define A_CNF_DC_DC_POLARITY 0x0080
ian@0 394 #define A_CNF_NO_AUTO_POLARITY 0x2000
ian@0 395 #define A_CNF_LOW_RX_SQUELCH 0x4000
ian@0 396 #define A_CNF_EXTND_10B_2 0x8000
ian@0 397
ian@0 398 #define PACKET_PAGE_OFFSET 0x8
ian@0 399
ian@0 400 /* Bit definitions for the ISA configuration word from the EEPROM */
ian@0 401 #define INT_NO_MASK 0x000F
ian@0 402 #define DMA_NO_MASK 0x0070
ian@0 403 #define ISA_DMA_SIZE 0x0200
ian@0 404 #define ISA_AUTO_RxDMA 0x0400
ian@0 405 #define ISA_RxDMA 0x0800
ian@0 406 #define DMA_BURST 0x1000
ian@0 407 #define STREAM_TRANSFER 0x2000
ian@0 408 #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
ian@0 409
ian@0 410 /* DMA controller registers */
ian@0 411 #define DMA_BASE 0x00 /* DMA controller base */
ian@0 412 #define DMA_BASE_2 0x0C0 /* DMA controller base */
ian@0 413
ian@0 414 #define DMA_STAT 0x0D0 /* DMA controller status register */
ian@0 415 #define DMA_MASK 0x0D4 /* DMA controller mask register */
ian@0 416 #define DMA_MODE 0x0D6 /* DMA controller mode register */
ian@0 417 #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
ian@0 418
ian@0 419 /* DMA data */
ian@0 420 #define DMA_DISABLE 0x04 /* Disable channel n */
ian@0 421 #define DMA_ENABLE 0x00 /* Enable channel n */
ian@0 422 /* Demand transfers, incr. address, auto init, writes, ch. n */
ian@0 423 #define DMA_RX_MODE 0x14
ian@0 424 /* Demand transfers, incr. address, auto init, reads, ch. n */
ian@0 425 #define DMA_TX_MODE 0x18
ian@0 426
ian@0 427 #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
ian@0 428
ian@0 429 #define CS8900 0x0000
ian@0 430 #define CS8920 0x4000
ian@0 431 #define CS8920M 0x6000
ian@0 432 #define REVISON_BITS 0x1F00
ian@0 433 #define EEVER_NUMBER 0x12
ian@0 434 #define CHKSUM_LEN 0x14
ian@0 435 #define CHKSUM_VAL 0x0000
ian@0 436 #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
ian@0 437 #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
ian@0 438 #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
ian@0 439 #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
ian@0 440 #ifdef CONFIG_SH_HICOSH4
ian@0 441 #define CS8900_IRQ_MAP 0x0002 /* HiCO-SH4 board has its IRQ on #1 */
ian@0 442 #else
ian@0 443 #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
ian@0 444 #endif
ian@0 445
ian@0 446 #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
ian@0 447
ian@0 448 #define PNP_ADD_PORT 0x0279
ian@0 449 #define PNP_WRITE_PORT 0x0A79
ian@0 450
ian@0 451 #define GET_PNP_ISA_STRUCT 0x40
ian@0 452 #define PNP_ISA_STRUCT_LEN 0x06
ian@0 453 #define PNP_CSN_CNT_OFF 0x01
ian@0 454 #define PNP_RD_PORT_OFF 0x02
ian@0 455 #define PNP_FUNCTION_OK 0x00
ian@0 456 #define PNP_WAKE 0x03
ian@0 457 #define PNP_RSRC_DATA 0x04
ian@0 458 #define PNP_RSRC_READY 0x01
ian@0 459 #define PNP_STATUS 0x05
ian@0 460 #define PNP_ACTIVATE 0x30
ian@0 461 #define PNP_CNF_IO_H 0x60
ian@0 462 #define PNP_CNF_IO_L 0x61
ian@0 463 #define PNP_CNF_INT 0x70
ian@0 464 #define PNP_CNF_DMA 0x74
ian@0 465 #define PNP_CNF_MEM 0x48
ian@0 466
ian@0 467 #define BIT0 1
ian@0 468 #define BIT15 0x8000
ian@0 469