ia64/linux-2.6.18-xen.hg

annotate arch/mips/pci/pci-excite.c @ 912:dd42cdb0ab89

[IA64] Build blktap2 driver by default in x86 builds.

add CONFIG_XEN_BLKDEV_TAP2=y to buildconfigs/linux-defconfig_xen_ia64.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 12:09:16 2009 +0900 (2009-06-29)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * Copyright (C) 2004 by Basler Vision Technologies AG
ian@0 3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
ian@0 4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
ian@0 5 *
ian@0 6 * This program is free software; you can redistribute it and/or modify
ian@0 7 * it under the terms of the GNU General Public License as published by
ian@0 8 * the Free Software Foundation; either version 2 of the License, or
ian@0 9 * (at your option) any later version.
ian@0 10 *
ian@0 11 * This program is distributed in the hope that it will be useful,
ian@0 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
ian@0 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ian@0 14 * GNU General Public License for more details.
ian@0 15 *
ian@0 16 * You should have received a copy of the GNU General Public License
ian@0 17 * along with this program; if not, write to the Free Software
ian@0 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ian@0 19 */
ian@0 20 #include <linux/init.h>
ian@0 21 #include <linux/kernel.h>
ian@0 22 #include <linux/types.h>
ian@0 23 #include <linux/pci.h>
ian@0 24 #include <linux/bitops.h>
ian@0 25 #include <asm/rm9k-ocd.h>
ian@0 26 #include <excite.h>
ian@0 27
ian@0 28
ian@0 29 extern struct pci_ops titan_pci_ops;
ian@0 30
ian@0 31
ian@0 32 static struct resource
ian@0 33 mem_resource = {
ian@0 34 .name = "PCI memory",
ian@0 35 .start = EXCITE_PHYS_PCI_MEM,
ian@0 36 .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
ian@0 37 .flags = IORESOURCE_MEM
ian@0 38 },
ian@0 39 io_resource = {
ian@0 40 .name = "PCI I/O",
ian@0 41 .start = EXCITE_PHYS_PCI_IO,
ian@0 42 .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
ian@0 43 .flags = IORESOURCE_IO
ian@0 44 };
ian@0 45
ian@0 46
ian@0 47 static struct pci_controller bx_controller = {
ian@0 48 .pci_ops = &titan_pci_ops,
ian@0 49 .mem_resource = &mem_resource,
ian@0 50 .mem_offset = 0x00000000UL,
ian@0 51 .io_resource = &io_resource,
ian@0 52 .io_offset = 0x00000000UL
ian@0 53 };
ian@0 54
ian@0 55
ian@0 56 static char
ian@0 57 iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
ian@0 58 modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
ian@0 59
ian@0 60 #define RM9000x2_OCD_HTSC 0x0604
ian@0 61 #define RM9000x2_OCD_HTBHL 0x060c
ian@0 62 #define RM9000x2_OCD_PCIHRST 0x078c
ian@0 63
ian@0 64 #define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
ian@0 65 #define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
ian@0 66
ian@0 67 #define PCISC_FB2B 0x00000200
ian@0 68 #define PCISC_MWICG 0x00000010
ian@0 69 #define PCISC_EMC 0x00000004
ian@0 70 #define PCISC_ERMA 0x00000002
ian@0 71
ian@0 72
ian@0 73
ian@0 74 static int __init basler_excite_pci_setup(void)
ian@0 75 {
ian@0 76 const unsigned int fullbars = memsize / (256 << 20);
ian@0 77 unsigned int i;
ian@0 78
ian@0 79 /* Check modebits to see if PCI is really enabled. */
ian@0 80 if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
ian@0 81 panic(modebits_no_pci);
ian@0 82
ian@0 83 if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
ian@0 84 "Memory-mapped PCI I/O page"))
ian@0 85 panic(iopage_failed);
ian@0 86
ian@0 87 /* Enable PCI 0 as master for config cycles */
ian@0 88 ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
ian@0 89
ian@0 90
ian@0 91 /* Set up latency timer */
ian@0 92 ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
ian@0 93
ian@0 94 /* Setup host IO and Memory space */
ian@0 95 ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
ian@0 96 ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
ian@0 97 ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
ian@0 98 ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
ian@0 99
ian@0 100 /* Set up PCI BARs to map all installed memory */
ian@0 101 for (i = 0; i < 6; i++) {
ian@0 102 const unsigned int bar = 0x610 + i * 4;
ian@0 103
ian@0 104 if (i < fullbars) {
ian@0 105 ocd_writel(0x10000000 * i, bar);
ian@0 106 ocd_writel(0x01000000 * i, bar + 0x140);
ian@0 107 ocd_writel(0x0ffff029, bar + 0x100);
ian@0 108 continue;
ian@0 109 }
ian@0 110
ian@0 111 if (i == fullbars) {
ian@0 112 int o;
ian@0 113 u32 mask;
ian@0 114
ian@0 115 const unsigned long rem = memsize - i * 0x10000000;
ian@0 116 if (!rem) {
ian@0 117 ocd_writel(0x00000000, bar + 0x100);
ian@0 118 continue;
ian@0 119 }
ian@0 120
ian@0 121 o = ffs(rem) - 1;
ian@0 122 if (rem & ~(0x1 << o))
ian@0 123 o++;
ian@0 124 mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
ian@0 125 ocd_writel(0x10000000 * i, bar);
ian@0 126 ocd_writel(0x01000000 * i, bar + 0x140);
ian@0 127 ocd_writel(0x00000029 | mask, bar + 0x100);
ian@0 128 continue;
ian@0 129 }
ian@0 130
ian@0 131 ocd_writel(0x00000000, bar + 0x100);
ian@0 132 }
ian@0 133
ian@0 134 /* Finally, enable the PCI interupt */
ian@0 135 #if USB_IRQ > 7
ian@0 136 set_c0_intcontrol(1 << USB_IRQ);
ian@0 137 #else
ian@0 138 set_c0_status(1 << (USB_IRQ + 8));
ian@0 139 #endif
ian@0 140
ian@0 141 ioport_resource.start = EXCITE_PHYS_PCI_IO;
ian@0 142 ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
ian@0 143 set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
ian@0 144 register_pci_controller(&bx_controller);
ian@0 145 return 0;
ian@0 146 }
ian@0 147
ian@0 148
ian@0 149 arch_initcall(basler_excite_pci_setup);