ia64/linux-2.6.18-xen.hg

annotate include/asm-v850/v850e_intc.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * include/asm-v850/v850e_intc.h -- V850E CPU interrupt controller (INTC)
ian@0 3 *
ian@0 4 * Copyright (C) 2001,02,03 NEC Electronics Corporation
ian@0 5 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
ian@0 6 *
ian@0 7 * This file is subject to the terms and conditions of the GNU General
ian@0 8 * Public License. See the file COPYING in the main directory of this
ian@0 9 * archive for more details.
ian@0 10 *
ian@0 11 * Written by Miles Bader <miles@gnu.org>
ian@0 12 */
ian@0 13
ian@0 14 #ifndef __V850_V850E_INTC_H__
ian@0 15 #define __V850_V850E_INTC_H__
ian@0 16
ian@0 17
ian@0 18 /* There are 4 16-bit `Interrupt Mask Registers' located contiguously
ian@0 19 starting from this base. Each interrupt uses a single bit to
ian@0 20 indicated enabled/disabled status. */
ian@0 21 #define V850E_INTC_IMR_BASE_ADDR 0xFFFFF100
ian@0 22 #define V850E_INTC_IMR_ADDR(irq) (V850E_INTC_IMR_BASE_ADDR + ((irq) >> 3))
ian@0 23 #define V850E_INTC_IMR_BIT(irq) ((irq) & 0x7)
ian@0 24
ian@0 25 /* Each maskable interrupt has a single-byte control register at this
ian@0 26 address. */
ian@0 27 #define V850E_INTC_IC_BASE_ADDR 0xFFFFF110
ian@0 28 #define V850E_INTC_IC_ADDR(irq) (V850E_INTC_IC_BASE_ADDR + ((irq) << 1))
ian@0 29 #define V850E_INTC_IC(irq) (*(volatile u8 *)V850E_INTC_IC_ADDR(irq))
ian@0 30 /* Encode priority PR for storing in an interrupt control register. */
ian@0 31 #define V850E_INTC_IC_PR(pr) (pr)
ian@0 32 /* Interrupt disable bit in an interrupt control register. */
ian@0 33 #define V850E_INTC_IC_MK_BIT 6
ian@0 34 #define V850E_INTC_IC_MK (1 << V850E_INTC_IC_MK_BIT)
ian@0 35 /* Interrupt pending flag in an interrupt control register. */
ian@0 36 #define V850E_INTC_IC_IF_BIT 7
ian@0 37 #define V850E_INTC_IC_IF (1 << V850E_INTC_IC_IF_BIT)
ian@0 38
ian@0 39 /* The ISPR (In-service priority register) contains one bit for each interrupt
ian@0 40 priority level, which is set to one when that level is currently being
ian@0 41 serviced (and thus blocking any interrupts of equal or lesser level). */
ian@0 42 #define V850E_INTC_ISPR_ADDR 0xFFFFF1FA
ian@0 43 #define V850E_INTC_ISPR (*(volatile u8 *)V850E_INTC_ISPR_ADDR)
ian@0 44
ian@0 45
ian@0 46 #ifndef __ASSEMBLY__
ian@0 47
ian@0 48 /* Enable interrupt handling for interrupt IRQ. */
ian@0 49 static inline void v850e_intc_enable_irq (unsigned irq)
ian@0 50 {
ian@0 51 __asm__ __volatile__ ("clr1 %0, [%1]"
ian@0 52 :: "r" (V850E_INTC_IMR_BIT (irq)),
ian@0 53 "r" (V850E_INTC_IMR_ADDR (irq))
ian@0 54 : "memory");
ian@0 55 }
ian@0 56
ian@0 57 /* Disable interrupt handling for interrupt IRQ. Note that any
ian@0 58 interrupts received while disabled will be delivered once the
ian@0 59 interrupt is enabled again, unless they are explicitly cleared using
ian@0 60 `v850e_intc_clear_pending_irq'. */
ian@0 61 static inline void v850e_intc_disable_irq (unsigned irq)
ian@0 62 {
ian@0 63 __asm__ __volatile__ ("set1 %0, [%1]"
ian@0 64 :: "r" (V850E_INTC_IMR_BIT (irq)),
ian@0 65 "r" (V850E_INTC_IMR_ADDR (irq))
ian@0 66 : "memory");
ian@0 67 }
ian@0 68
ian@0 69 /* Return true if interrupt handling for interrupt IRQ is enabled. */
ian@0 70 static inline int v850e_intc_irq_enabled (unsigned irq)
ian@0 71 {
ian@0 72 int rval;
ian@0 73 __asm__ __volatile__ ("tst1 %1, [%2]; setf z, %0"
ian@0 74 : "=r" (rval)
ian@0 75 : "r" (V850E_INTC_IMR_BIT (irq)),
ian@0 76 "r" (V850E_INTC_IMR_ADDR (irq)));
ian@0 77 return rval;
ian@0 78 }
ian@0 79
ian@0 80 /* Disable irqs from 0 until LIMIT. LIMIT must be a multiple of 8. */
ian@0 81 static inline void _v850e_intc_disable_irqs (unsigned limit)
ian@0 82 {
ian@0 83 unsigned long addr;
ian@0 84 for (addr = V850E_INTC_IMR_BASE_ADDR; limit >= 8; addr++, limit -= 8)
ian@0 85 *(char *)addr = 0xFF;
ian@0 86 }
ian@0 87
ian@0 88 /* Disable all irqs. This is purposely a macro, because NUM_MACH_IRQS
ian@0 89 will be only be defined later. */
ian@0 90 #define v850e_intc_disable_irqs() _v850e_intc_disable_irqs (NUM_MACH_IRQS)
ian@0 91
ian@0 92 /* Clear any pending interrupts for IRQ. */
ian@0 93 static inline void v850e_intc_clear_pending_irq (unsigned irq)
ian@0 94 {
ian@0 95 __asm__ __volatile__ ("clr1 %0, 0[%1]"
ian@0 96 :: "i" (V850E_INTC_IC_IF_BIT),
ian@0 97 "r" (V850E_INTC_IC_ADDR (irq))
ian@0 98 : "memory");
ian@0 99 }
ian@0 100
ian@0 101 /* Return true if interrupt IRQ is pending (but disabled). */
ian@0 102 static inline int v850e_intc_irq_pending (unsigned irq)
ian@0 103 {
ian@0 104 int rval;
ian@0 105 __asm__ __volatile__ ("tst1 %1, 0[%2]; setf nz, %0"
ian@0 106 : "=r" (rval)
ian@0 107 : "i" (V850E_INTC_IC_IF_BIT),
ian@0 108 "r" (V850E_INTC_IC_ADDR (irq)));
ian@0 109 return rval;
ian@0 110 }
ian@0 111
ian@0 112
ian@0 113 struct v850e_intc_irq_init {
ian@0 114 const char *name; /* name of interrupt type */
ian@0 115
ian@0 116 /* Range of kernel irq numbers for this type:
ian@0 117 BASE, BASE+INTERVAL, ..., BASE+INTERVAL*NUM */
ian@0 118 unsigned base, num, interval;
ian@0 119
ian@0 120 unsigned priority; /* interrupt priority to assign */
ian@0 121 };
ian@0 122 struct hw_interrupt_type; /* fwd decl */
ian@0 123
ian@0 124 /* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
ian@0 125 INITS (which is terminated by an entry with the name field == 0). */
ian@0 126 extern void v850e_intc_init_irq_types (struct v850e_intc_irq_init *inits,
ian@0 127 struct hw_interrupt_type *hw_irq_types);
ian@0 128
ian@0 129
ian@0 130 #endif /* !__ASSEMBLY__ */
ian@0 131
ian@0 132
ian@0 133 #endif /* __V850_V850E_INTC_H__ */