ia64/linux-2.6.18-xen.hg

annotate include/asm-v850/rte_mb_a_pci.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * include/asm-v850/mb_a_pci.h -- PCI support for Midas lab RTE-MOTHER-A board
ian@0 3 *
ian@0 4 * Copyright (C) 2001 NEC Corporation
ian@0 5 * Copyright (C) 2001 Miles Bader <miles@gnu.org>
ian@0 6 *
ian@0 7 * This file is subject to the terms and conditions of the GNU General
ian@0 8 * Public License. See the file COPYING in the main directory of this
ian@0 9 * archive for more details.
ian@0 10 *
ian@0 11 * Written by Miles Bader <miles@gnu.org>
ian@0 12 */
ian@0 13
ian@0 14 #ifndef __V850_MB_A_PCI_H__
ian@0 15 #define __V850_MB_A_PCI_H__
ian@0 16
ian@0 17
ian@0 18 #define MB_A_PCI_MEM_ADDR GCS5_ADDR
ian@0 19 #define MB_A_PCI_MEM_SIZE (GCS5_SIZE / 2)
ian@0 20 #define MB_A_PCI_IO_ADDR (GCS5_ADDR + MB_A_PCI_MEM_SIZE)
ian@0 21 #define MB_A_PCI_IO_SIZE (GCS5_SIZE / 2)
ian@0 22 #define MB_A_PCI_REG_BASE_ADDR GCS6_ADDR
ian@0 23
ian@0 24 #define MB_A_PCI_PCICR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x4)
ian@0 25 #define MB_A_PCI_PCICR (*(volatile u16 *)MB_A_PCI_PCICR_ADDR)
ian@0 26 #define MB_A_PCI_PCISR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x6)
ian@0 27 #define MB_A_PCI_PCISR (*(volatile u16 *)MB_A_PCI_PCISR_ADDR)
ian@0 28 #define MB_A_PCI_PCILTR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xD)
ian@0 29 #define MB_A_PCI_PCILTR (*(volatile u8 *)MB_A_PCI_PCILTR_ADDR)
ian@0 30 #define MB_A_PCI_PCIBAR0_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x10)
ian@0 31 #define MB_A_PCI_PCIBAR0 (*(volatile u32 *)MB_A_PCI_PCIBAR0_ADDR)
ian@0 32 #define MB_A_PCI_PCIBAR1_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x14)
ian@0 33 #define MB_A_PCI_PCIBAR1 (*(volatile u32 *)MB_A_PCI_PCIBAR1_ADDR)
ian@0 34 #define MB_A_PCI_PCIBAR2_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x18)
ian@0 35 #define MB_A_PCI_PCIBAR2 (*(volatile u32 *)MB_A_PCI_PCIBAR2_ADDR)
ian@0 36 #define MB_A_PCI_VENDOR_ID_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x2C)
ian@0 37 #define MB_A_PCI_VENDOR_ID (*(volatile u16 *)MB_A_PCI_VENDOR_ID_ADDR)
ian@0 38 #define MB_A_PCI_DEVICE_ID_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x2E)
ian@0 39 #define MB_A_PCI_DEVICE_ID (*(volatile u16 *)MB_A_PCI_DEVICE_ID_ADDR)
ian@0 40 #define MB_A_PCI_DMRR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x9C)
ian@0 41 #define MB_A_PCI_DMRR (*(volatile u32 *)MB_A_PCI_DMRR_ADDR)
ian@0 42 #define MB_A_PCI_DMLBAM_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xA0)
ian@0 43 #define MB_A_PCI_DMLBAM (*(volatile u32 *)MB_A_PCI_DMLBAM_ADDR)
ian@0 44 #define MB_A_PCI_DMLBAI_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xA4)
ian@0 45 #define MB_A_PCI_DMLBAI (*(volatile u32 *)MB_A_PCI_DMLBAI_ADDR)
ian@0 46 #define MB_A_PCI_PCIPBAM_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xA8)
ian@0 47 #define MB_A_PCI_PCIPBAM (*(volatile u32 *)MB_A_PCI_PCIPBAM_ADDR)
ian@0 48 /* `PCI Configuration Address Register for Direct Master to PCI IO/CFG' */
ian@0 49 #define MB_A_PCI_DMCFGA_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xAC)
ian@0 50 #define MB_A_PCI_DMCFGA (*(volatile u32 *)MB_A_PCI_DMCFGA_ADDR)
ian@0 51 /* `PCI Permanent Configuration ID Register' */
ian@0 52 #define MB_A_PCI_PCIHIDR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xF0)
ian@0 53 #define MB_A_PCI_PCIHIDR (*(volatile u32 *)MB_A_PCI_PCIHIDR_ADDR)
ian@0 54
ian@0 55
ian@0 56 #endif /* __V850_MB_A_PCI_H__ */