ia64/linux-2.6.18-xen.hg

annotate include/asm-v850/ma.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * include/asm-v850/ma.h -- V850E/MA series of cpu chips
ian@0 3 *
ian@0 4 * Copyright (C) 2001,02,03 NEC Electronics Corporation
ian@0 5 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
ian@0 6 *
ian@0 7 * This file is subject to the terms and conditions of the GNU General
ian@0 8 * Public License. See the file COPYING in the main directory of this
ian@0 9 * archive for more details.
ian@0 10 *
ian@0 11 * Written by Miles Bader <miles@gnu.org>
ian@0 12 */
ian@0 13
ian@0 14 #ifndef __V850_MA_H__
ian@0 15 #define __V850_MA_H__
ian@0 16
ian@0 17 /* The MA series uses the V850E cpu core. */
ian@0 18 #include <asm/v850e.h>
ian@0 19
ian@0 20
ian@0 21 /* For <asm/entry.h> */
ian@0 22 /* We use on-chip RAM, for a few miscellaneous variables that must be
ian@0 23 accessible using a load instruction relative to R0. The amount
ian@0 24 varies between chip models, but there's always at least 4K, and it
ian@0 25 should always start at FFFFC000. */
ian@0 26 #define R0_RAM_ADDR 0xFFFFC000
ian@0 27
ian@0 28
ian@0 29 /* MA series UART details. */
ian@0 30 #define V850E_UART_BASE_FREQ CPU_CLOCK_FREQ
ian@0 31
ian@0 32 /* This is a function that gets called before configuring the UART. */
ian@0 33 #define V850E_UART_PRE_CONFIGURE ma_uart_pre_configure
ian@0 34 #ifndef __ASSEMBLY__
ian@0 35 extern void ma_uart_pre_configure (unsigned chan,
ian@0 36 unsigned cflags, unsigned baud);
ian@0 37 #endif
ian@0 38
ian@0 39
ian@0 40 /* MA series timer C details. */
ian@0 41 #define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
ian@0 42
ian@0 43
ian@0 44 /* MA series timer D details. */
ian@0 45 #define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
ian@0 46 #define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
ian@0 47 #define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
ian@0 48 #define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
ian@0 49
ian@0 50 #define V850E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
ian@0 51
ian@0 52
ian@0 53 /* Port 0 */
ian@0 54 /* Direct I/O. Bits 0-7 are pins P00-P07. */
ian@0 55 #define MA_PORT0_IO_ADDR 0xFFFFF400
ian@0 56 #define MA_PORT0_IO (*(volatile u8 *)MA_PORT0_IO_ADDR)
ian@0 57 /* Port mode (for direct I/O, 0 = output, 1 = input). */
ian@0 58 #define MA_PORT0_PM_ADDR 0xFFFFF420
ian@0 59 #define MA_PORT0_PM (*(volatile u8 *)MA_PORT0_PM_ADDR)
ian@0 60 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
ian@0 61 #define MA_PORT0_PMC_ADDR 0xFFFFF440
ian@0 62 #define MA_PORT0_PMC (*(volatile u8 *)MA_PORT0_PMC_ADDR)
ian@0 63 /* Port function control (for P04-P07, 0 = IRQ, 1 = DMARQ). */
ian@0 64 #define MA_PORT0_PFC_ADDR 0xFFFFF460
ian@0 65 #define MA_PORT0_PFC (*(volatile u8 *)MA_PORT0_PFC_ADDR)
ian@0 66
ian@0 67 /* Port 1 */
ian@0 68 /* Direct I/O. Bits 0-3 are pins P10-P13. */
ian@0 69 #define MA_PORT1_IO_ADDR 0xFFFFF402
ian@0 70 #define MA_PORT1_IO (*(volatile u8 *)MA_PORT1_IO_ADDR)
ian@0 71 /* Port mode (for direct I/O, 0 = output, 1 = input). */
ian@0 72 #define MA_PORT1_PM_ADDR 0xFFFFF420
ian@0 73 #define MA_PORT1_PM (*(volatile u8 *)MA_PORT1_PM_ADDR)
ian@0 74 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
ian@0 75 #define MA_PORT1_PMC_ADDR 0xFFFFF442
ian@0 76 #define MA_PORT1_PMC (*(volatile u8 *)MA_PORT1_PMC_ADDR)
ian@0 77
ian@0 78 /* Port 4 */
ian@0 79 /* Direct I/O. Bits 0-5 are pins P40-P45. */
ian@0 80 #define MA_PORT4_IO_ADDR 0xFFFFF408
ian@0 81 #define MA_PORT4_IO (*(volatile u8 *)MA_PORT4_IO_ADDR)
ian@0 82 /* Port mode (for direct I/O, 0 = output, 1 = input). */
ian@0 83 #define MA_PORT4_PM_ADDR 0xFFFFF428
ian@0 84 #define MA_PORT4_PM (*(volatile u8 *)MA_PORT4_PM_ADDR)
ian@0 85 /* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
ian@0 86 #define MA_PORT4_PMC_ADDR 0xFFFFF448
ian@0 87 #define MA_PORT4_PMC (*(volatile u8 *)MA_PORT4_PMC_ADDR)
ian@0 88 /* Port function control (for serial interfaces, 0 = CSI, 1 = UART). */
ian@0 89 #define MA_PORT4_PFC_ADDR 0xFFFFF468
ian@0 90 #define MA_PORT4_PFC (*(volatile u8 *)MA_PORT4_PFC_ADDR)
ian@0 91
ian@0 92
ian@0 93 #ifndef __ASSEMBLY__
ian@0 94
ian@0 95 /* Initialize MA chip interrupts. */
ian@0 96 extern void ma_init_irqs (void);
ian@0 97
ian@0 98 #endif /* !__ASSEMBLY__ */
ian@0 99
ian@0 100
ian@0 101 #endif /* __V850_MA_H__ */