ia64/linux-2.6.18-xen.hg

annotate include/asm-m68knommu/m5272sim.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
rev   line source
ian@0 1 /****************************************************************************/
ian@0 2
ian@0 3 /*
ian@0 4 * m5272sim.h -- ColdFire 5272 System Integration Module support.
ian@0 5 *
ian@0 6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
ian@0 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
ian@0 8 */
ian@0 9
ian@0 10 /****************************************************************************/
ian@0 11 #ifndef m5272sim_h
ian@0 12 #define m5272sim_h
ian@0 13 /****************************************************************************/
ian@0 14
ian@0 15
ian@0 16 /*
ian@0 17 * Define the 5272 SIM register set addresses.
ian@0 18 */
ian@0 19 #define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
ian@0 20 #define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
ian@0 21 #define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
ian@0 22 #define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
ian@0 23 #define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
ian@0 24
ian@0 25 #define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
ian@0 26 #define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
ian@0 27 #define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
ian@0 28 #define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
ian@0 29
ian@0 30 #define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
ian@0 31 #define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
ian@0 32 #define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
ian@0 33 #define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
ian@0 34
ian@0 35 #define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
ian@0 36 #define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
ian@0 37 #define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
ian@0 38 #define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
ian@0 39
ian@0 40 #define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
ian@0 41 #define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
ian@0 42 #define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
ian@0 43 #define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
ian@0 44 #define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
ian@0 45 #define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
ian@0 46 #define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
ian@0 47 #define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
ian@0 48 #define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
ian@0 49 #define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
ian@0 50 #define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
ian@0 51 #define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
ian@0 52 #define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
ian@0 53 #define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
ian@0 54 #define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
ian@0 55 #define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
ian@0 56
ian@0 57 #define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
ian@0 58 #define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
ian@0 59 #define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
ian@0 60 #define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
ian@0 61 #define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
ian@0 62 #define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
ian@0 63 #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
ian@0 64 #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
ian@0 65
ian@0 66 #define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
ian@0 67 #define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
ian@0 68 #define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
ian@0 69 #define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
ian@0 70 #define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
ian@0 71 #define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
ian@0 72 #define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
ian@0 73 #define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
ian@0 74 #define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
ian@0 75
ian@0 76
ian@0 77 /****************************************************************************/
ian@0 78 #endif /* m5272sim_h */