ia64/linux-2.6.18-xen.hg

annotate include/asm-m32r/m32r.h @ 452:c7ed6fe5dca0

kexec: dont initialise regions in reserve_memory()

There is no need to initialise efi_memmap_res and boot_param_res in
reserve_memory() for the initial xen domain as it is done in
machine_kexec_setup_resources() using values from the kexec hypercall.

Signed-off-by: Simon Horman <horms@verge.net.au>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 28 10:55:18 2008 +0000 (2008-02-28)
parents 831230e53067
children
rev   line source
ian@0 1 #ifndef _ASM_M32R_M32R_H_
ian@0 2 #define _ASM_M32R_M32R_H_
ian@0 3
ian@0 4 /*
ian@0 5 * Renesas M32R processor
ian@0 6 *
ian@0 7 * Copyright (C) 2003, 2004 Renesas Technology Corp.
ian@0 8 */
ian@0 9
ian@0 10
ian@0 11 /* Chip type */
ian@0 12 #if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
ian@0 13 #include <asm/m32r_mp_fpga.h>
ian@0 14 #elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
ian@0 15 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
ian@0 16 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
ian@0 17 #include <asm/m32102.h>
ian@0 18 #endif
ian@0 19
ian@0 20 /* Platform type */
ian@0 21 #if defined(CONFIG_PLAT_M32700UT)
ian@0 22 #include <asm/m32700ut/m32700ut_pld.h>
ian@0 23 #include <asm/m32700ut/m32700ut_lan.h>
ian@0 24 #include <asm/m32700ut/m32700ut_lcd.h>
ian@0 25 #endif /* CONFIG_PLAT_M32700UT */
ian@0 26
ian@0 27 #if defined(CONFIG_PLAT_OPSPUT)
ian@0 28 #include <asm/opsput/opsput_pld.h>
ian@0 29 #include <asm/opsput/opsput_lan.h>
ian@0 30 #include <asm/opsput/opsput_lcd.h>
ian@0 31 #endif /* CONFIG_PLAT_OPSPUT */
ian@0 32
ian@0 33 #if defined(CONFIG_PLAT_MAPPI2)
ian@0 34 #include <asm/mappi2/mappi2_pld.h>
ian@0 35 #endif /* CONFIG_PLAT_MAPPI2 */
ian@0 36
ian@0 37 #if defined(CONFIG_PLAT_MAPPI3)
ian@0 38 #include <asm/mappi3/mappi3_pld.h>
ian@0 39 #endif /* CONFIG_PLAT_MAPPI3 */
ian@0 40
ian@0 41 #if defined(CONFIG_PLAT_USRV)
ian@0 42 #include <asm/m32700ut/m32700ut_pld.h>
ian@0 43 #endif
ian@0 44
ian@0 45 #if defined(CONFIG_PLAT_M32104UT)
ian@0 46 #include <asm/m32104ut/m32104ut_pld.h>
ian@0 47 #endif /* CONFIG_PLAT_M32104 */
ian@0 48
ian@0 49 /*
ian@0 50 * M32R Register
ian@0 51 */
ian@0 52
ian@0 53 /*
ian@0 54 * MMU Register
ian@0 55 */
ian@0 56
ian@0 57 #define MMU_REG_BASE (0xffff0000)
ian@0 58 #define ITLB_BASE (0xfe000000)
ian@0 59 #define DTLB_BASE (0xfe000800)
ian@0 60
ian@0 61 #define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES
ian@0 62
ian@0 63 #define MATM MMU_REG_BASE /* MMU Address Translation Mode
ian@0 64 Register */
ian@0 65 #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
ian@0 66 #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
ian@0 67 #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
ian@0 68 #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
ian@0 69 Address Register */
ian@0 70 #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
ian@0 71 Number Register */
ian@0 72 #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
ian@0 73 #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
ian@0 74 Register */
ian@0 75 #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
ian@0 76 #define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
ian@0 77 Instruciton */
ian@0 78 #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
ian@0 79
ian@0 80 #define MATM_offset (MATM - MMU_REG_BASE)
ian@0 81 #define MPSZ_offset (MPSZ - MMU_REG_BASE)
ian@0 82 #define MASID_offset (MASID - MMU_REG_BASE)
ian@0 83 #define MESTS_offset (MESTS - MMU_REG_BASE)
ian@0 84 #define MDEVA_offset (MDEVA - MMU_REG_BASE)
ian@0 85 #define MDEVP_offset (MDEVP - MMU_REG_BASE)
ian@0 86 #define MPTB_offset (MPTB - MMU_REG_BASE)
ian@0 87 #define MSVA_offset (MSVA - MMU_REG_BASE)
ian@0 88 #define MTOP_offset (MTOP - MMU_REG_BASE)
ian@0 89 #define MIDXI_offset (MIDXI - MMU_REG_BASE)
ian@0 90 #define MIDXD_offset (MIDXD - MMU_REG_BASE)
ian@0 91
ian@0 92 #define MESTS_IT (1 << 0) /* Instruction TLB miss */
ian@0 93 #define MESTS_IA (1 << 1) /* Instruction Access Exception */
ian@0 94 #define MESTS_DT (1 << 4) /* Operand TLB miss */
ian@0 95 #define MESTS_DA (1 << 5) /* Operand Access Exception */
ian@0 96 #define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */
ian@0 97
ian@0 98 /*
ian@0 99 * PSW (Processor Status Word)
ian@0 100 */
ian@0 101
ian@0 102 /* PSW bit */
ian@0 103 #define M32R_PSW_BIT_SM (7) /* Stack Mode */
ian@0 104 #define M32R_PSW_BIT_IE (6) /* Interrupt Enable */
ian@0 105 #define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
ian@0 106 #define M32R_PSW_BIT_C (0) /* Condition */
ian@0 107 #define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
ian@0 108 #define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */
ian@0 109 #define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
ian@0 110 #define M32R_PSW_BIT_BC (0+8) /* Backup Condition */
ian@0 111
ian@0 112 /* PSW bit map */
ian@0 113 #define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
ian@0 114 #define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */
ian@0 115 #define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
ian@0 116 #define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */
ian@0 117 #define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
ian@0 118 #define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */
ian@0 119 #define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
ian@0 120 #define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */
ian@0 121
ian@0 122 /*
ian@0 123 * Direct address to SFR
ian@0 124 */
ian@0 125
ian@0 126 #include <asm/page.h>
ian@0 127 #ifdef CONFIG_MMU
ian@0 128 #define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
ian@0 129 #else
ian@0 130 #define NONCACHE_OFFSET __PAGE_OFFSET
ian@0 131 #endif /* CONFIG_MMU */
ian@0 132
ian@0 133 #define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
ian@0 134 #define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
ian@0 135 #define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
ian@0 136 #define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
ian@0 137 #define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
ian@0 138 #define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
ian@0 139
ian@0 140 #endif /* _ASM_M32R_M32R_H_ */