ia64/linux-2.6.18-xen.hg

annotate arch/v850/kernel/v850e_cache.c @ 854:950b9eb27661

usbback: fix urb interval value for interrupt urbs.

Signed-off-by: Noboru Iwamatsu <n_iwamatsu@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Apr 06 13:51:20 2009 +0100 (2009-04-06)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * arch/v850/kernel/v850e_cache.c -- Cache control for V850E cache memories
ian@0 3 *
ian@0 4 * Copyright (C) 2003 NEC Electronics Corporation
ian@0 5 * Copyright (C) 2003 Miles Bader <miles@gnu.org>
ian@0 6 *
ian@0 7 * This file is subject to the terms and conditions of the GNU General
ian@0 8 * Public License. See the file COPYING in the main directory of this
ian@0 9 * archive for more details.
ian@0 10 *
ian@0 11 * Written by Miles Bader <miles@gnu.org>
ian@0 12 */
ian@0 13
ian@0 14 /* This file implements cache control for the rather simple cache used on
ian@0 15 some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
ian@0 16 CPU. V850E2 processors have their own (better) cache
ian@0 17 implementation. */
ian@0 18
ian@0 19 #include <asm/entry.h>
ian@0 20 #include <asm/cacheflush.h>
ian@0 21 #include <asm/v850e_cache.h>
ian@0 22
ian@0 23 #define WAIT_UNTIL_CLEAR(value) while (value) {}
ian@0 24
ian@0 25 /* Set caching params via the BHC and DCC registers. */
ian@0 26 void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc)
ian@0 27 {
ian@0 28 unsigned long *r0_ram = (unsigned long *)R0_RAM_ADDR;
ian@0 29 register u16 bhc_val asm ("r6") = bhc;
ian@0 30
ian@0 31 /* Read the instruction cache control register (ICC) and confirm
ian@0 32 that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
ian@0 33 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
ian@0 34 V850E_CACHE_ICC = icc;
ian@0 35
ian@0 36 #ifdef V850E_CACHE_DCC
ian@0 37 /* Configure data-cache. */
ian@0 38 V850E_CACHE_DCC = dcc;
ian@0 39 #endif /* V850E_CACHE_DCC */
ian@0 40
ian@0 41 /* Configure caching for various memory regions by writing the BHC
ian@0 42 register. The documentation says that an instruction _cannot_
ian@0 43 enable/disable caching for the memory region in which the
ian@0 44 instruction itself exists; to work around this, we store
ian@0 45 appropriate instructions into the on-chip RAM area (which is never
ian@0 46 cached), and briefly jump there to do the work. */
ian@0 47 #ifdef V850E_CACHE_WRITE_IBS
ian@0 48 *r0_ram++ = 0xf0720760; /* st.h r0, 0xfffff072[r0] */
ian@0 49 #endif
ian@0 50 *r0_ram++ = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
ian@0 51 *r0_ram = 0x5640006b; /* jmp [r11] */
ian@0 52
ian@0 53 asm ("mov hilo(1f), r11; jmp [%1]; 1:;"
ian@0 54 :: "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
ian@0 55 }
ian@0 56
ian@0 57 static void clear_icache (void)
ian@0 58 {
ian@0 59 /* 1. Read the instruction cache control register (ICC) and confirm
ian@0 60 that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
ian@0 61 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
ian@0 62
ian@0 63 /* 2. Read the ICC register and confirm that bit 12 (LOCK0) is
ian@0 64 cleared. Bit 13 of the ICC register is always cleared. */
ian@0 65 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x1000);
ian@0 66
ian@0 67 /* 3. Set the TCLR0 and TCLR1 bits of the ICC register as follows,
ian@0 68 when clearing way 0 and way 1 at the same time:
ian@0 69 (a) Set the TCLR0 and TCLR1 bits.
ian@0 70 (b) Read the TCLR0 and TCLR1 bits to confirm that these bits
ian@0 71 are cleared.
ian@0 72 (c) Perform (a) and (b) above again. */
ian@0 73 V850E_CACHE_ICC |= 0x3;
ian@0 74 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
ian@0 75
ian@0 76 #ifdef V850E_CACHE_REPEAT_ICC_WRITE
ian@0 77 /* Do it again. */
ian@0 78 V850E_CACHE_ICC |= 0x3;
ian@0 79 WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
ian@0 80 #endif
ian@0 81 }
ian@0 82
ian@0 83 #ifdef V850E_CACHE_DCC
ian@0 84 /* Flush or clear (or both) the data cache, depending on the value of FLAGS;
ian@0 85 the procedure is the same for both, just the control bits used differ (and
ian@0 86 both may be performed simultaneously). */
ian@0 87 static void dcache_op (unsigned short flags)
ian@0 88 {
ian@0 89 /* 1. Read the data cache control register (DCC) and confirm that bits
ian@0 90 0, 1, 4, and 5 (DC00, DC01, DC04, DC05) are all cleared. */
ian@0 91 WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & 0x33);
ian@0 92
ian@0 93 /* 2. Clear DCC register bit 12 (DC12), bit 13 (DC13), or both
ian@0 94 depending on the way for which tags are to be cleared. */
ian@0 95 V850E_CACHE_DCC &= ~0xC000;
ian@0 96
ian@0 97 /* 3. Set DCC register bit 0 (DC00), bit 1 (DC01) or both depending on
ian@0 98 the way for which tags are to be cleared.
ian@0 99 ...
ian@0 100 Set DCC register bit 4 (DC04), bit 5 (DC05), or both depending
ian@0 101 on the way to be data flushed. */
ian@0 102 V850E_CACHE_DCC |= flags;
ian@0 103
ian@0 104 /* 4. Read DCC register bit DC00, DC01 [DC04, DC05], or both depending
ian@0 105 on the way for which tags were cleared [flushed] and confirm
ian@0 106 that that bit is cleared. */
ian@0 107 WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & flags);
ian@0 108 }
ian@0 109 #endif /* V850E_CACHE_DCC */
ian@0 110
ian@0 111 /* Flushes the contents of the dcache to memory. */
ian@0 112 static inline void flush_dcache (void)
ian@0 113 {
ian@0 114 #ifdef V850E_CACHE_DCC
ian@0 115 /* We only need to do something if in write-back mode. */
ian@0 116 if (V850E_CACHE_DCC & 0x0400)
ian@0 117 dcache_op (0x30);
ian@0 118 #endif /* V850E_CACHE_DCC */
ian@0 119 }
ian@0 120
ian@0 121 /* Flushes the contents of the dcache to memory, and then clears it. */
ian@0 122 static inline void clear_dcache (void)
ian@0 123 {
ian@0 124 #ifdef V850E_CACHE_DCC
ian@0 125 /* We only need to do something if the dcache is enabled. */
ian@0 126 if (V850E_CACHE_DCC & 0x0C00)
ian@0 127 dcache_op (0x33);
ian@0 128 #endif /* V850E_CACHE_DCC */
ian@0 129 }
ian@0 130
ian@0 131 /* Clears the dcache without flushing to memory first. */
ian@0 132 static inline void clear_dcache_no_flush (void)
ian@0 133 {
ian@0 134 #ifdef V850E_CACHE_DCC
ian@0 135 /* We only need to do something if the dcache is enabled. */
ian@0 136 if (V850E_CACHE_DCC & 0x0C00)
ian@0 137 dcache_op (0x3);
ian@0 138 #endif /* V850E_CACHE_DCC */
ian@0 139 }
ian@0 140
ian@0 141 static inline void cache_exec_after_store (void)
ian@0 142 {
ian@0 143 flush_dcache ();
ian@0 144 clear_icache ();
ian@0 145 }
ian@0 146
ian@0 147
ian@0 148 /* Exported functions. */
ian@0 149
ian@0 150 void flush_icache (void)
ian@0 151 {
ian@0 152 cache_exec_after_store ();
ian@0 153 }
ian@0 154
ian@0 155 void flush_icache_range (unsigned long start, unsigned long end)
ian@0 156 {
ian@0 157 cache_exec_after_store ();
ian@0 158 }
ian@0 159
ian@0 160 void flush_icache_page (struct vm_area_struct *vma, struct page *page)
ian@0 161 {
ian@0 162 cache_exec_after_store ();
ian@0 163 }
ian@0 164
ian@0 165 void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
ian@0 166 unsigned long adr, int len)
ian@0 167 {
ian@0 168 cache_exec_after_store ();
ian@0 169 }
ian@0 170
ian@0 171 void flush_cache_sigtramp (unsigned long addr)
ian@0 172 {
ian@0 173 cache_exec_after_store ();
ian@0 174 }