ia64/linux-2.6.18-xen.hg

annotate drivers/net/smc911x.h @ 0:831230e53067

Import 2.6.18 from kernel.org tarball.
author Ian Campbell <ian.campbell@xensource.com>
date Wed Apr 11 14:15:44 2007 +0100 (2007-04-11)
parents
children
rev   line source
ian@0 1 /*------------------------------------------------------------------------
ian@0 2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
ian@0 3 .
ian@0 4 . Copyright (C) 2005 Sensoria Corp.
ian@0 5 . Derived from the unified SMC91x driver by Nicolas Pitre
ian@0 6 .
ian@0 7 . This program is free software; you can redistribute it and/or modify
ian@0 8 . it under the terms of the GNU General Public License as published by
ian@0 9 . the Free Software Foundation; either version 2 of the License, or
ian@0 10 . (at your option) any later version.
ian@0 11 .
ian@0 12 . This program is distributed in the hope that it will be useful,
ian@0 13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
ian@0 14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ian@0 15 . GNU General Public License for more details.
ian@0 16 .
ian@0 17 . You should have received a copy of the GNU General Public License
ian@0 18 . along with this program; if not, write to the Free Software
ian@0 19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ian@0 20 .
ian@0 21 . Information contained in this file was obtained from the LAN9118
ian@0 22 . manual from SMC. To get a copy, if you really want one, you can find
ian@0 23 . information under www.smsc.com.
ian@0 24 .
ian@0 25 . Authors
ian@0 26 . Dustin McIntire <dustin@sensoria.com>
ian@0 27 .
ian@0 28 ---------------------------------------------------------------------------*/
ian@0 29 #ifndef _SMC911X_H_
ian@0 30 #define _SMC911X_H_
ian@0 31
ian@0 32 /*
ian@0 33 * Use the DMA feature on PXA chips
ian@0 34 */
ian@0 35 #ifdef CONFIG_ARCH_PXA
ian@0 36 #define SMC_USE_PXA_DMA 1
ian@0 37 #define SMC_USE_16BIT 0
ian@0 38 #define SMC_USE_32BIT 1
ian@0 39 #endif
ian@0 40
ian@0 41
ian@0 42 /*
ian@0 43 * Define the bus width specific IO macros
ian@0 44 */
ian@0 45
ian@0 46 #if SMC_USE_16BIT
ian@0 47 #define SMC_inb(a, r) readb((a) + (r))
ian@0 48 #define SMC_inw(a, r) readw((a) + (r))
ian@0 49 #define SMC_inl(a, r) ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
ian@0 50 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
ian@0 51 #define SMC_outw(v, a, r) writew(v, (a) + (r))
ian@0 52 #define SMC_outl(v, a, r) \
ian@0 53 do{ \
ian@0 54 writel(v & 0xFFFF, (a) + (r)); \
ian@0 55 writel(v >> 16, (a) + (r) + 2); \
ian@0 56 } while (0)
ian@0 57 #define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2)
ian@0 58 #define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2)
ian@0 59
ian@0 60 #elif SMC_USE_32BIT
ian@0 61 #define SMC_inb(a, r) readb((a) + (r))
ian@0 62 #define SMC_inw(a, r) readw((a) + (r))
ian@0 63 #define SMC_inl(a, r) readl((a) + (r))
ian@0 64 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
ian@0 65 #define SMC_outl(v, a, r) writel(v, (a) + (r))
ian@0 66 #define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l)
ian@0 67 #define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l)
ian@0 68
ian@0 69 #endif /* SMC_USE_16BIT */
ian@0 70
ian@0 71
ian@0 72
ian@0 73 #if SMC_USE_PXA_DMA
ian@0 74 #define SMC_USE_DMA
ian@0 75
ian@0 76 /*
ian@0 77 * Define the request and free functions
ian@0 78 * These are unfortunately architecture specific as no generic allocation
ian@0 79 * mechanism exits
ian@0 80 */
ian@0 81 #define SMC_DMA_REQUEST(dev, handler) \
ian@0 82 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
ian@0 83
ian@0 84 #define SMC_DMA_FREE(dev, dma) \
ian@0 85 pxa_free_dma(dma)
ian@0 86
ian@0 87 #define SMC_DMA_ACK_IRQ(dev, dma) \
ian@0 88 { \
ian@0 89 if (DCSR(dma) & DCSR_BUSERR) { \
ian@0 90 printk("%s: DMA %d bus error!\n", dev->name, dma); \
ian@0 91 } \
ian@0 92 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
ian@0 93 }
ian@0 94
ian@0 95 /*
ian@0 96 * Use a DMA for RX and TX packets.
ian@0 97 */
ian@0 98 #include <linux/dma-mapping.h>
ian@0 99 #include <asm/dma.h>
ian@0 100 #include <asm/arch/pxa-regs.h>
ian@0 101
ian@0 102 static dma_addr_t rx_dmabuf, tx_dmabuf;
ian@0 103 static int rx_dmalen, tx_dmalen;
ian@0 104
ian@0 105 #ifdef SMC_insl
ian@0 106 #undef SMC_insl
ian@0 107 #define SMC_insl(a, r, p, l) \
ian@0 108 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
ian@0 109
ian@0 110 static inline void
ian@0 111 smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
ian@0 112 int reg, int dma, u_char *buf, int len)
ian@0 113 {
ian@0 114 /* 64 bit alignment is required for memory to memory DMA */
ian@0 115 if ((long)buf & 4) {
ian@0 116 *((u32 *)buf) = SMC_inl(ioaddr, reg);
ian@0 117 buf += 4;
ian@0 118 len--;
ian@0 119 }
ian@0 120
ian@0 121 len *= 4;
ian@0 122 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
ian@0 123 rx_dmalen = len;
ian@0 124 DCSR(dma) = DCSR_NODESC;
ian@0 125 DTADR(dma) = rx_dmabuf;
ian@0 126 DSADR(dma) = physaddr + reg;
ian@0 127 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
ian@0 128 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
ian@0 129 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
ian@0 130 }
ian@0 131 #endif
ian@0 132
ian@0 133 #ifdef SMC_insw
ian@0 134 #undef SMC_insw
ian@0 135 #define SMC_insw(a, r, p, l) \
ian@0 136 smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
ian@0 137
ian@0 138 static inline void
ian@0 139 smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
ian@0 140 int reg, int dma, u_char *buf, int len)
ian@0 141 {
ian@0 142 /* 64 bit alignment is required for memory to memory DMA */
ian@0 143 while ((long)buf & 6) {
ian@0 144 *((u16 *)buf) = SMC_inw(ioaddr, reg);
ian@0 145 buf += 2;
ian@0 146 len--;
ian@0 147 }
ian@0 148
ian@0 149 len *= 2;
ian@0 150 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
ian@0 151 rx_dmalen = len;
ian@0 152 DCSR(dma) = DCSR_NODESC;
ian@0 153 DTADR(dma) = rx_dmabuf;
ian@0 154 DSADR(dma) = physaddr + reg;
ian@0 155 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
ian@0 156 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
ian@0 157 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
ian@0 158 }
ian@0 159 #endif
ian@0 160
ian@0 161 #ifdef SMC_outsl
ian@0 162 #undef SMC_outsl
ian@0 163 #define SMC_outsl(a, r, p, l) \
ian@0 164 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
ian@0 165
ian@0 166 static inline void
ian@0 167 smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
ian@0 168 int reg, int dma, u_char *buf, int len)
ian@0 169 {
ian@0 170 /* 64 bit alignment is required for memory to memory DMA */
ian@0 171 if ((long)buf & 4) {
ian@0 172 SMC_outl(*((u32 *)buf), ioaddr, reg);
ian@0 173 buf += 4;
ian@0 174 len--;
ian@0 175 }
ian@0 176
ian@0 177 len *= 4;
ian@0 178 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
ian@0 179 tx_dmalen = len;
ian@0 180 DCSR(dma) = DCSR_NODESC;
ian@0 181 DSADR(dma) = tx_dmabuf;
ian@0 182 DTADR(dma) = physaddr + reg;
ian@0 183 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
ian@0 184 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
ian@0 185 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
ian@0 186 }
ian@0 187 #endif
ian@0 188
ian@0 189 #ifdef SMC_outsw
ian@0 190 #undef SMC_outsw
ian@0 191 #define SMC_outsw(a, r, p, l) \
ian@0 192 smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
ian@0 193
ian@0 194 static inline void
ian@0 195 smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
ian@0 196 int reg, int dma, u_char *buf, int len)
ian@0 197 {
ian@0 198 /* 64 bit alignment is required for memory to memory DMA */
ian@0 199 while ((long)buf & 6) {
ian@0 200 SMC_outw(*((u16 *)buf), ioaddr, reg);
ian@0 201 buf += 2;
ian@0 202 len--;
ian@0 203 }
ian@0 204
ian@0 205 len *= 2;
ian@0 206 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
ian@0 207 tx_dmalen = len;
ian@0 208 DCSR(dma) = DCSR_NODESC;
ian@0 209 DSADR(dma) = tx_dmabuf;
ian@0 210 DTADR(dma) = physaddr + reg;
ian@0 211 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
ian@0 212 DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
ian@0 213 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
ian@0 214 }
ian@0 215 #endif
ian@0 216
ian@0 217 #endif /* SMC_USE_PXA_DMA */
ian@0 218
ian@0 219
ian@0 220 /* Chip Parameters and Register Definitions */
ian@0 221
ian@0 222 #define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
ian@0 223
ian@0 224 #define SMC911X_IO_EXTENT 0x100
ian@0 225
ian@0 226 #define SMC911X_EEPROM_LEN 7
ian@0 227
ian@0 228 /* Below are the register offsets and bit definitions
ian@0 229 * of the Lan911x memory space
ian@0 230 */
ian@0 231 #define RX_DATA_FIFO (0x00)
ian@0 232
ian@0 233 #define TX_DATA_FIFO (0x20)
ian@0 234 #define TX_CMD_A_INT_ON_COMP_ (0x80000000)
ian@0 235 #define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
ian@0 236 #define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
ian@0 237 #define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
ian@0 238 #define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
ian@0 239 #define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
ian@0 240 #define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
ian@0 241 #define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
ian@0 242 #define TX_CMD_A_BUF_SIZE_ (0x000007FF)
ian@0 243 #define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
ian@0 244 #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
ian@0 245 #define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
ian@0 246 #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
ian@0 247
ian@0 248 #define RX_STATUS_FIFO (0x40)
ian@0 249 #define RX_STS_PKT_LEN_ (0x3FFF0000)
ian@0 250 #define RX_STS_ES_ (0x00008000)
ian@0 251 #define RX_STS_BCST_ (0x00002000)
ian@0 252 #define RX_STS_LEN_ERR_ (0x00001000)
ian@0 253 #define RX_STS_RUNT_ERR_ (0x00000800)
ian@0 254 #define RX_STS_MCAST_ (0x00000400)
ian@0 255 #define RX_STS_TOO_LONG_ (0x00000080)
ian@0 256 #define RX_STS_COLL_ (0x00000040)
ian@0 257 #define RX_STS_ETH_TYPE_ (0x00000020)
ian@0 258 #define RX_STS_WDOG_TMT_ (0x00000010)
ian@0 259 #define RX_STS_MII_ERR_ (0x00000008)
ian@0 260 #define RX_STS_DRIBBLING_ (0x00000004)
ian@0 261 #define RX_STS_CRC_ERR_ (0x00000002)
ian@0 262 #define RX_STATUS_FIFO_PEEK (0x44)
ian@0 263 #define TX_STATUS_FIFO (0x48)
ian@0 264 #define TX_STS_TAG_ (0xFFFF0000)
ian@0 265 #define TX_STS_ES_ (0x00008000)
ian@0 266 #define TX_STS_LOC_ (0x00000800)
ian@0 267 #define TX_STS_NO_CARR_ (0x00000400)
ian@0 268 #define TX_STS_LATE_COLL_ (0x00000200)
ian@0 269 #define TX_STS_MANY_COLL_ (0x00000100)
ian@0 270 #define TX_STS_COLL_CNT_ (0x00000078)
ian@0 271 #define TX_STS_MANY_DEFER_ (0x00000004)
ian@0 272 #define TX_STS_UNDERRUN_ (0x00000002)
ian@0 273 #define TX_STS_DEFERRED_ (0x00000001)
ian@0 274 #define TX_STATUS_FIFO_PEEK (0x4C)
ian@0 275 #define ID_REV (0x50)
ian@0 276 #define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
ian@0 277 #define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
ian@0 278
ian@0 279 #define INT_CFG (0x54)
ian@0 280 #define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
ian@0 281 #define INT_CFG_INT_DEAS_CLR_ (0x00004000)
ian@0 282 #define INT_CFG_INT_DEAS_STS_ (0x00002000)
ian@0 283 #define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
ian@0 284 #define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
ian@0 285 #define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
ian@0 286 #define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
ian@0 287
ian@0 288 #define INT_STS (0x58)
ian@0 289 #define INT_STS_SW_INT_ (0x80000000) /* R/WC */
ian@0 290 #define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
ian@0 291 #define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
ian@0 292 #define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
ian@0 293 #define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
ian@0 294 #define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
ian@0 295 #define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
ian@0 296 #define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
ian@0 297 #define INT_STS_PHY_INT_ (0x00040000) /* RO */
ian@0 298 #define INT_STS_PME_INT_ (0x00020000) /* R/WC */
ian@0 299 #define INT_STS_TXSO_ (0x00010000) /* R/WC */
ian@0 300 #define INT_STS_RWT_ (0x00008000) /* R/WC */
ian@0 301 #define INT_STS_RXE_ (0x00004000) /* R/WC */
ian@0 302 #define INT_STS_TXE_ (0x00002000) /* R/WC */
ian@0 303 //#define INT_STS_ERX_ (0x00001000) /* R/WC */
ian@0 304 #define INT_STS_TDFU_ (0x00000800) /* R/WC */
ian@0 305 #define INT_STS_TDFO_ (0x00000400) /* R/WC */
ian@0 306 #define INT_STS_TDFA_ (0x00000200) /* R/WC */
ian@0 307 #define INT_STS_TSFF_ (0x00000100) /* R/WC */
ian@0 308 #define INT_STS_TSFL_ (0x00000080) /* R/WC */
ian@0 309 //#define INT_STS_RXDF_ (0x00000040) /* R/WC */
ian@0 310 #define INT_STS_RDFO_ (0x00000040) /* R/WC */
ian@0 311 #define INT_STS_RDFL_ (0x00000020) /* R/WC */
ian@0 312 #define INT_STS_RSFF_ (0x00000010) /* R/WC */
ian@0 313 #define INT_STS_RSFL_ (0x00000008) /* R/WC */
ian@0 314 #define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
ian@0 315 #define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
ian@0 316 #define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
ian@0 317
ian@0 318 #define INT_EN (0x5C)
ian@0 319 #define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
ian@0 320 #define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
ian@0 321 #define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
ian@0 322 #define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
ian@0 323 //#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
ian@0 324 #define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
ian@0 325 #define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
ian@0 326 #define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
ian@0 327 #define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
ian@0 328 #define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
ian@0 329 #define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
ian@0 330 #define INT_EN_RWT_EN_ (0x00008000) /* R/W */
ian@0 331 #define INT_EN_RXE_EN_ (0x00004000) /* R/W */
ian@0 332 #define INT_EN_TXE_EN_ (0x00002000) /* R/W */
ian@0 333 //#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
ian@0 334 #define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
ian@0 335 #define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
ian@0 336 #define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
ian@0 337 #define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
ian@0 338 #define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
ian@0 339 //#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
ian@0 340 #define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
ian@0 341 #define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
ian@0 342 #define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
ian@0 343 #define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
ian@0 344 #define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
ian@0 345 #define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
ian@0 346 #define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
ian@0 347
ian@0 348 #define BYTE_TEST (0x64)
ian@0 349 #define FIFO_INT (0x68)
ian@0 350 #define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
ian@0 351 #define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
ian@0 352 #define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
ian@0 353 #define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
ian@0 354
ian@0 355 #define RX_CFG (0x6C)
ian@0 356 #define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
ian@0 357 #define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
ian@0 358 #define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
ian@0 359 #define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
ian@0 360 #define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
ian@0 361 #define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
ian@0 362 #define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
ian@0 363 //#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
ian@0 364
ian@0 365 #define TX_CFG (0x70)
ian@0 366 //#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
ian@0 367 //#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
ian@0 368 #define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
ian@0 369 #define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
ian@0 370 #define TX_CFG_TXSAO_ (0x00000004) /* R/W */
ian@0 371 #define TX_CFG_TX_ON_ (0x00000002) /* R/W */
ian@0 372 #define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
ian@0 373
ian@0 374 #define HW_CFG (0x74)
ian@0 375 #define HW_CFG_TTM_ (0x00200000) /* R/W */
ian@0 376 #define HW_CFG_SF_ (0x00100000) /* R/W */
ian@0 377 #define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
ian@0 378 #define HW_CFG_TR_ (0x00003000) /* R/W */
ian@0 379 #define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
ian@0 380 #define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
ian@0 381 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
ian@0 382 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
ian@0 383 #define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
ian@0 384 #define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
ian@0 385 #define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
ian@0 386 #define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
ian@0 387 #define HW_CFG_SRST_TO_ (0x00000002) /* RO */
ian@0 388 #define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
ian@0 389
ian@0 390 #define RX_DP_CTRL (0x78)
ian@0 391 #define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
ian@0 392 #define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
ian@0 393
ian@0 394 #define RX_FIFO_INF (0x7C)
ian@0 395 #define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
ian@0 396 #define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
ian@0 397
ian@0 398 #define TX_FIFO_INF (0x80)
ian@0 399 #define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
ian@0 400 #define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
ian@0 401
ian@0 402 #define PMT_CTRL (0x84)
ian@0 403 #define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
ian@0 404 #define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
ian@0 405 #define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
ian@0 406 #define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
ian@0 407 #define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
ian@0 408 #define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
ian@0 409 #define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
ian@0 410 #define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
ian@0 411 #define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
ian@0 412 #define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
ian@0 413 #define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
ian@0 414 #define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
ian@0 415 #define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
ian@0 416 #define PMT_CTRL_READY_ (0x00000001) /* RO */
ian@0 417
ian@0 418 #define GPIO_CFG (0x88)
ian@0 419 #define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
ian@0 420 #define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
ian@0 421 #define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
ian@0 422 #define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
ian@0 423 #define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
ian@0 424 #define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
ian@0 425 #define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
ian@0 426 #define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
ian@0 427 #define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
ian@0 428 #define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
ian@0 429 #define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
ian@0 430 #define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
ian@0 431 #define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
ian@0 432 #define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
ian@0 433 #define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
ian@0 434 #define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
ian@0 435 #define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
ian@0 436 #define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
ian@0 437
ian@0 438 #define GPT_CFG (0x8C)
ian@0 439 #define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
ian@0 440 #define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
ian@0 441
ian@0 442 #define GPT_CNT (0x90)
ian@0 443 #define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
ian@0 444
ian@0 445 #define ENDIAN (0x98)
ian@0 446 #define FREE_RUN (0x9C)
ian@0 447 #define RX_DROP (0xA0)
ian@0 448 #define MAC_CSR_CMD (0xA4)
ian@0 449 #define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
ian@0 450 #define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
ian@0 451 #define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
ian@0 452
ian@0 453 #define MAC_CSR_DATA (0xA8)
ian@0 454 #define AFC_CFG (0xAC)
ian@0 455 #define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
ian@0 456 #define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
ian@0 457 #define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
ian@0 458 #define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
ian@0 459 #define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
ian@0 460 #define AFC_CFG_FCADD_ (0x00000002) /* R/W */
ian@0 461 #define AFC_CFG_FCANY_ (0x00000001) /* R/W */
ian@0 462
ian@0 463 #define E2P_CMD (0xB0)
ian@0 464 #define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
ian@0 465 #define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
ian@0 466 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
ian@0 467 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
ian@0 468 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
ian@0 469 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
ian@0 470 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
ian@0 471 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
ian@0 472 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
ian@0 473 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
ian@0 474 #define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
ian@0 475 #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
ian@0 476 #define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
ian@0 477
ian@0 478 #define E2P_DATA (0xB4)
ian@0 479 #define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
ian@0 480 /* end of LAN register offsets and bit definitions */
ian@0 481
ian@0 482 /*
ian@0 483 ****************************************************************************
ian@0 484 ****************************************************************************
ian@0 485 * MAC Control and Status Register (Indirect Address)
ian@0 486 * Offset (through the MAC_CSR CMD and DATA port)
ian@0 487 ****************************************************************************
ian@0 488 ****************************************************************************
ian@0 489 *
ian@0 490 */
ian@0 491 #define MAC_CR (0x01) /* R/W */
ian@0 492
ian@0 493 /* MAC_CR - MAC Control Register */
ian@0 494 #define MAC_CR_RXALL_ (0x80000000)
ian@0 495 // TODO: delete this bit? It is not described in the data sheet.
ian@0 496 #define MAC_CR_HBDIS_ (0x10000000)
ian@0 497 #define MAC_CR_RCVOWN_ (0x00800000)
ian@0 498 #define MAC_CR_LOOPBK_ (0x00200000)
ian@0 499 #define MAC_CR_FDPX_ (0x00100000)
ian@0 500 #define MAC_CR_MCPAS_ (0x00080000)
ian@0 501 #define MAC_CR_PRMS_ (0x00040000)
ian@0 502 #define MAC_CR_INVFILT_ (0x00020000)
ian@0 503 #define MAC_CR_PASSBAD_ (0x00010000)
ian@0 504 #define MAC_CR_HFILT_ (0x00008000)
ian@0 505 #define MAC_CR_HPFILT_ (0x00002000)
ian@0 506 #define MAC_CR_LCOLL_ (0x00001000)
ian@0 507 #define MAC_CR_BCAST_ (0x00000800)
ian@0 508 #define MAC_CR_DISRTY_ (0x00000400)
ian@0 509 #define MAC_CR_PADSTR_ (0x00000100)
ian@0 510 #define MAC_CR_BOLMT_MASK_ (0x000000C0)
ian@0 511 #define MAC_CR_DFCHK_ (0x00000020)
ian@0 512 #define MAC_CR_TXEN_ (0x00000008)
ian@0 513 #define MAC_CR_RXEN_ (0x00000004)
ian@0 514
ian@0 515 #define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
ian@0 516 #define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
ian@0 517 #define HASHH (0x04) /* R/W */
ian@0 518 #define HASHL (0x05) /* R/W */
ian@0 519
ian@0 520 #define MII_ACC (0x06) /* R/W */
ian@0 521 #define MII_ACC_PHY_ADDR_ (0x0000F800)
ian@0 522 #define MII_ACC_MIIRINDA_ (0x000007C0)
ian@0 523 #define MII_ACC_MII_WRITE_ (0x00000002)
ian@0 524 #define MII_ACC_MII_BUSY_ (0x00000001)
ian@0 525
ian@0 526 #define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
ian@0 527
ian@0 528 #define FLOW (0x08) /* R/W */
ian@0 529 #define FLOW_FCPT_ (0xFFFF0000)
ian@0 530 #define FLOW_FCPASS_ (0x00000004)
ian@0 531 #define FLOW_FCEN_ (0x00000002)
ian@0 532 #define FLOW_FCBSY_ (0x00000001)
ian@0 533
ian@0 534 #define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
ian@0 535 #define VLAN1_VTI1_ (0x0000ffff)
ian@0 536
ian@0 537 #define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
ian@0 538 #define VLAN2_VTI2_ (0x0000ffff)
ian@0 539
ian@0 540 #define WUFF (0x0B) /* WO */
ian@0 541
ian@0 542 #define WUCSR (0x0C) /* R/W */
ian@0 543 #define WUCSR_GUE_ (0x00000200)
ian@0 544 #define WUCSR_WUFR_ (0x00000040)
ian@0 545 #define WUCSR_MPR_ (0x00000020)
ian@0 546 #define WUCSR_WAKE_EN_ (0x00000004)
ian@0 547 #define WUCSR_MPEN_ (0x00000002)
ian@0 548
ian@0 549 /*
ian@0 550 ****************************************************************************
ian@0 551 * Chip Specific MII Defines
ian@0 552 ****************************************************************************
ian@0 553 *
ian@0 554 * Phy register offsets and bit definitions
ian@0 555 *
ian@0 556 */
ian@0 557
ian@0 558 #define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
ian@0 559 //#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
ian@0 560 #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
ian@0 561 //#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
ian@0 562 //#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
ian@0 563 //#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
ian@0 564 //#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
ian@0 565 //#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
ian@0 566 //#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
ian@0 567 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
ian@0 568 #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
ian@0 569
ian@0 570 #define PHY_INT_SRC ((u32)29)
ian@0 571 #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
ian@0 572 #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
ian@0 573 #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
ian@0 574 #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
ian@0 575 #define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
ian@0 576 #define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
ian@0 577 #define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
ian@0 578
ian@0 579 #define PHY_INT_MASK ((u32)30)
ian@0 580 #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
ian@0 581 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
ian@0 582 #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
ian@0 583 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
ian@0 584 #define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
ian@0 585 #define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
ian@0 586 #define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
ian@0 587
ian@0 588 #define PHY_SPECIAL ((u32)31)
ian@0 589 #define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
ian@0 590 #define PHY_SPECIAL_RES_ ((u16)0x0040)
ian@0 591 #define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
ian@0 592 #define PHY_SPECIAL_SPD_ ((u16)0x001C)
ian@0 593 #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
ian@0 594 #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
ian@0 595 #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
ian@0 596 #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
ian@0 597
ian@0 598 #define LAN911X_INTERNAL_PHY_ID (0x0007C000)
ian@0 599
ian@0 600 /* Chip ID values */
ian@0 601 #define CHIP_9115 0x115
ian@0 602 #define CHIP_9116 0x116
ian@0 603 #define CHIP_9117 0x117
ian@0 604 #define CHIP_9118 0x118
ian@0 605
ian@0 606 struct chip_id {
ian@0 607 u16 id;
ian@0 608 char *name;
ian@0 609 };
ian@0 610
ian@0 611 static const struct chip_id chip_ids[] = {
ian@0 612 { CHIP_9115, "LAN9115" },
ian@0 613 { CHIP_9116, "LAN9116" },
ian@0 614 { CHIP_9117, "LAN9117" },
ian@0 615 { CHIP_9118, "LAN9118" },
ian@0 616 { 0, NULL },
ian@0 617 };
ian@0 618
ian@0 619 #define IS_REV_A(x) ((x & 0xFFFF)==0)
ian@0 620
ian@0 621 /*
ian@0 622 * Macros to abstract register access according to the data bus
ian@0 623 * capabilities. Please use those and not the in/out primitives.
ian@0 624 */
ian@0 625 /* FIFO read/write macros */
ian@0 626 #define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
ian@0 627 #define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
ian@0 628 #define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO )
ian@0 629 #define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO )
ian@0 630
ian@0 631
ian@0 632 /* I/O mapped register read/write macros */
ian@0 633 #define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO )
ian@0 634 #define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO )
ian@0 635 #define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
ian@0 636 #define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16)
ian@0 637 #define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
ian@0 638 #define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG )
ian@0 639 #define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG )
ian@0 640 #define SMC_GET_INT() SMC_inl( ioaddr, INT_STS )
ian@0 641 #define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS )
ian@0 642 #define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN )
ian@0 643 #define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN )
ian@0 644 #define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST )
ian@0 645 #define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST )
ian@0 646 #define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT )
ian@0 647 #define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT )
ian@0 648 #define SMC_SET_FIFO_TDA(x) \
ian@0 649 do { \
ian@0 650 unsigned long __flags; \
ian@0 651 int __mask; \
ian@0 652 local_irq_save(__flags); \
ian@0 653 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \
ian@0 654 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \
ian@0 655 local_irq_restore(__flags); \
ian@0 656 } while (0)
ian@0 657 #define SMC_SET_FIFO_TSL(x) \
ian@0 658 do { \
ian@0 659 unsigned long __flags; \
ian@0 660 int __mask; \
ian@0 661 local_irq_save(__flags); \
ian@0 662 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \
ian@0 663 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
ian@0 664 local_irq_restore(__flags); \
ian@0 665 } while (0)
ian@0 666 #define SMC_SET_FIFO_RSA(x) \
ian@0 667 do { \
ian@0 668 unsigned long __flags; \
ian@0 669 int __mask; \
ian@0 670 local_irq_save(__flags); \
ian@0 671 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \
ian@0 672 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \
ian@0 673 local_irq_restore(__flags); \
ian@0 674 } while (0)
ian@0 675 #define SMC_SET_FIFO_RSL(x) \
ian@0 676 do { \
ian@0 677 unsigned long __flags; \
ian@0 678 int __mask; \
ian@0 679 local_irq_save(__flags); \
ian@0 680 __mask = SMC_GET_FIFO_INT() & ~0xFF; \
ian@0 681 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \
ian@0 682 local_irq_restore(__flags); \
ian@0 683 } while (0)
ian@0 684 #define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG )
ian@0 685 #define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG )
ian@0 686 #define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG )
ian@0 687 #define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG )
ian@0 688 #define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG )
ian@0 689 #define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG )
ian@0 690 #define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL )
ian@0 691 #define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL )
ian@0 692 #define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL )
ian@0 693 #define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL )
ian@0 694 #define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG )
ian@0 695 #define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG )
ian@0 696 #define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF )
ian@0 697 #define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF )
ian@0 698 #define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF )
ian@0 699 #define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF )
ian@0 700 #define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG )
ian@0 701 #define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG )
ian@0 702 #define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP )
ian@0 703 #define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP )
ian@0 704 #define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD )
ian@0 705 #define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD )
ian@0 706 #define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA )
ian@0 707 #define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA )
ian@0 708 #define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG )
ian@0 709 #define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG )
ian@0 710 #define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD )
ian@0 711 #define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD )
ian@0 712 #define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA )
ian@0 713 #define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA )
ian@0 714
ian@0 715 /* MAC register read/write macros */
ian@0 716 #define SMC_GET_MAC_CSR(a,v) \
ian@0 717 do { \
ian@0 718 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
ian@0 719 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \
ian@0 720 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
ian@0 721 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
ian@0 722 v = SMC_GET_MAC_DATA(); \
ian@0 723 } while (0)
ian@0 724 #define SMC_SET_MAC_CSR(a,v) \
ian@0 725 do { \
ian@0 726 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
ian@0 727 SMC_SET_MAC_DATA(v); \
ian@0 728 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
ian@0 729 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
ian@0 730 } while (0)
ian@0 731 #define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x )
ian@0 732 #define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x )
ian@0 733 #define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x )
ian@0 734 #define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x )
ian@0 735 #define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x )
ian@0 736 #define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x )
ian@0 737 #define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x )
ian@0 738 #define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x )
ian@0 739 #define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x )
ian@0 740 #define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x )
ian@0 741 #define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x )
ian@0 742 #define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x )
ian@0 743 #define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x )
ian@0 744 #define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x )
ian@0 745 #define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x )
ian@0 746 #define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x )
ian@0 747 #define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x )
ian@0 748 #define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x )
ian@0 749 #define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x )
ian@0 750 #define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x )
ian@0 751 #define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x )
ian@0 752 #define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x )
ian@0 753 #define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x )
ian@0 754
ian@0 755 /* PHY register read/write macros */
ian@0 756 #define SMC_GET_MII(a,phy,v) \
ian@0 757 do { \
ian@0 758 u32 __v; \
ian@0 759 do { \
ian@0 760 SMC_GET_MII_ACC(__v); \
ian@0 761 } while ( __v & MII_ACC_MII_BUSY_ ); \
ian@0 762 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
ian@0 763 MII_ACC_MII_BUSY_); \
ian@0 764 do { \
ian@0 765 SMC_GET_MII_ACC(__v); \
ian@0 766 } while ( __v & MII_ACC_MII_BUSY_ ); \
ian@0 767 SMC_GET_MII_DATA(v); \
ian@0 768 } while (0)
ian@0 769 #define SMC_SET_MII(a,phy,v) \
ian@0 770 do { \
ian@0 771 u32 __v; \
ian@0 772 do { \
ian@0 773 SMC_GET_MII_ACC(__v); \
ian@0 774 } while ( __v & MII_ACC_MII_BUSY_ ); \
ian@0 775 SMC_SET_MII_DATA(v); \
ian@0 776 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \
ian@0 777 MII_ACC_MII_BUSY_ | \
ian@0 778 MII_ACC_MII_WRITE_ ); \
ian@0 779 do { \
ian@0 780 SMC_GET_MII_ACC(__v); \
ian@0 781 } while ( __v & MII_ACC_MII_BUSY_ ); \
ian@0 782 } while (0)
ian@0 783 #define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x )
ian@0 784 #define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x )
ian@0 785 #define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x )
ian@0 786 #define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x )
ian@0 787 #define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x )
ian@0 788 #define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x )
ian@0 789 #define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x )
ian@0 790 #define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x )
ian@0 791 #define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x )
ian@0 792 #define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x )
ian@0 793 #define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x )
ian@0 794 #define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x )
ian@0 795 #define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x )
ian@0 796 #define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x )
ian@0 797 #define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x )
ian@0 798 #define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x )
ian@0 799
ian@0 800
ian@0 801
ian@0 802 /* Misc read/write macros */
ian@0 803
ian@0 804 #ifndef SMC_GET_MAC_ADDR
ian@0 805 #define SMC_GET_MAC_ADDR(addr) \
ian@0 806 do { \
ian@0 807 unsigned int __v; \
ian@0 808 \
ian@0 809 SMC_GET_MAC_CSR(ADDRL, __v); \
ian@0 810 addr[0] = __v; addr[1] = __v >> 8; \
ian@0 811 addr[2] = __v >> 16; addr[3] = __v >> 24; \
ian@0 812 SMC_GET_MAC_CSR(ADDRH, __v); \
ian@0 813 addr[4] = __v; addr[5] = __v >> 8; \
ian@0 814 } while (0)
ian@0 815 #endif
ian@0 816
ian@0 817 #define SMC_SET_MAC_ADDR(addr) \
ian@0 818 do { \
ian@0 819 SMC_SET_MAC_CSR(ADDRL, \
ian@0 820 addr[0] | \
ian@0 821 (addr[1] << 8) | \
ian@0 822 (addr[2] << 16) | \
ian@0 823 (addr[3] << 24)); \
ian@0 824 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\
ian@0 825 } while (0)
ian@0 826
ian@0 827
ian@0 828 #define SMC_WRITE_EEPROM_CMD(cmd, addr) \
ian@0 829 do { \
ian@0 830 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
ian@0 831 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \
ian@0 832 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \
ian@0 833 } while (0)
ian@0 834
ian@0 835 #endif /* _SMC911X_H_ */