annotate Documentation/voyager.txt @ 524:7f8b544237bf

netfront: Allow netfront in domain 0.

This is useful if your physical network device is in a utility domain.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Apr 15 15:18:58 2008 +0100 (2008-04-15)
parents 831230e53067
rev   line source
ian@0 1 Running Linux on the Voyager Architecture
ian@0 2 =========================================
ian@0 3
ian@0 4 For full details and current project status, see
ian@0 5
ian@0 6 http://www.hansenpartnership.com/voyager
ian@0 7
ian@0 8 The voyager architecture was designed by NCR in the mid 80s to be a
ian@0 9 fully SMP capable RAS computing architecture built around intel's 486
ian@0 10 chip set. The voyager came in three levels of architectural
ian@0 11 sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype.
ian@0 12 The linux patches support only the Level 5 voyager architecture (any
ian@0 13 machine class 3435 and above).
ian@0 14
ian@0 15 The Voyager Architecture
ian@0 16 ------------------------
ian@0 17
ian@0 18 Voyager machines consist of a Baseboard with a 386 diagnostic
ian@0 19 processor, a Power Supply Interface (PSI) a Primary and possibly
ian@0 20 Secondary Microchannel bus and between 2 and 20 voyager slots. The
ian@0 21 voyager slots can be populated with memory and cpu cards (up to 4GB
ian@0 22 memory and from 1 486 to 32 Pentium Pro processors). Internally, the
ian@0 23 voyager has a dual arbitrated system bus and a configuration and test
ian@0 24 bus (CAT). The voyager bus speed is 40MHz. Therefore (since all
ian@0 25 voyager cards are dual ported for each system bus) the maximum
ian@0 26 transfer rate is 320Mb/s but only if you have your slot configuration
ian@0 27 tuned (only memory cards can communicate with both busses at once, CPU
ian@0 28 cards utilise them one at a time).
ian@0 29
ian@0 30 Voyager SMP
ian@0 31 -----------
ian@0 32
ian@0 33 Since voyager was the first intel based SMP system, it is slightly
ian@0 34 more primitive than the Intel IO-APIC approach to SMP. Voyager allows
ian@0 35 arbitrary interrupt routing (including processor affinity routing) of
ian@0 36 all 16 PC type interrupts. However it does this by using a modified
ian@0 37 5259 master/slave chip set instead of an APIC bus. Additionally,
ian@0 38 voyager supports Cross Processor Interrupts (CPI) equivalent to the
ian@0 39 APIC IPIs. There are two routed voyager interrupt lines provided to
ian@0 40 each slot.
ian@0 41
ian@0 42 Processor Cards
ian@0 43 ---------------
ian@0 44
ian@0 45 These come in single, dyadic and quad configurations (the quads are
ian@0 46 problematic--see later). The maximum configuration is 8 quad cards
ian@0 47 for 32 way SMP.
ian@0 48
ian@0 49 Quad Processors
ian@0 50 ---------------
ian@0 51
ian@0 52 Because voyager only supplies two interrupt lines to each Processor
ian@0 53 card, the Quad processors have to be configured (and Bootstrapped) in
ian@0 54 as a pair of Master/Slave processors.
ian@0 55
ian@0 56 In fact, most Quad cards only accept one VIC interrupt line, so they
ian@0 57 have one interrupt handling processor (called the VIC extended
ian@0 58 processor) and three non-interrupt handling processors.
ian@0 59
ian@0 60 Current Status
ian@0 61 --------------
ian@0 62
ian@0 63 The System will boot on Mono, Dyad and Quad cards. There was
ian@0 64 originally a Quad boot problem which has been fixed by proper gdt
ian@0 65 alignment in the initial boot loader. If you still cannot get your
ian@0 66 voyager system to boot, email me at:
ian@0 67
ian@0 68 <J.E.J.Bottomley@HansenPartnership.com>
ian@0 69
ian@0 70
ian@0 71 The Quad cards now support using the separate Quad CPI vectors instead
ian@0 72 of going through the VIC mailbox system.
ian@0 73
ian@0 74 The Level 4 architecture (3430 and 3360 Machines) should also work
ian@0 75 fine.
ian@0 76
ian@0 77 Dump Switch
ian@0 78 -----------
ian@0 79
ian@0 80 The voyager dump switch sends out a broadcast NMI which the voyager
ian@0 81 code intercepts and does a task dump.
ian@0 82
ian@0 83 Power Switch
ian@0 84 ------------
ian@0 85
ian@0 86 The front panel power switch is intercepted by the kernel and should
ian@0 87 cause a system shutdown and power off.
ian@0 88
ian@0 89 A Note About Mixed CPU Systems
ian@0 90 ------------------------------
ian@0 91
ian@0 92 Linux isn't designed to handle mixed CPU systems very well. In order
ian@0 93 to get everything going you *must* make sure that your lowest
ian@0 94 capability CPU is used for booting. Also, mixing CPU classes
ian@0 95 (e.g. 486 and 586) is really not going to work very well at all.