ia64/linux-2.6.18-xen.hg

annotate drivers/serial/m32r_sio_reg.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * m32r_sio_reg.h
ian@0 3 *
ian@0 4 * Copyright (C) 1992, 1994 by Theodore Ts'o.
ian@0 5 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
ian@0 6 *
ian@0 7 * Redistribution of this file is permitted under the terms of the GNU
ian@0 8 * Public License (GPL)
ian@0 9 *
ian@0 10 * These are the UART port assignments, expressed as offsets from the base
ian@0 11 * register. These assignments should hold for any serial port based on
ian@0 12 * a 8250, 16450, or 16550(A).
ian@0 13 */
ian@0 14
ian@0 15 #ifndef _M32R_SIO_REG_H
ian@0 16 #define _M32R_SIO_REG_H
ian@0 17
ian@0 18
ian@0 19 #ifdef CONFIG_SERIAL_M32R_PLDSIO
ian@0 20
ian@0 21 #define SIOCR 0x000
ian@0 22 #define SIOMOD0 0x002
ian@0 23 #define SIOMOD1 0x004
ian@0 24 #define SIOSTS 0x006
ian@0 25 #define SIOTRCR 0x008
ian@0 26 #define SIOBAUR 0x00a
ian@0 27 // #define SIORBAUR 0x018
ian@0 28 #define SIOTXB 0x00c
ian@0 29 #define SIORXB 0x00e
ian@0 30
ian@0 31 #define UART_RX ((unsigned long) PLD_ESIO0RXB)
ian@0 32 /* In: Receive buffer (DLAB=0) */
ian@0 33 #define UART_TX ((unsigned long) PLD_ESIO0TXB)
ian@0 34 /* Out: Transmit buffer (DLAB=0) */
ian@0 35 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
ian@0 36 #define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
ian@0 37 * In: Fifo count
ian@0 38 * Out: Fifo custom trigger levels
ian@0 39 * XR16C85x only */
ian@0 40
ian@0 41 #define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
ian@0 42 #define UART_IER ((unsigned long) PLD_ESIO0INTCR)
ian@0 43 /* Out: Interrupt Enable Register */
ian@0 44 #define UART_FCTR 0 /* (LCR=BF) Feature Control Register
ian@0 45 * XR16C85x only */
ian@0 46
ian@0 47 #define UART_IIR 0 /* In: Interrupt ID Register */
ian@0 48 #define UART_FCR 0 /* Out: FIFO Control Register */
ian@0 49 #define UART_EFR 0 /* I/O: Extended Features Register */
ian@0 50 /* (DLAB=1, 16C660 only) */
ian@0 51
ian@0 52 #define UART_LCR 0 /* Out: Line Control Register */
ian@0 53 #define UART_MCR 0 /* Out: Modem Control Register */
ian@0 54 #define UART_LSR ((unsigned long) PLD_ESIO0STS)
ian@0 55 /* In: Line Status Register */
ian@0 56 #define UART_MSR 0 /* In: Modem Status Register */
ian@0 57 #define UART_SCR 0 /* I/O: Scratch Register */
ian@0 58 #define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
ian@0 59 * FCTR bit 6 selects SCR or EMSR
ian@0 60 * XR16c85x only */
ian@0 61
ian@0 62 #else /* not CONFIG_SERIAL_M32R_PLDSIO */
ian@0 63
ian@0 64 #define SIOCR 0x000
ian@0 65 #define SIOMOD0 0x004
ian@0 66 #define SIOMOD1 0x008
ian@0 67 #define SIOSTS 0x00c
ian@0 68 #define SIOTRCR 0x010
ian@0 69 #define SIOBAUR 0x014
ian@0 70 #define SIORBAUR 0x018
ian@0 71 #define SIOTXB 0x01c
ian@0 72 #define SIORXB 0x020
ian@0 73
ian@0 74 #define UART_RX M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */
ian@0 75 #define UART_TX M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */
ian@0 76 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
ian@0 77 #define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
ian@0 78 * In: Fifo count
ian@0 79 * Out: Fifo custom trigger levels
ian@0 80 * XR16C85x only */
ian@0 81
ian@0 82 #define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
ian@0 83 #define UART_IER M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */
ian@0 84 #define UART_FCTR 0 /* (LCR=BF) Feature Control Register
ian@0 85 * XR16C85x only */
ian@0 86
ian@0 87 #define UART_IIR 0 /* In: Interrupt ID Register */
ian@0 88 #define UART_FCR 0 /* Out: FIFO Control Register */
ian@0 89 #define UART_EFR 0 /* I/O: Extended Features Register */
ian@0 90 /* (DLAB=1, 16C660 only) */
ian@0 91
ian@0 92 #define UART_LCR 0 /* Out: Line Control Register */
ian@0 93 #define UART_MCR 0 /* Out: Modem Control Register */
ian@0 94 #define UART_LSR M32R_SIO0_STS_PORTL /* In: Line Status Register */
ian@0 95 #define UART_MSR 0 /* In: Modem Status Register */
ian@0 96 #define UART_SCR 0 /* I/O: Scratch Register */
ian@0 97 #define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
ian@0 98 * FCTR bit 6 selects SCR or EMSR
ian@0 99 * XR16c85x only */
ian@0 100
ian@0 101 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
ian@0 102
ian@0 103 #define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
ian@0 104
ian@0 105 /*
ian@0 106 * These are the definitions for the Line Control Register
ian@0 107 *
ian@0 108 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
ian@0 109 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
ian@0 110 */
ian@0 111 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
ian@0 112 #define UART_LCR_SBC 0x40 /* Set break control */
ian@0 113 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
ian@0 114 #define UART_LCR_EPAR 0x10 /* Even parity select */
ian@0 115 #define UART_LCR_PARITY 0x08 /* Parity Enable */
ian@0 116 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
ian@0 117 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
ian@0 118 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
ian@0 119 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
ian@0 120 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
ian@0 121
ian@0 122 /*
ian@0 123 * These are the definitions for the Line Status Register
ian@0 124 */
ian@0 125 #define UART_LSR_TEMT 0x02 /* Transmitter empty */
ian@0 126 #define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */
ian@0 127 #define UART_LSR_BI 0x00 /* Break interrupt indicator */
ian@0 128 #define UART_LSR_FE 0x80 /* Frame error indicator */
ian@0 129 #define UART_LSR_PE 0x40 /* Parity error indicator */
ian@0 130 #define UART_LSR_OE 0x20 /* Overrun error indicator */
ian@0 131 #define UART_LSR_DR 0x04 /* Receiver data ready */
ian@0 132
ian@0 133 /*
ian@0 134 * These are the definitions for the Interrupt Identification Register
ian@0 135 */
ian@0 136 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
ian@0 137 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
ian@0 138
ian@0 139 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
ian@0 140 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
ian@0 141 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
ian@0 142 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
ian@0 143
ian@0 144 /*
ian@0 145 * These are the definitions for the Interrupt Enable Register
ian@0 146 */
ian@0 147 #define UART_IER_MSI 0x00 /* Enable Modem status interrupt */
ian@0 148 #define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */
ian@0 149 #define UART_IER_THRI 0x03 /* Enable Transmitter holding register int. */
ian@0 150 #define UART_IER_RDI 0x04 /* Enable receiver data interrupt */
ian@0 151
ian@0 152 #endif /* _M32R_SIO_REG_H */