ia64/linux-2.6.18-xen.hg

annotate drivers/net/starfire.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
rev   line source
ian@0 1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
ian@0 2 /*
ian@0 3 Written 1998-2000 by Donald Becker.
ian@0 4
ian@0 5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
ian@0 6 send all bug reports to me, and not to Donald Becker, as this code
ian@0 7 has been heavily modified from Donald's original version.
ian@0 8
ian@0 9 This software may be used and distributed according to the terms of
ian@0 10 the GNU General Public License (GPL), incorporated herein by reference.
ian@0 11 Drivers based on or derived from this code fall under the GPL and must
ian@0 12 retain the authorship, copyright and license notice. This file is not
ian@0 13 a complete program and may only be used when the entire operating
ian@0 14 system is licensed under the GPL.
ian@0 15
ian@0 16 The information below comes from Donald Becker's original driver:
ian@0 17
ian@0 18 The author may be reached as becker@scyld.com, or C/O
ian@0 19 Scyld Computing Corporation
ian@0 20 410 Severn Ave., Suite 210
ian@0 21 Annapolis MD 21403
ian@0 22
ian@0 23 Support and updates available at
ian@0 24 http://www.scyld.com/network/starfire.html
ian@0 25 [link no longer provides useful info -jgarzik]
ian@0 26
ian@0 27 */
ian@0 28
ian@0 29 #define DRV_NAME "starfire"
ian@0 30 #define DRV_VERSION "2.0"
ian@0 31 #define DRV_RELDATE "June 27, 2006"
ian@0 32
ian@0 33 #include <linux/module.h>
ian@0 34 #include <linux/kernel.h>
ian@0 35 #include <linux/pci.h>
ian@0 36 #include <linux/netdevice.h>
ian@0 37 #include <linux/etherdevice.h>
ian@0 38 #include <linux/init.h>
ian@0 39 #include <linux/delay.h>
ian@0 40 #include <linux/crc32.h>
ian@0 41 #include <linux/ethtool.h>
ian@0 42 #include <linux/mii.h>
ian@0 43 #include <linux/if_vlan.h>
ian@0 44 #include <asm/processor.h> /* Processor type for cache alignment. */
ian@0 45 #include <asm/uaccess.h>
ian@0 46 #include <asm/io.h>
ian@0 47
ian@0 48 #include "starfire_firmware.h"
ian@0 49 /*
ian@0 50 * The current frame processor firmware fails to checksum a fragment
ian@0 51 * of length 1. If and when this is fixed, the #define below can be removed.
ian@0 52 */
ian@0 53 #define HAS_BROKEN_FIRMWARE
ian@0 54
ian@0 55 /*
ian@0 56 * If using the broken firmware, data must be padded to the next 32-bit boundary.
ian@0 57 */
ian@0 58 #ifdef HAS_BROKEN_FIRMWARE
ian@0 59 #define PADDING_MASK 3
ian@0 60 #endif
ian@0 61
ian@0 62 /*
ian@0 63 * Define this if using the driver with the zero-copy patch
ian@0 64 */
ian@0 65 #define ZEROCOPY
ian@0 66
ian@0 67 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
ian@0 68 #define VLAN_SUPPORT
ian@0 69 #endif
ian@0 70
ian@0 71 #ifndef CONFIG_ADAPTEC_STARFIRE_NAPI
ian@0 72 #undef HAVE_NETDEV_POLL
ian@0 73 #endif
ian@0 74
ian@0 75 /* The user-configurable values.
ian@0 76 These may be modified when a driver module is loaded.*/
ian@0 77
ian@0 78 /* Used for tuning interrupt latency vs. overhead. */
ian@0 79 static int intr_latency;
ian@0 80 static int small_frames;
ian@0 81
ian@0 82 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
ian@0 83 static int max_interrupt_work = 20;
ian@0 84 static int mtu;
ian@0 85 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
ian@0 86 The Starfire has a 512 element hash table based on the Ethernet CRC. */
ian@0 87 static const int multicast_filter_limit = 512;
ian@0 88 /* Whether to do TCP/UDP checksums in hardware */
ian@0 89 static int enable_hw_cksum = 1;
ian@0 90
ian@0 91 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
ian@0 92 /*
ian@0 93 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
ian@0 94 * Setting to > 1518 effectively disables this feature.
ian@0 95 *
ian@0 96 * NOTE:
ian@0 97 * The ia64 doesn't allow for unaligned loads even of integers being
ian@0 98 * misaligned on a 2 byte boundary. Thus always force copying of
ian@0 99 * packets as the starfire doesn't allow for misaligned DMAs ;-(
ian@0 100 * 23/10/2000 - Jes
ian@0 101 *
ian@0 102 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
ian@0 103 * at least, having unaligned frames leads to a rather serious performance
ian@0 104 * penalty. -Ion
ian@0 105 */
ian@0 106 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
ian@0 107 static int rx_copybreak = PKT_BUF_SZ;
ian@0 108 #else
ian@0 109 static int rx_copybreak /* = 0 */;
ian@0 110 #endif
ian@0 111
ian@0 112 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
ian@0 113 #ifdef __sparc__
ian@0 114 #define DMA_BURST_SIZE 64
ian@0 115 #else
ian@0 116 #define DMA_BURST_SIZE 128
ian@0 117 #endif
ian@0 118
ian@0 119 /* Used to pass the media type, etc.
ian@0 120 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
ian@0 121 The media type is usually passed in 'options[]'.
ian@0 122 These variables are deprecated, use ethtool instead. -Ion
ian@0 123 */
ian@0 124 #define MAX_UNITS 8 /* More are supported, limit only on options */
ian@0 125 static int options[MAX_UNITS] = {0, };
ian@0 126 static int full_duplex[MAX_UNITS] = {0, };
ian@0 127
ian@0 128 /* Operational parameters that are set at compile time. */
ian@0 129
ian@0 130 /* The "native" ring sizes are either 256 or 2048.
ian@0 131 However in some modes a descriptor may be marked to wrap the ring earlier.
ian@0 132 */
ian@0 133 #define RX_RING_SIZE 256
ian@0 134 #define TX_RING_SIZE 32
ian@0 135 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
ian@0 136 #define DONE_Q_SIZE 1024
ian@0 137 /* All queues must be aligned on a 256-byte boundary */
ian@0 138 #define QUEUE_ALIGN 256
ian@0 139
ian@0 140 #if RX_RING_SIZE > 256
ian@0 141 #define RX_Q_ENTRIES Rx2048QEntries
ian@0 142 #else
ian@0 143 #define RX_Q_ENTRIES Rx256QEntries
ian@0 144 #endif
ian@0 145
ian@0 146 /* Operational parameters that usually are not changed. */
ian@0 147 /* Time in jiffies before concluding the transmitter is hung. */
ian@0 148 #define TX_TIMEOUT (2 * HZ)
ian@0 149
ian@0 150 /*
ian@0 151 * This SUCKS.
ian@0 152 * We need a much better method to determine if dma_addr_t is 64-bit.
ian@0 153 */
ian@0 154 #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
ian@0 155 /* 64-bit dma_addr_t */
ian@0 156 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
ian@0 157 #define netdrv_addr_t u64
ian@0 158 #define cpu_to_dma(x) cpu_to_le64(x)
ian@0 159 #define dma_to_cpu(x) le64_to_cpu(x)
ian@0 160 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
ian@0 161 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
ian@0 162 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
ian@0 163 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
ian@0 164 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
ian@0 165 #else /* 32-bit dma_addr_t */
ian@0 166 #define netdrv_addr_t u32
ian@0 167 #define cpu_to_dma(x) cpu_to_le32(x)
ian@0 168 #define dma_to_cpu(x) le32_to_cpu(x)
ian@0 169 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
ian@0 170 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
ian@0 171 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
ian@0 172 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
ian@0 173 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
ian@0 174 #endif
ian@0 175
ian@0 176 #define skb_first_frag_len(skb) skb_headlen(skb)
ian@0 177 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
ian@0 178
ian@0 179 #ifdef HAVE_NETDEV_POLL
ian@0 180 #define init_poll(dev) \
ian@0 181 do { \
ian@0 182 dev->poll = &netdev_poll; \
ian@0 183 dev->weight = max_interrupt_work; \
ian@0 184 } while (0)
ian@0 185 #define netdev_rx(dev, ioaddr) \
ian@0 186 do { \
ian@0 187 u32 intr_enable; \
ian@0 188 if (netif_rx_schedule_prep(dev)) { \
ian@0 189 __netif_rx_schedule(dev); \
ian@0 190 intr_enable = readl(ioaddr + IntrEnable); \
ian@0 191 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
ian@0 192 writel(intr_enable, ioaddr + IntrEnable); \
ian@0 193 readl(ioaddr + IntrEnable); /* flush PCI posting buffers */ \
ian@0 194 } else { \
ian@0 195 /* Paranoia check */ \
ian@0 196 intr_enable = readl(ioaddr + IntrEnable); \
ian@0 197 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \
ian@0 198 printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \
ian@0 199 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
ian@0 200 writel(intr_enable, ioaddr + IntrEnable); \
ian@0 201 } \
ian@0 202 } \
ian@0 203 } while (0)
ian@0 204 #define netdev_receive_skb(skb) netif_receive_skb(skb)
ian@0 205 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_receive_skb(skb, vlgrp, vlid)
ian@0 206 static int netdev_poll(struct net_device *dev, int *budget);
ian@0 207 #else /* not HAVE_NETDEV_POLL */
ian@0 208 #define init_poll(dev)
ian@0 209 #define netdev_receive_skb(skb) netif_rx(skb)
ian@0 210 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_rx(skb, vlgrp, vlid)
ian@0 211 #define netdev_rx(dev, ioaddr) \
ian@0 212 do { \
ian@0 213 int quota = np->dirty_rx + RX_RING_SIZE - np->cur_rx; \
ian@0 214 __netdev_rx(dev, &quota);\
ian@0 215 } while (0)
ian@0 216 #endif /* not HAVE_NETDEV_POLL */
ian@0 217 /* end of compatibility code */
ian@0 218
ian@0 219
ian@0 220 /* These identify the driver base version and may not be removed. */
ian@0 221 static const char version[] __devinitdata =
ian@0 222 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
ian@0 223 KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
ian@0 224
ian@0 225 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
ian@0 226 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
ian@0 227 MODULE_LICENSE("GPL");
ian@0 228 MODULE_VERSION(DRV_VERSION);
ian@0 229
ian@0 230 module_param(max_interrupt_work, int, 0);
ian@0 231 module_param(mtu, int, 0);
ian@0 232 module_param(debug, int, 0);
ian@0 233 module_param(rx_copybreak, int, 0);
ian@0 234 module_param(intr_latency, int, 0);
ian@0 235 module_param(small_frames, int, 0);
ian@0 236 module_param_array(options, int, NULL, 0);
ian@0 237 module_param_array(full_duplex, int, NULL, 0);
ian@0 238 module_param(enable_hw_cksum, int, 0);
ian@0 239 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
ian@0 240 MODULE_PARM_DESC(mtu, "MTU (all boards)");
ian@0 241 MODULE_PARM_DESC(debug, "Debug level (0-6)");
ian@0 242 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
ian@0 243 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
ian@0 244 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
ian@0 245 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
ian@0 246 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
ian@0 247 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
ian@0 248
ian@0 249 /*
ian@0 250 Theory of Operation
ian@0 251
ian@0 252 I. Board Compatibility
ian@0 253
ian@0 254 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
ian@0 255
ian@0 256 II. Board-specific settings
ian@0 257
ian@0 258 III. Driver operation
ian@0 259
ian@0 260 IIIa. Ring buffers
ian@0 261
ian@0 262 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
ian@0 263 ring sizes are set fixed by the hardware, but may optionally be wrapped
ian@0 264 earlier by the END bit in the descriptor.
ian@0 265 This driver uses that hardware queue size for the Rx ring, where a large
ian@0 266 number of entries has no ill effect beyond increases the potential backlog.
ian@0 267 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
ian@0 268 disables the queue layer priority ordering and we have no mechanism to
ian@0 269 utilize the hardware two-level priority queue. When modifying the
ian@0 270 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
ian@0 271 levels.
ian@0 272
ian@0 273 IIIb/c. Transmit/Receive Structure
ian@0 274
ian@0 275 See the Adaptec manual for the many possible structures, and options for
ian@0 276 each structure. There are far too many to document all of them here.
ian@0 277
ian@0 278 For transmit this driver uses type 0/1 transmit descriptors (depending
ian@0 279 on the 32/64 bitness of the architecture), and relies on automatic
ian@0 280 minimum-length padding. It does not use the completion queue
ian@0 281 consumer index, but instead checks for non-zero status entries.
ian@0 282
ian@0 283 For receive this driver uses type 2/3 receive descriptors. The driver
ian@0 284 allocates full frame size skbuffs for the Rx ring buffers, so all frames
ian@0 285 should fit in a single descriptor. The driver does not use the completion
ian@0 286 queue consumer index, but instead checks for non-zero status entries.
ian@0 287
ian@0 288 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
ian@0 289 is allocated and the frame is copied to the new skbuff. When the incoming
ian@0 290 frame is larger, the skbuff is passed directly up the protocol stack.
ian@0 291 Buffers consumed this way are replaced by newly allocated skbuffs in a later
ian@0 292 phase of receive.
ian@0 293
ian@0 294 A notable aspect of operation is that unaligned buffers are not permitted by
ian@0 295 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
ian@0 296 isn't longword aligned, which may cause problems on some machine
ian@0 297 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
ian@0 298 the frame into a new skbuff unconditionally. Copied frames are put into the
ian@0 299 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
ian@0 300
ian@0 301 IIId. Synchronization
ian@0 302
ian@0 303 The driver runs as two independent, single-threaded flows of control. One
ian@0 304 is the send-packet routine, which enforces single-threaded use by the
ian@0 305 dev->tbusy flag. The other thread is the interrupt handler, which is single
ian@0 306 threaded by the hardware and interrupt handling software.
ian@0 307
ian@0 308 The send packet thread has partial control over the Tx ring and the netif_queue
ian@0 309 status. If the number of free Tx slots in the ring falls below a certain number
ian@0 310 (currently hardcoded to 4), it signals the upper layer to stop the queue.
ian@0 311
ian@0 312 The interrupt handler has exclusive control over the Rx ring and records stats
ian@0 313 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
ian@0 314 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
ian@0 315 number of free Tx slow is above the threshold, it signals the upper layer to
ian@0 316 restart the queue.
ian@0 317
ian@0 318 IV. Notes
ian@0 319
ian@0 320 IVb. References
ian@0 321
ian@0 322 The Adaptec Starfire manuals, available only from Adaptec.
ian@0 323 http://www.scyld.com/expert/100mbps.html
ian@0 324 http://www.scyld.com/expert/NWay.html
ian@0 325
ian@0 326 IVc. Errata
ian@0 327
ian@0 328 - StopOnPerr is broken, don't enable
ian@0 329 - Hardware ethernet padding exposes random data, perform software padding
ian@0 330 instead (unverified -- works correctly for all the hardware I have)
ian@0 331
ian@0 332 */
ian@0 333
ian@0 334
ian@0 335
ian@0 336 enum chip_capability_flags {CanHaveMII=1, };
ian@0 337
ian@0 338 enum chipset {
ian@0 339 CH_6915 = 0,
ian@0 340 };
ian@0 341
ian@0 342 static struct pci_device_id starfire_pci_tbl[] = {
ian@0 343 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 },
ian@0 344 { 0, }
ian@0 345 };
ian@0 346 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
ian@0 347
ian@0 348 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
ian@0 349 static const struct chip_info {
ian@0 350 const char *name;
ian@0 351 int drv_flags;
ian@0 352 } netdrv_tbl[] __devinitdata = {
ian@0 353 { "Adaptec Starfire 6915", CanHaveMII },
ian@0 354 };
ian@0 355
ian@0 356
ian@0 357 /* Offsets to the device registers.
ian@0 358 Unlike software-only systems, device drivers interact with complex hardware.
ian@0 359 It's not useful to define symbolic names for every register bit in the
ian@0 360 device. The name can only partially document the semantics and make
ian@0 361 the driver longer and more difficult to read.
ian@0 362 In general, only the important configuration values or bits changed
ian@0 363 multiple times should be defined symbolically.
ian@0 364 */
ian@0 365 enum register_offsets {
ian@0 366 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
ian@0 367 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
ian@0 368 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
ian@0 369 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
ian@0 370 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
ian@0 371 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
ian@0 372 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
ian@0 373 TxThreshold=0x500B0,
ian@0 374 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
ian@0 375 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
ian@0 376 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
ian@0 377 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
ian@0 378 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
ian@0 379 TxMode=0x55000, VlanType=0x55064,
ian@0 380 PerfFilterTable=0x56000, HashTable=0x56100,
ian@0 381 TxGfpMem=0x58000, RxGfpMem=0x5a000,
ian@0 382 };
ian@0 383
ian@0 384 /*
ian@0 385 * Bits in the interrupt status/mask registers.
ian@0 386 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
ian@0 387 * enables all the interrupt sources that are or'ed into those status bits.
ian@0 388 */
ian@0 389 enum intr_status_bits {
ian@0 390 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
ian@0 391 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
ian@0 392 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
ian@0 393 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
ian@0 394 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
ian@0 395 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
ian@0 396 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
ian@0 397 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
ian@0 398 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
ian@0 399 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
ian@0 400 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
ian@0 401 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
ian@0 402 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
ian@0 403 IntrTxGfp=0x02, IntrPCIPad=0x01,
ian@0 404 /* not quite bits */
ian@0 405 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
ian@0 406 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
ian@0 407 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
ian@0 408 };
ian@0 409
ian@0 410 /* Bits in the RxFilterMode register. */
ian@0 411 enum rx_mode_bits {
ian@0 412 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
ian@0 413 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
ian@0 414 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
ian@0 415 WakeupOnGFP=0x0800,
ian@0 416 };
ian@0 417
ian@0 418 /* Bits in the TxMode register */
ian@0 419 enum tx_mode_bits {
ian@0 420 MiiSoftReset=0x8000, MIILoopback=0x4000,
ian@0 421 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
ian@0 422 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
ian@0 423 };
ian@0 424
ian@0 425 /* Bits in the TxDescCtrl register. */
ian@0 426 enum tx_ctrl_bits {
ian@0 427 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
ian@0 428 TxDescSpace128=0x30, TxDescSpace256=0x40,
ian@0 429 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
ian@0 430 TxDescType3=0x03, TxDescType4=0x04,
ian@0 431 TxNoDMACompletion=0x08,
ian@0 432 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
ian@0 433 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
ian@0 434 TxDMABurstSizeShift=8,
ian@0 435 };
ian@0 436
ian@0 437 /* Bits in the RxDescQCtrl register. */
ian@0 438 enum rx_ctrl_bits {
ian@0 439 RxBufferLenShift=16, RxMinDescrThreshShift=0,
ian@0 440 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
ian@0 441 Rx2048QEntries=0x4000, Rx256QEntries=0,
ian@0 442 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
ian@0 443 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
ian@0 444 RxDescSpace4=0x000, RxDescSpace8=0x100,
ian@0 445 RxDescSpace16=0x200, RxDescSpace32=0x300,
ian@0 446 RxDescSpace64=0x400, RxDescSpace128=0x500,
ian@0 447 RxConsumerWrEn=0x80,
ian@0 448 };
ian@0 449
ian@0 450 /* Bits in the RxDMACtrl register. */
ian@0 451 enum rx_dmactrl_bits {
ian@0 452 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
ian@0 453 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
ian@0 454 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
ian@0 455 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
ian@0 456 RxChecksumRejectTCPOnly=0x01000000,
ian@0 457 RxCompletionQ2Enable=0x800000,
ian@0 458 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
ian@0 459 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
ian@0 460 RxDMAQ2NonIP=0x400000,
ian@0 461 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
ian@0 462 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
ian@0 463 RxBurstSizeShift=0,
ian@0 464 };
ian@0 465
ian@0 466 /* Bits in the RxCompletionAddr register */
ian@0 467 enum rx_compl_bits {
ian@0 468 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
ian@0 469 RxComplProducerWrEn=0x40,
ian@0 470 RxComplType0=0x00, RxComplType1=0x10,
ian@0 471 RxComplType2=0x20, RxComplType3=0x30,
ian@0 472 RxComplThreshShift=0,
ian@0 473 };
ian@0 474
ian@0 475 /* Bits in the TxCompletionAddr register */
ian@0 476 enum tx_compl_bits {
ian@0 477 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
ian@0 478 TxComplProducerWrEn=0x40,
ian@0 479 TxComplIntrStatus=0x20,
ian@0 480 CommonQueueMode=0x10,
ian@0 481 TxComplThreshShift=0,
ian@0 482 };
ian@0 483
ian@0 484 /* Bits in the GenCtrl register */
ian@0 485 enum gen_ctrl_bits {
ian@0 486 RxEnable=0x05, TxEnable=0x0a,
ian@0 487 RxGFPEnable=0x10, TxGFPEnable=0x20,
ian@0 488 };
ian@0 489
ian@0 490 /* Bits in the IntrTimerCtrl register */
ian@0 491 enum intr_ctrl_bits {
ian@0 492 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
ian@0 493 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
ian@0 494 IntrLatencyMask=0x1f,
ian@0 495 };
ian@0 496
ian@0 497 /* The Rx and Tx buffer descriptors. */
ian@0 498 struct starfire_rx_desc {
ian@0 499 dma_addr_t rxaddr;
ian@0 500 };
ian@0 501 enum rx_desc_bits {
ian@0 502 RxDescValid=1, RxDescEndRing=2,
ian@0 503 };
ian@0 504
ian@0 505 /* Completion queue entry. */
ian@0 506 struct short_rx_done_desc {
ian@0 507 u32 status; /* Low 16 bits is length. */
ian@0 508 };
ian@0 509 struct basic_rx_done_desc {
ian@0 510 u32 status; /* Low 16 bits is length. */
ian@0 511 u16 vlanid;
ian@0 512 u16 status2;
ian@0 513 };
ian@0 514 struct csum_rx_done_desc {
ian@0 515 u32 status; /* Low 16 bits is length. */
ian@0 516 u16 csum; /* Partial checksum */
ian@0 517 u16 status2;
ian@0 518 };
ian@0 519 struct full_rx_done_desc {
ian@0 520 u32 status; /* Low 16 bits is length. */
ian@0 521 u16 status3;
ian@0 522 u16 status2;
ian@0 523 u16 vlanid;
ian@0 524 u16 csum; /* partial checksum */
ian@0 525 u32 timestamp;
ian@0 526 };
ian@0 527 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
ian@0 528 #ifdef VLAN_SUPPORT
ian@0 529 typedef struct full_rx_done_desc rx_done_desc;
ian@0 530 #define RxComplType RxComplType3
ian@0 531 #else /* not VLAN_SUPPORT */
ian@0 532 typedef struct csum_rx_done_desc rx_done_desc;
ian@0 533 #define RxComplType RxComplType2
ian@0 534 #endif /* not VLAN_SUPPORT */
ian@0 535
ian@0 536 enum rx_done_bits {
ian@0 537 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
ian@0 538 };
ian@0 539
ian@0 540 /* Type 1 Tx descriptor. */
ian@0 541 struct starfire_tx_desc_1 {
ian@0 542 u32 status; /* Upper bits are status, lower 16 length. */
ian@0 543 u32 addr;
ian@0 544 };
ian@0 545
ian@0 546 /* Type 2 Tx descriptor. */
ian@0 547 struct starfire_tx_desc_2 {
ian@0 548 u32 status; /* Upper bits are status, lower 16 length. */
ian@0 549 u32 reserved;
ian@0 550 u64 addr;
ian@0 551 };
ian@0 552
ian@0 553 #ifdef ADDR_64BITS
ian@0 554 typedef struct starfire_tx_desc_2 starfire_tx_desc;
ian@0 555 #define TX_DESC_TYPE TxDescType2
ian@0 556 #else /* not ADDR_64BITS */
ian@0 557 typedef struct starfire_tx_desc_1 starfire_tx_desc;
ian@0 558 #define TX_DESC_TYPE TxDescType1
ian@0 559 #endif /* not ADDR_64BITS */
ian@0 560 #define TX_DESC_SPACING TxDescSpaceUnlim
ian@0 561
ian@0 562 enum tx_desc_bits {
ian@0 563 TxDescID=0xB0000000,
ian@0 564 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
ian@0 565 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
ian@0 566 };
ian@0 567 struct tx_done_desc {
ian@0 568 u32 status; /* timestamp, index. */
ian@0 569 #if 0
ian@0 570 u32 intrstatus; /* interrupt status */
ian@0 571 #endif
ian@0 572 };
ian@0 573
ian@0 574 struct rx_ring_info {
ian@0 575 struct sk_buff *skb;
ian@0 576 dma_addr_t mapping;
ian@0 577 };
ian@0 578 struct tx_ring_info {
ian@0 579 struct sk_buff *skb;
ian@0 580 dma_addr_t mapping;
ian@0 581 unsigned int used_slots;
ian@0 582 };
ian@0 583
ian@0 584 #define PHY_CNT 2
ian@0 585 struct netdev_private {
ian@0 586 /* Descriptor rings first for alignment. */
ian@0 587 struct starfire_rx_desc *rx_ring;
ian@0 588 starfire_tx_desc *tx_ring;
ian@0 589 dma_addr_t rx_ring_dma;
ian@0 590 dma_addr_t tx_ring_dma;
ian@0 591 /* The addresses of rx/tx-in-place skbuffs. */
ian@0 592 struct rx_ring_info rx_info[RX_RING_SIZE];
ian@0 593 struct tx_ring_info tx_info[TX_RING_SIZE];
ian@0 594 /* Pointers to completion queues (full pages). */
ian@0 595 rx_done_desc *rx_done_q;
ian@0 596 dma_addr_t rx_done_q_dma;
ian@0 597 unsigned int rx_done;
ian@0 598 struct tx_done_desc *tx_done_q;
ian@0 599 dma_addr_t tx_done_q_dma;
ian@0 600 unsigned int tx_done;
ian@0 601 struct net_device_stats stats;
ian@0 602 struct pci_dev *pci_dev;
ian@0 603 #ifdef VLAN_SUPPORT
ian@0 604 struct vlan_group *vlgrp;
ian@0 605 #endif
ian@0 606 void *queue_mem;
ian@0 607 dma_addr_t queue_mem_dma;
ian@0 608 size_t queue_mem_size;
ian@0 609
ian@0 610 /* Frequently used values: keep some adjacent for cache effect. */
ian@0 611 spinlock_t lock;
ian@0 612 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
ian@0 613 unsigned int cur_tx, dirty_tx, reap_tx;
ian@0 614 unsigned int rx_buf_sz; /* Based on MTU+slack. */
ian@0 615 /* These values keep track of the transceiver/media in use. */
ian@0 616 int speed100; /* Set if speed == 100MBit. */
ian@0 617 u32 tx_mode;
ian@0 618 u32 intr_timer_ctrl;
ian@0 619 u8 tx_threshold;
ian@0 620 /* MII transceiver section. */
ian@0 621 struct mii_if_info mii_if; /* MII lib hooks/info */
ian@0 622 int phy_cnt; /* MII device addresses. */
ian@0 623 unsigned char phys[PHY_CNT]; /* MII device addresses. */
ian@0 624 void __iomem *base;
ian@0 625 };
ian@0 626
ian@0 627
ian@0 628 static int mdio_read(struct net_device *dev, int phy_id, int location);
ian@0 629 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
ian@0 630 static int netdev_open(struct net_device *dev);
ian@0 631 static void check_duplex(struct net_device *dev);
ian@0 632 static void tx_timeout(struct net_device *dev);
ian@0 633 static void init_ring(struct net_device *dev);
ian@0 634 static int start_tx(struct sk_buff *skb, struct net_device *dev);
ian@0 635 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
ian@0 636 static void netdev_error(struct net_device *dev, int intr_status);
ian@0 637 static int __netdev_rx(struct net_device *dev, int *quota);
ian@0 638 static void refill_rx_ring(struct net_device *dev);
ian@0 639 static void netdev_error(struct net_device *dev, int intr_status);
ian@0 640 static void set_rx_mode(struct net_device *dev);
ian@0 641 static struct net_device_stats *get_stats(struct net_device *dev);
ian@0 642 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
ian@0 643 static int netdev_close(struct net_device *dev);
ian@0 644 static void netdev_media_change(struct net_device *dev);
ian@0 645 static struct ethtool_ops ethtool_ops;
ian@0 646
ian@0 647
ian@0 648 #ifdef VLAN_SUPPORT
ian@0 649 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
ian@0 650 {
ian@0 651 struct netdev_private *np = netdev_priv(dev);
ian@0 652
ian@0 653 spin_lock(&np->lock);
ian@0 654 if (debug > 2)
ian@0 655 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
ian@0 656 np->vlgrp = grp;
ian@0 657 set_rx_mode(dev);
ian@0 658 spin_unlock(&np->lock);
ian@0 659 }
ian@0 660
ian@0 661 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
ian@0 662 {
ian@0 663 struct netdev_private *np = netdev_priv(dev);
ian@0 664
ian@0 665 spin_lock(&np->lock);
ian@0 666 if (debug > 1)
ian@0 667 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
ian@0 668 set_rx_mode(dev);
ian@0 669 spin_unlock(&np->lock);
ian@0 670 }
ian@0 671
ian@0 672 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
ian@0 673 {
ian@0 674 struct netdev_private *np = netdev_priv(dev);
ian@0 675
ian@0 676 spin_lock(&np->lock);
ian@0 677 if (debug > 1)
ian@0 678 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
ian@0 679 if (np->vlgrp)
ian@0 680 np->vlgrp->vlan_devices[vid] = NULL;
ian@0 681 set_rx_mode(dev);
ian@0 682 spin_unlock(&np->lock);
ian@0 683 }
ian@0 684 #endif /* VLAN_SUPPORT */
ian@0 685
ian@0 686
ian@0 687 static int __devinit starfire_init_one(struct pci_dev *pdev,
ian@0 688 const struct pci_device_id *ent)
ian@0 689 {
ian@0 690 struct netdev_private *np;
ian@0 691 int i, irq, option, chip_idx = ent->driver_data;
ian@0 692 struct net_device *dev;
ian@0 693 static int card_idx = -1;
ian@0 694 long ioaddr;
ian@0 695 void __iomem *base;
ian@0 696 int drv_flags, io_size;
ian@0 697 int boguscnt;
ian@0 698
ian@0 699 /* when built into the kernel, we only print version if device is found */
ian@0 700 #ifndef MODULE
ian@0 701 static int printed_version;
ian@0 702 if (!printed_version++)
ian@0 703 printk(version);
ian@0 704 #endif
ian@0 705
ian@0 706 card_idx++;
ian@0 707
ian@0 708 if (pci_enable_device (pdev))
ian@0 709 return -EIO;
ian@0 710
ian@0 711 ioaddr = pci_resource_start(pdev, 0);
ian@0 712 io_size = pci_resource_len(pdev, 0);
ian@0 713 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
ian@0 714 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
ian@0 715 return -ENODEV;
ian@0 716 }
ian@0 717
ian@0 718 dev = alloc_etherdev(sizeof(*np));
ian@0 719 if (!dev) {
ian@0 720 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
ian@0 721 return -ENOMEM;
ian@0 722 }
ian@0 723 SET_MODULE_OWNER(dev);
ian@0 724 SET_NETDEV_DEV(dev, &pdev->dev);
ian@0 725
ian@0 726 irq = pdev->irq;
ian@0 727
ian@0 728 if (pci_request_regions (pdev, DRV_NAME)) {
ian@0 729 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
ian@0 730 goto err_out_free_netdev;
ian@0 731 }
ian@0 732
ian@0 733 base = ioremap(ioaddr, io_size);
ian@0 734 if (!base) {
ian@0 735 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
ian@0 736 card_idx, io_size, ioaddr);
ian@0 737 goto err_out_free_res;
ian@0 738 }
ian@0 739
ian@0 740 pci_set_master(pdev);
ian@0 741
ian@0 742 /* enable MWI -- it vastly improves Rx performance on sparc64 */
ian@0 743 pci_set_mwi(pdev);
ian@0 744
ian@0 745 #ifdef ZEROCOPY
ian@0 746 /* Starfire can do TCP/UDP checksumming */
ian@0 747 if (enable_hw_cksum)
ian@0 748 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
ian@0 749 #endif /* ZEROCOPY */
ian@0 750 #ifdef VLAN_SUPPORT
ian@0 751 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
ian@0 752 dev->vlan_rx_register = netdev_vlan_rx_register;
ian@0 753 dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid;
ian@0 754 dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid;
ian@0 755 #endif /* VLAN_RX_KILL_VID */
ian@0 756 #ifdef ADDR_64BITS
ian@0 757 dev->features |= NETIF_F_HIGHDMA;
ian@0 758 #endif /* ADDR_64BITS */
ian@0 759
ian@0 760 /* Serial EEPROM reads are hidden by the hardware. */
ian@0 761 for (i = 0; i < 6; i++)
ian@0 762 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
ian@0 763
ian@0 764 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
ian@0 765 if (debug > 4)
ian@0 766 for (i = 0; i < 0x20; i++)
ian@0 767 printk("%2.2x%s",
ian@0 768 (unsigned int)readb(base + EEPROMCtrl + i),
ian@0 769 i % 16 != 15 ? " " : "\n");
ian@0 770 #endif
ian@0 771
ian@0 772 /* Issue soft reset */
ian@0 773 writel(MiiSoftReset, base + TxMode);
ian@0 774 udelay(1000);
ian@0 775 writel(0, base + TxMode);
ian@0 776
ian@0 777 /* Reset the chip to erase previous misconfiguration. */
ian@0 778 writel(1, base + PCIDeviceConfig);
ian@0 779 boguscnt = 1000;
ian@0 780 while (--boguscnt > 0) {
ian@0 781 udelay(10);
ian@0 782 if ((readl(base + PCIDeviceConfig) & 1) == 0)
ian@0 783 break;
ian@0 784 }
ian@0 785 if (boguscnt == 0)
ian@0 786 printk("%s: chipset reset never completed!\n", dev->name);
ian@0 787 /* wait a little longer */
ian@0 788 udelay(1000);
ian@0 789
ian@0 790 dev->base_addr = (unsigned long)base;
ian@0 791 dev->irq = irq;
ian@0 792
ian@0 793 np = netdev_priv(dev);
ian@0 794 np->base = base;
ian@0 795 spin_lock_init(&np->lock);
ian@0 796 pci_set_drvdata(pdev, dev);
ian@0 797
ian@0 798 np->pci_dev = pdev;
ian@0 799
ian@0 800 np->mii_if.dev = dev;
ian@0 801 np->mii_if.mdio_read = mdio_read;
ian@0 802 np->mii_if.mdio_write = mdio_write;
ian@0 803 np->mii_if.phy_id_mask = 0x1f;
ian@0 804 np->mii_if.reg_num_mask = 0x1f;
ian@0 805
ian@0 806 drv_flags = netdrv_tbl[chip_idx].drv_flags;
ian@0 807
ian@0 808 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
ian@0 809 if (dev->mem_start)
ian@0 810 option = dev->mem_start;
ian@0 811
ian@0 812 /* The lower four bits are the media type. */
ian@0 813 if (option & 0x200)
ian@0 814 np->mii_if.full_duplex = 1;
ian@0 815
ian@0 816 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
ian@0 817 np->mii_if.full_duplex = 1;
ian@0 818
ian@0 819 if (np->mii_if.full_duplex)
ian@0 820 np->mii_if.force_media = 1;
ian@0 821 else
ian@0 822 np->mii_if.force_media = 0;
ian@0 823 np->speed100 = 1;
ian@0 824
ian@0 825 /* timer resolution is 128 * 0.8us */
ian@0 826 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
ian@0 827 Timer10X | EnableIntrMasking;
ian@0 828
ian@0 829 if (small_frames > 0) {
ian@0 830 np->intr_timer_ctrl |= SmallFrameBypass;
ian@0 831 switch (small_frames) {
ian@0 832 case 1 ... 64:
ian@0 833 np->intr_timer_ctrl |= SmallFrame64;
ian@0 834 break;
ian@0 835 case 65 ... 128:
ian@0 836 np->intr_timer_ctrl |= SmallFrame128;
ian@0 837 break;
ian@0 838 case 129 ... 256:
ian@0 839 np->intr_timer_ctrl |= SmallFrame256;
ian@0 840 break;
ian@0 841 default:
ian@0 842 np->intr_timer_ctrl |= SmallFrame512;
ian@0 843 if (small_frames > 512)
ian@0 844 printk("Adjusting small_frames down to 512\n");
ian@0 845 break;
ian@0 846 }
ian@0 847 }
ian@0 848
ian@0 849 /* The chip-specific entries in the device structure. */
ian@0 850 dev->open = &netdev_open;
ian@0 851 dev->hard_start_xmit = &start_tx;
ian@0 852 dev->tx_timeout = tx_timeout;
ian@0 853 dev->watchdog_timeo = TX_TIMEOUT;
ian@0 854 init_poll(dev);
ian@0 855 dev->stop = &netdev_close;
ian@0 856 dev->get_stats = &get_stats;
ian@0 857 dev->set_multicast_list = &set_rx_mode;
ian@0 858 dev->do_ioctl = &netdev_ioctl;
ian@0 859 SET_ETHTOOL_OPS(dev, &ethtool_ops);
ian@0 860
ian@0 861 if (mtu)
ian@0 862 dev->mtu = mtu;
ian@0 863
ian@0 864 if (register_netdev(dev))
ian@0 865 goto err_out_cleardev;
ian@0 866
ian@0 867 printk(KERN_INFO "%s: %s at %p, ",
ian@0 868 dev->name, netdrv_tbl[chip_idx].name, base);
ian@0 869 for (i = 0; i < 5; i++)
ian@0 870 printk("%2.2x:", dev->dev_addr[i]);
ian@0 871 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
ian@0 872
ian@0 873 if (drv_flags & CanHaveMII) {
ian@0 874 int phy, phy_idx = 0;
ian@0 875 int mii_status;
ian@0 876 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
ian@0 877 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
ian@0 878 mdelay(100);
ian@0 879 boguscnt = 1000;
ian@0 880 while (--boguscnt > 0)
ian@0 881 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
ian@0 882 break;
ian@0 883 if (boguscnt == 0) {
ian@0 884 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
ian@0 885 continue;
ian@0 886 }
ian@0 887 mii_status = mdio_read(dev, phy, MII_BMSR);
ian@0 888 if (mii_status != 0) {
ian@0 889 np->phys[phy_idx++] = phy;
ian@0 890 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
ian@0 891 printk(KERN_INFO "%s: MII PHY found at address %d, status "
ian@0 892 "%#4.4x advertising %#4.4x.\n",
ian@0 893 dev->name, phy, mii_status, np->mii_if.advertising);
ian@0 894 /* there can be only one PHY on-board */
ian@0 895 break;
ian@0 896 }
ian@0 897 }
ian@0 898 np->phy_cnt = phy_idx;
ian@0 899 if (np->phy_cnt > 0)
ian@0 900 np->mii_if.phy_id = np->phys[0];
ian@0 901 else
ian@0 902 memset(&np->mii_if, 0, sizeof(np->mii_if));
ian@0 903 }
ian@0 904
ian@0 905 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
ian@0 906 dev->name, enable_hw_cksum ? "enabled" : "disabled");
ian@0 907 return 0;
ian@0 908
ian@0 909 err_out_cleardev:
ian@0 910 pci_set_drvdata(pdev, NULL);
ian@0 911 iounmap(base);
ian@0 912 err_out_free_res:
ian@0 913 pci_release_regions (pdev);
ian@0 914 err_out_free_netdev:
ian@0 915 free_netdev(dev);
ian@0 916 return -ENODEV;
ian@0 917 }
ian@0 918
ian@0 919
ian@0 920 /* Read the MII Management Data I/O (MDIO) interfaces. */
ian@0 921 static int mdio_read(struct net_device *dev, int phy_id, int location)
ian@0 922 {
ian@0 923 struct netdev_private *np = netdev_priv(dev);
ian@0 924 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
ian@0 925 int result, boguscnt=1000;
ian@0 926 /* ??? Should we add a busy-wait here? */
ian@0 927 do
ian@0 928 result = readl(mdio_addr);
ian@0 929 while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
ian@0 930 if (boguscnt == 0)
ian@0 931 return 0;
ian@0 932 if ((result & 0xffff) == 0xffff)
ian@0 933 return 0;
ian@0 934 return result & 0xffff;
ian@0 935 }
ian@0 936
ian@0 937
ian@0 938 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
ian@0 939 {
ian@0 940 struct netdev_private *np = netdev_priv(dev);
ian@0 941 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
ian@0 942 writel(value, mdio_addr);
ian@0 943 /* The busy-wait will occur before a read. */
ian@0 944 }
ian@0 945
ian@0 946
ian@0 947 static int netdev_open(struct net_device *dev)
ian@0 948 {
ian@0 949 struct netdev_private *np = netdev_priv(dev);
ian@0 950 void __iomem *ioaddr = np->base;
ian@0 951 int i, retval;
ian@0 952 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
ian@0 953
ian@0 954 /* Do we ever need to reset the chip??? */
ian@0 955
ian@0 956 retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
ian@0 957 if (retval)
ian@0 958 return retval;
ian@0 959
ian@0 960 /* Disable the Rx and Tx, and reset the chip. */
ian@0 961 writel(0, ioaddr + GenCtrl);
ian@0 962 writel(1, ioaddr + PCIDeviceConfig);
ian@0 963 if (debug > 1)
ian@0 964 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
ian@0 965 dev->name, dev->irq);
ian@0 966
ian@0 967 /* Allocate the various queues. */
ian@0 968 if (np->queue_mem == 0) {
ian@0 969 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
ian@0 970 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
ian@0 971 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
ian@0 972 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
ian@0 973 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
ian@0 974 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
ian@0 975 if (np->queue_mem == NULL) {
ian@0 976 free_irq(dev->irq, dev);
ian@0 977 return -ENOMEM;
ian@0 978 }
ian@0 979
ian@0 980 np->tx_done_q = np->queue_mem;
ian@0 981 np->tx_done_q_dma = np->queue_mem_dma;
ian@0 982 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
ian@0 983 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
ian@0 984 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
ian@0 985 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
ian@0 986 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
ian@0 987 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
ian@0 988 }
ian@0 989
ian@0 990 /* Start with no carrier, it gets adjusted later */
ian@0 991 netif_carrier_off(dev);
ian@0 992 init_ring(dev);
ian@0 993 /* Set the size of the Rx buffers. */
ian@0 994 writel((np->rx_buf_sz << RxBufferLenShift) |
ian@0 995 (0 << RxMinDescrThreshShift) |
ian@0 996 RxPrefetchMode | RxVariableQ |
ian@0 997 RX_Q_ENTRIES |
ian@0 998 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
ian@0 999 RxDescSpace4,
ian@0 1000 ioaddr + RxDescQCtrl);
ian@0 1001
ian@0 1002 /* Set up the Rx DMA controller. */
ian@0 1003 writel(RxChecksumIgnore |
ian@0 1004 (0 << RxEarlyIntThreshShift) |
ian@0 1005 (6 << RxHighPrioThreshShift) |
ian@0 1006 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
ian@0 1007 ioaddr + RxDMACtrl);
ian@0 1008
ian@0 1009 /* Set Tx descriptor */
ian@0 1010 writel((2 << TxHiPriFIFOThreshShift) |
ian@0 1011 (0 << TxPadLenShift) |
ian@0 1012 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
ian@0 1013 TX_DESC_Q_ADDR_SIZE |
ian@0 1014 TX_DESC_SPACING | TX_DESC_TYPE,
ian@0 1015 ioaddr + TxDescCtrl);
ian@0 1016
ian@0 1017 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
ian@0 1018 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
ian@0 1019 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
ian@0 1020 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
ian@0 1021 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
ian@0 1022
ian@0 1023 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
ian@0 1024 writel(np->rx_done_q_dma |
ian@0 1025 RxComplType |
ian@0 1026 (0 << RxComplThreshShift),
ian@0 1027 ioaddr + RxCompletionAddr);
ian@0 1028
ian@0 1029 if (debug > 1)
ian@0 1030 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
ian@0 1031
ian@0 1032 /* Fill both the Tx SA register and the Rx perfect filter. */
ian@0 1033 for (i = 0; i < 6; i++)
ian@0 1034 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
ian@0 1035 /* The first entry is special because it bypasses the VLAN filter.
ian@0 1036 Don't use it. */
ian@0 1037 writew(0, ioaddr + PerfFilterTable);
ian@0 1038 writew(0, ioaddr + PerfFilterTable + 4);
ian@0 1039 writew(0, ioaddr + PerfFilterTable + 8);
ian@0 1040 for (i = 1; i < 16; i++) {
ian@0 1041 u16 *eaddrs = (u16 *)dev->dev_addr;
ian@0 1042 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
ian@0 1043 writew(cpu_to_be16(eaddrs[2]), setup_frm); setup_frm += 4;
ian@0 1044 writew(cpu_to_be16(eaddrs[1]), setup_frm); setup_frm += 4;
ian@0 1045 writew(cpu_to_be16(eaddrs[0]), setup_frm); setup_frm += 8;
ian@0 1046 }
ian@0 1047
ian@0 1048 /* Initialize other registers. */
ian@0 1049 /* Configure the PCI bus bursts and FIFO thresholds. */
ian@0 1050 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
ian@0 1051 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
ian@0 1052 udelay(1000);
ian@0 1053 writel(np->tx_mode, ioaddr + TxMode);
ian@0 1054 np->tx_threshold = 4;
ian@0 1055 writel(np->tx_threshold, ioaddr + TxThreshold);
ian@0 1056
ian@0 1057 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
ian@0 1058
ian@0 1059 netif_start_queue(dev);
ian@0 1060
ian@0 1061 if (debug > 1)
ian@0 1062 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
ian@0 1063 set_rx_mode(dev);
ian@0 1064
ian@0 1065 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
ian@0 1066 check_duplex(dev);
ian@0 1067
ian@0 1068 /* Enable GPIO interrupts on link change */
ian@0 1069 writel(0x0f00ff00, ioaddr + GPIOCtrl);
ian@0 1070
ian@0 1071 /* Set the interrupt mask */
ian@0 1072 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
ian@0 1073 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
ian@0 1074 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
ian@0 1075 ioaddr + IntrEnable);
ian@0 1076 /* Enable PCI interrupts. */
ian@0 1077 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
ian@0 1078 ioaddr + PCIDeviceConfig);
ian@0 1079
ian@0 1080 #ifdef VLAN_SUPPORT
ian@0 1081 /* Set VLAN type to 802.1q */
ian@0 1082 writel(ETH_P_8021Q, ioaddr + VlanType);
ian@0 1083 #endif /* VLAN_SUPPORT */
ian@0 1084
ian@0 1085 /* Load Rx/Tx firmware into the frame processors */
ian@0 1086 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
ian@0 1087 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
ian@0 1088 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
ian@0 1089 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
ian@0 1090 if (enable_hw_cksum)
ian@0 1091 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
ian@0 1092 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
ian@0 1093 else
ian@0 1094 /* Enable the Rx and Tx units only. */
ian@0 1095 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
ian@0 1096
ian@0 1097 if (debug > 1)
ian@0 1098 printk(KERN_DEBUG "%s: Done netdev_open().\n",
ian@0 1099 dev->name);
ian@0 1100
ian@0 1101 return 0;
ian@0 1102 }
ian@0 1103
ian@0 1104
ian@0 1105 static void check_duplex(struct net_device *dev)
ian@0 1106 {
ian@0 1107 struct netdev_private *np = netdev_priv(dev);
ian@0 1108 u16 reg0;
ian@0 1109 int silly_count = 1000;
ian@0 1110
ian@0 1111 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
ian@0 1112 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
ian@0 1113 udelay(500);
ian@0 1114 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
ian@0 1115 /* do nothing */;
ian@0 1116 if (!silly_count) {
ian@0 1117 printk("%s: MII reset failed!\n", dev->name);
ian@0 1118 return;
ian@0 1119 }
ian@0 1120
ian@0 1121 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
ian@0 1122
ian@0 1123 if (!np->mii_if.force_media) {
ian@0 1124 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
ian@0 1125 } else {
ian@0 1126 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
ian@0 1127 if (np->speed100)
ian@0 1128 reg0 |= BMCR_SPEED100;
ian@0 1129 if (np->mii_if.full_duplex)
ian@0 1130 reg0 |= BMCR_FULLDPLX;
ian@0 1131 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
ian@0 1132 dev->name,
ian@0 1133 np->speed100 ? "100" : "10",
ian@0 1134 np->mii_if.full_duplex ? "full" : "half");
ian@0 1135 }
ian@0 1136 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
ian@0 1137 }
ian@0 1138
ian@0 1139
ian@0 1140 static void tx_timeout(struct net_device *dev)
ian@0 1141 {
ian@0 1142 struct netdev_private *np = netdev_priv(dev);
ian@0 1143 void __iomem *ioaddr = np->base;
ian@0 1144 int old_debug;
ian@0 1145
ian@0 1146 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
ian@0 1147 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
ian@0 1148
ian@0 1149 /* Perhaps we should reinitialize the hardware here. */
ian@0 1150
ian@0 1151 /*
ian@0 1152 * Stop and restart the interface.
ian@0 1153 * Cheat and increase the debug level temporarily.
ian@0 1154 */
ian@0 1155 old_debug = debug;
ian@0 1156 debug = 2;
ian@0 1157 netdev_close(dev);
ian@0 1158 netdev_open(dev);
ian@0 1159 debug = old_debug;
ian@0 1160
ian@0 1161 /* Trigger an immediate transmit demand. */
ian@0 1162
ian@0 1163 dev->trans_start = jiffies;
ian@0 1164 np->stats.tx_errors++;
ian@0 1165 netif_wake_queue(dev);
ian@0 1166 }
ian@0 1167
ian@0 1168
ian@0 1169 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
ian@0 1170 static void init_ring(struct net_device *dev)
ian@0 1171 {
ian@0 1172 struct netdev_private *np = netdev_priv(dev);
ian@0 1173 int i;
ian@0 1174
ian@0 1175 np->cur_rx = np->cur_tx = np->reap_tx = 0;
ian@0 1176 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
ian@0 1177
ian@0 1178 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
ian@0 1179
ian@0 1180 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
ian@0 1181 for (i = 0; i < RX_RING_SIZE; i++) {
ian@0 1182 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
ian@0 1183 np->rx_info[i].skb = skb;
ian@0 1184 if (skb == NULL)
ian@0 1185 break;
ian@0 1186 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
ian@0 1187 skb->dev = dev; /* Mark as being used by this device. */
ian@0 1188 /* Grrr, we cannot offset to correctly align the IP header. */
ian@0 1189 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
ian@0 1190 }
ian@0 1191 writew(i - 1, np->base + RxDescQIdx);
ian@0 1192 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
ian@0 1193
ian@0 1194 /* Clear the remainder of the Rx buffer ring. */
ian@0 1195 for ( ; i < RX_RING_SIZE; i++) {
ian@0 1196 np->rx_ring[i].rxaddr = 0;
ian@0 1197 np->rx_info[i].skb = NULL;
ian@0 1198 np->rx_info[i].mapping = 0;
ian@0 1199 }
ian@0 1200 /* Mark the last entry as wrapping the ring. */
ian@0 1201 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
ian@0 1202
ian@0 1203 /* Clear the completion rings. */
ian@0 1204 for (i = 0; i < DONE_Q_SIZE; i++) {
ian@0 1205 np->rx_done_q[i].status = 0;
ian@0 1206 np->tx_done_q[i].status = 0;
ian@0 1207 }
ian@0 1208
ian@0 1209 for (i = 0; i < TX_RING_SIZE; i++)
ian@0 1210 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
ian@0 1211
ian@0 1212 return;
ian@0 1213 }
ian@0 1214
ian@0 1215
ian@0 1216 static int start_tx(struct sk_buff *skb, struct net_device *dev)
ian@0 1217 {
ian@0 1218 struct netdev_private *np = netdev_priv(dev);
ian@0 1219 unsigned int entry;
ian@0 1220 u32 status;
ian@0 1221 int i;
ian@0 1222
ian@0 1223 /*
ian@0 1224 * be cautious here, wrapping the queue has weird semantics
ian@0 1225 * and we may not have enough slots even when it seems we do.
ian@0 1226 */
ian@0 1227 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
ian@0 1228 netif_stop_queue(dev);
ian@0 1229 return 1;
ian@0 1230 }
ian@0 1231
ian@0 1232 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
ian@0 1233 if (skb->ip_summed == CHECKSUM_HW) {
ian@0 1234 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
ian@0 1235 return NETDEV_TX_OK;
ian@0 1236 }
ian@0 1237 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
ian@0 1238
ian@0 1239 entry = np->cur_tx % TX_RING_SIZE;
ian@0 1240 for (i = 0; i < skb_num_frags(skb); i++) {
ian@0 1241 int wrap_ring = 0;
ian@0 1242 status = TxDescID;
ian@0 1243
ian@0 1244 if (i == 0) {
ian@0 1245 np->tx_info[entry].skb = skb;
ian@0 1246 status |= TxCRCEn;
ian@0 1247 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
ian@0 1248 status |= TxRingWrap;
ian@0 1249 wrap_ring = 1;
ian@0 1250 }
ian@0 1251 if (np->reap_tx) {
ian@0 1252 status |= TxDescIntr;
ian@0 1253 np->reap_tx = 0;
ian@0 1254 }
ian@0 1255 if (skb->ip_summed == CHECKSUM_HW) {
ian@0 1256 status |= TxCalTCP;
ian@0 1257 np->stats.tx_compressed++;
ian@0 1258 }
ian@0 1259 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
ian@0 1260
ian@0 1261 np->tx_info[entry].mapping =
ian@0 1262 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
ian@0 1263 } else {
ian@0 1264 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
ian@0 1265 status |= this_frag->size;
ian@0 1266 np->tx_info[entry].mapping =
ian@0 1267 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
ian@0 1268 }
ian@0 1269
ian@0 1270 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
ian@0 1271 np->tx_ring[entry].status = cpu_to_le32(status);
ian@0 1272 if (debug > 3)
ian@0 1273 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
ian@0 1274 dev->name, np->cur_tx, np->dirty_tx,
ian@0 1275 entry, status);
ian@0 1276 if (wrap_ring) {
ian@0 1277 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
ian@0 1278 np->cur_tx += np->tx_info[entry].used_slots;
ian@0 1279 entry = 0;
ian@0 1280 } else {
ian@0 1281 np->tx_info[entry].used_slots = 1;
ian@0 1282 np->cur_tx += np->tx_info[entry].used_slots;
ian@0 1283 entry++;
ian@0 1284 }
ian@0 1285 /* scavenge the tx descriptors twice per TX_RING_SIZE */
ian@0 1286 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
ian@0 1287 np->reap_tx = 1;
ian@0 1288 }
ian@0 1289
ian@0 1290 /* Non-x86: explicitly flush descriptor cache lines here. */
ian@0 1291 /* Ensure all descriptors are written back before the transmit is
ian@0 1292 initiated. - Jes */
ian@0 1293 wmb();
ian@0 1294
ian@0 1295 /* Update the producer index. */
ian@0 1296 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
ian@0 1297
ian@0 1298 /* 4 is arbitrary, but should be ok */
ian@0 1299 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
ian@0 1300 netif_stop_queue(dev);
ian@0 1301
ian@0 1302 dev->trans_start = jiffies;
ian@0 1303
ian@0 1304 return 0;
ian@0 1305 }
ian@0 1306
ian@0 1307
ian@0 1308 /* The interrupt handler does all of the Rx thread work and cleans up
ian@0 1309 after the Tx thread. */
ian@0 1310 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
ian@0 1311 {
ian@0 1312 struct net_device *dev = dev_instance;
ian@0 1313 struct netdev_private *np = netdev_priv(dev);
ian@0 1314 void __iomem *ioaddr = np->base;
ian@0 1315 int boguscnt = max_interrupt_work;
ian@0 1316 int consumer;
ian@0 1317 int tx_status;
ian@0 1318 int handled = 0;
ian@0 1319
ian@0 1320 do {
ian@0 1321 u32 intr_status = readl(ioaddr + IntrClear);
ian@0 1322
ian@0 1323 if (debug > 4)
ian@0 1324 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
ian@0 1325 dev->name, intr_status);
ian@0 1326
ian@0 1327 if (intr_status == 0 || intr_status == (u32) -1)
ian@0 1328 break;
ian@0 1329
ian@0 1330 handled = 1;
ian@0 1331
ian@0 1332 if (intr_status & (IntrRxDone | IntrRxEmpty))
ian@0 1333 netdev_rx(dev, ioaddr);
ian@0 1334
ian@0 1335 /* Scavenge the skbuff list based on the Tx-done queue.
ian@0 1336 There are redundant checks here that may be cleaned up
ian@0 1337 after the driver has proven to be reliable. */
ian@0 1338 consumer = readl(ioaddr + TxConsumerIdx);
ian@0 1339 if (debug > 3)
ian@0 1340 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
ian@0 1341 dev->name, consumer);
ian@0 1342
ian@0 1343 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
ian@0 1344 if (debug > 3)
ian@0 1345 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
ian@0 1346 dev->name, np->dirty_tx, np->tx_done, tx_status);
ian@0 1347 if ((tx_status & 0xe0000000) == 0xa0000000) {
ian@0 1348 np->stats.tx_packets++;
ian@0 1349 } else if ((tx_status & 0xe0000000) == 0x80000000) {
ian@0 1350 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
ian@0 1351 struct sk_buff *skb = np->tx_info[entry].skb;
ian@0 1352 np->tx_info[entry].skb = NULL;
ian@0 1353 pci_unmap_single(np->pci_dev,
ian@0 1354 np->tx_info[entry].mapping,
ian@0 1355 skb_first_frag_len(skb),
ian@0 1356 PCI_DMA_TODEVICE);
ian@0 1357 np->tx_info[entry].mapping = 0;
ian@0 1358 np->dirty_tx += np->tx_info[entry].used_slots;
ian@0 1359 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
ian@0 1360 {
ian@0 1361 int i;
ian@0 1362 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
ian@0 1363 pci_unmap_single(np->pci_dev,
ian@0 1364 np->tx_info[entry].mapping,
ian@0 1365 skb_shinfo(skb)->frags[i].size,
ian@0 1366 PCI_DMA_TODEVICE);
ian@0 1367 np->dirty_tx++;
ian@0 1368 entry++;
ian@0 1369 }
ian@0 1370 }
ian@0 1371
ian@0 1372 dev_kfree_skb_irq(skb);
ian@0 1373 }
ian@0 1374 np->tx_done_q[np->tx_done].status = 0;
ian@0 1375 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
ian@0 1376 }
ian@0 1377 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
ian@0 1378
ian@0 1379 if (netif_queue_stopped(dev) &&
ian@0 1380 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
ian@0 1381 /* The ring is no longer full, wake the queue. */
ian@0 1382 netif_wake_queue(dev);
ian@0 1383 }
ian@0 1384
ian@0 1385 /* Stats overflow */
ian@0 1386 if (intr_status & IntrStatsMax)
ian@0 1387 get_stats(dev);
ian@0 1388
ian@0 1389 /* Media change interrupt. */
ian@0 1390 if (intr_status & IntrLinkChange)
ian@0 1391 netdev_media_change(dev);
ian@0 1392
ian@0 1393 /* Abnormal error summary/uncommon events handlers. */
ian@0 1394 if (intr_status & IntrAbnormalSummary)
ian@0 1395 netdev_error(dev, intr_status);
ian@0 1396
ian@0 1397 if (--boguscnt < 0) {
ian@0 1398 if (debug > 1)
ian@0 1399 printk(KERN_WARNING "%s: Too much work at interrupt, "
ian@0 1400 "status=%#8.8x.\n",
ian@0 1401 dev->name, intr_status);
ian@0 1402 break;
ian@0 1403 }
ian@0 1404 } while (1);
ian@0 1405
ian@0 1406 if (debug > 4)
ian@0 1407 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
ian@0 1408 dev->name, (int) readl(ioaddr + IntrStatus));
ian@0 1409 return IRQ_RETVAL(handled);
ian@0 1410 }
ian@0 1411
ian@0 1412
ian@0 1413 /* This routine is logically part of the interrupt/poll handler, but separated
ian@0 1414 for clarity, code sharing between NAPI/non-NAPI, and better register allocation. */
ian@0 1415 static int __netdev_rx(struct net_device *dev, int *quota)
ian@0 1416 {
ian@0 1417 struct netdev_private *np = netdev_priv(dev);
ian@0 1418 u32 desc_status;
ian@0 1419 int retcode = 0;
ian@0 1420
ian@0 1421 /* If EOP is set on the next entry, it's a new packet. Send it up. */
ian@0 1422 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
ian@0 1423 struct sk_buff *skb;
ian@0 1424 u16 pkt_len;
ian@0 1425 int entry;
ian@0 1426 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
ian@0 1427
ian@0 1428 if (debug > 4)
ian@0 1429 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
ian@0 1430 if (!(desc_status & RxOK)) {
ian@0 1431 /* There was an error. */
ian@0 1432 if (debug > 2)
ian@0 1433 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
ian@0 1434 np->stats.rx_errors++;
ian@0 1435 if (desc_status & RxFIFOErr)
ian@0 1436 np->stats.rx_fifo_errors++;
ian@0 1437 goto next_rx;
ian@0 1438 }
ian@0 1439
ian@0 1440 if (*quota <= 0) { /* out of rx quota */
ian@0 1441 retcode = 1;
ian@0 1442 goto out;
ian@0 1443 }
ian@0 1444 (*quota)--;
ian@0 1445
ian@0 1446 pkt_len = desc_status; /* Implicitly Truncate */
ian@0 1447 entry = (desc_status >> 16) & 0x7ff;
ian@0 1448
ian@0 1449 if (debug > 4)
ian@0 1450 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
ian@0 1451 /* Check if the packet is long enough to accept without copying
ian@0 1452 to a minimally-sized skbuff. */
ian@0 1453 if (pkt_len < rx_copybreak
ian@0 1454 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
ian@0 1455 skb->dev = dev;
ian@0 1456 skb_reserve(skb, 2); /* 16 byte align the IP header */
ian@0 1457 pci_dma_sync_single_for_cpu(np->pci_dev,
ian@0 1458 np->rx_info[entry].mapping,
ian@0 1459 pkt_len, PCI_DMA_FROMDEVICE);
ian@0 1460 eth_copy_and_sum(skb, np->rx_info[entry].skb->data, pkt_len, 0);
ian@0 1461 pci_dma_sync_single_for_device(np->pci_dev,
ian@0 1462 np->rx_info[entry].mapping,
ian@0 1463 pkt_len, PCI_DMA_FROMDEVICE);
ian@0 1464 skb_put(skb, pkt_len);
ian@0 1465 } else {
ian@0 1466 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
ian@0 1467 skb = np->rx_info[entry].skb;
ian@0 1468 skb_put(skb, pkt_len);
ian@0 1469 np->rx_info[entry].skb = NULL;
ian@0 1470 np->rx_info[entry].mapping = 0;
ian@0 1471 }
ian@0 1472 #ifndef final_version /* Remove after testing. */
ian@0 1473 /* You will want this info for the initial debug. */
ian@0 1474 if (debug > 5)
ian@0 1475 printk(KERN_DEBUG " Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:"
ian@0 1476 "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x.\n",
ian@0 1477 skb->data[0], skb->data[1], skb->data[2], skb->data[3],
ian@0 1478 skb->data[4], skb->data[5], skb->data[6], skb->data[7],
ian@0 1479 skb->data[8], skb->data[9], skb->data[10],
ian@0 1480 skb->data[11], skb->data[12], skb->data[13]);
ian@0 1481 #endif
ian@0 1482
ian@0 1483 skb->protocol = eth_type_trans(skb, dev);
ian@0 1484 #ifdef VLAN_SUPPORT
ian@0 1485 if (debug > 4)
ian@0 1486 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
ian@0 1487 #endif
ian@0 1488 if (le16_to_cpu(desc->status2) & 0x0100) {
ian@0 1489 skb->ip_summed = CHECKSUM_UNNECESSARY;
ian@0 1490 np->stats.rx_compressed++;
ian@0 1491 }
ian@0 1492 /*
ian@0 1493 * This feature doesn't seem to be working, at least
ian@0 1494 * with the two firmware versions I have. If the GFP sees
ian@0 1495 * an IP fragment, it either ignores it completely, or reports
ian@0 1496 * "bad checksum" on it.
ian@0 1497 *
ian@0 1498 * Maybe I missed something -- corrections are welcome.
ian@0 1499 * Until then, the printk stays. :-) -Ion
ian@0 1500 */
ian@0 1501 else if (le16_to_cpu(desc->status2) & 0x0040) {
ian@0 1502 skb->ip_summed = CHECKSUM_HW;
ian@0 1503 skb->csum = le16_to_cpu(desc->csum);
ian@0 1504 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
ian@0 1505 }
ian@0 1506 #ifdef VLAN_SUPPORT
ian@0 1507 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
ian@0 1508 if (debug > 4)
ian@0 1509 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", le16_to_cpu(desc->vlanid));
ian@0 1510 /* vlan_netdev_receive_skb() expects a packet with the VLAN tag stripped out */
ian@0 1511 vlan_netdev_receive_skb(skb, np->vlgrp, le16_to_cpu(desc->vlanid) & VLAN_VID_MASK);
ian@0 1512 } else
ian@0 1513 #endif /* VLAN_SUPPORT */
ian@0 1514 netdev_receive_skb(skb);
ian@0 1515 dev->last_rx = jiffies;
ian@0 1516 np->stats.rx_packets++;
ian@0 1517
ian@0 1518 next_rx:
ian@0 1519 np->cur_rx++;
ian@0 1520 desc->status = 0;
ian@0 1521 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
ian@0 1522 }
ian@0 1523 writew(np->rx_done, np->base + CompletionQConsumerIdx);
ian@0 1524
ian@0 1525 out:
ian@0 1526 refill_rx_ring(dev);
ian@0 1527 if (debug > 5)
ian@0 1528 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
ian@0 1529 retcode, np->rx_done, desc_status);
ian@0 1530 return retcode;
ian@0 1531 }
ian@0 1532
ian@0 1533
ian@0 1534 #ifdef HAVE_NETDEV_POLL
ian@0 1535 static int netdev_poll(struct net_device *dev, int *budget)
ian@0 1536 {
ian@0 1537 u32 intr_status;
ian@0 1538 struct netdev_private *np = netdev_priv(dev);
ian@0 1539 void __iomem *ioaddr = np->base;
ian@0 1540 int retcode = 0, quota = dev->quota;
ian@0 1541
ian@0 1542 do {
ian@0 1543 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
ian@0 1544
ian@0 1545 retcode = __netdev_rx(dev, &quota);
ian@0 1546 *budget -= (dev->quota - quota);
ian@0 1547 dev->quota = quota;
ian@0 1548 if (retcode)
ian@0 1549 goto out;
ian@0 1550
ian@0 1551 intr_status = readl(ioaddr + IntrStatus);
ian@0 1552 } while (intr_status & (IntrRxDone | IntrRxEmpty));
ian@0 1553
ian@0 1554 netif_rx_complete(dev);
ian@0 1555 intr_status = readl(ioaddr + IntrEnable);
ian@0 1556 intr_status |= IntrRxDone | IntrRxEmpty;
ian@0 1557 writel(intr_status, ioaddr + IntrEnable);
ian@0 1558
ian@0 1559 out:
ian@0 1560 if (debug > 5)
ian@0 1561 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n", retcode);
ian@0 1562
ian@0 1563 /* Restart Rx engine if stopped. */
ian@0 1564 return retcode;
ian@0 1565 }
ian@0 1566 #endif /* HAVE_NETDEV_POLL */
ian@0 1567
ian@0 1568
ian@0 1569 static void refill_rx_ring(struct net_device *dev)
ian@0 1570 {
ian@0 1571 struct netdev_private *np = netdev_priv(dev);
ian@0 1572 struct sk_buff *skb;
ian@0 1573 int entry = -1;
ian@0 1574
ian@0 1575 /* Refill the Rx ring buffers. */
ian@0 1576 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
ian@0 1577 entry = np->dirty_rx % RX_RING_SIZE;
ian@0 1578 if (np->rx_info[entry].skb == NULL) {
ian@0 1579 skb = dev_alloc_skb(np->rx_buf_sz);
ian@0 1580 np->rx_info[entry].skb = skb;
ian@0 1581 if (skb == NULL)
ian@0 1582 break; /* Better luck next round. */
ian@0 1583 np->rx_info[entry].mapping =
ian@0 1584 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
ian@0 1585 skb->dev = dev; /* Mark as being used by this device. */
ian@0 1586 np->rx_ring[entry].rxaddr =
ian@0 1587 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
ian@0 1588 }
ian@0 1589 if (entry == RX_RING_SIZE - 1)
ian@0 1590 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
ian@0 1591 }
ian@0 1592 if (entry >= 0)
ian@0 1593 writew(entry, np->base + RxDescQIdx);
ian@0 1594 }
ian@0 1595
ian@0 1596
ian@0 1597 static void netdev_media_change(struct net_device *dev)
ian@0 1598 {
ian@0 1599 struct netdev_private *np = netdev_priv(dev);
ian@0 1600 void __iomem *ioaddr = np->base;
ian@0 1601 u16 reg0, reg1, reg4, reg5;
ian@0 1602 u32 new_tx_mode;
ian@0 1603 u32 new_intr_timer_ctrl;
ian@0 1604
ian@0 1605 /* reset status first */
ian@0 1606 mdio_read(dev, np->phys[0], MII_BMCR);
ian@0 1607 mdio_read(dev, np->phys[0], MII_BMSR);
ian@0 1608
ian@0 1609 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
ian@0 1610 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
ian@0 1611
ian@0 1612 if (reg1 & BMSR_LSTATUS) {
ian@0 1613 /* link is up */
ian@0 1614 if (reg0 & BMCR_ANENABLE) {
ian@0 1615 /* autonegotiation is enabled */
ian@0 1616 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
ian@0 1617 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
ian@0 1618 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
ian@0 1619 np->speed100 = 1;
ian@0 1620 np->mii_if.full_duplex = 1;
ian@0 1621 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
ian@0 1622 np->speed100 = 1;
ian@0 1623 np->mii_if.full_duplex = 0;
ian@0 1624 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
ian@0 1625 np->speed100 = 0;
ian@0 1626 np->mii_if.full_duplex = 1;
ian@0 1627 } else {
ian@0 1628 np->speed100 = 0;
ian@0 1629 np->mii_if.full_duplex = 0;
ian@0 1630 }
ian@0 1631 } else {
ian@0 1632 /* autonegotiation is disabled */
ian@0 1633 if (reg0 & BMCR_SPEED100)
ian@0 1634 np->speed100 = 1;
ian@0 1635 else
ian@0 1636 np->speed100 = 0;
ian@0 1637 if (reg0 & BMCR_FULLDPLX)
ian@0 1638 np->mii_if.full_duplex = 1;
ian@0 1639 else
ian@0 1640 np->mii_if.full_duplex = 0;
ian@0 1641 }
ian@0 1642 netif_carrier_on(dev);
ian@0 1643 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
ian@0 1644 dev->name,
ian@0 1645 np->speed100 ? "100" : "10",
ian@0 1646 np->mii_if.full_duplex ? "full" : "half");
ian@0 1647
ian@0 1648 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
ian@0 1649 if (np->mii_if.full_duplex)
ian@0 1650 new_tx_mode |= FullDuplex;
ian@0 1651 if (np->tx_mode != new_tx_mode) {
ian@0 1652 np->tx_mode = new_tx_mode;
ian@0 1653 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
ian@0 1654 udelay(1000);
ian@0 1655 writel(np->tx_mode, ioaddr + TxMode);
ian@0 1656 }
ian@0 1657
ian@0 1658 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
ian@0 1659 if (np->speed100)
ian@0 1660 new_intr_timer_ctrl |= Timer10X;
ian@0 1661 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
ian@0 1662 np->intr_timer_ctrl = new_intr_timer_ctrl;
ian@0 1663 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
ian@0 1664 }
ian@0 1665 } else {
ian@0 1666 netif_carrier_off(dev);
ian@0 1667 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
ian@0 1668 }
ian@0 1669 }
ian@0 1670
ian@0 1671
ian@0 1672 static void netdev_error(struct net_device *dev, int intr_status)
ian@0 1673 {
ian@0 1674 struct netdev_private *np = netdev_priv(dev);
ian@0 1675
ian@0 1676 /* Came close to underrunning the Tx FIFO, increase threshold. */
ian@0 1677 if (intr_status & IntrTxDataLow) {
ian@0 1678 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
ian@0 1679 writel(++np->tx_threshold, np->base + TxThreshold);
ian@0 1680 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
ian@0 1681 dev->name, np->tx_threshold * 16);
ian@0 1682 } else
ian@0 1683 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
ian@0 1684 }
ian@0 1685 if (intr_status & IntrRxGFPDead) {
ian@0 1686 np->stats.rx_fifo_errors++;
ian@0 1687 np->stats.rx_errors++;
ian@0 1688 }
ian@0 1689 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
ian@0 1690 np->stats.tx_fifo_errors++;
ian@0 1691 np->stats.tx_errors++;
ian@0 1692 }
ian@0 1693 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
ian@0 1694 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
ian@0 1695 dev->name, intr_status);
ian@0 1696 }
ian@0 1697
ian@0 1698
ian@0 1699 static struct net_device_stats *get_stats(struct net_device *dev)
ian@0 1700 {
ian@0 1701 struct netdev_private *np = netdev_priv(dev);
ian@0 1702 void __iomem *ioaddr = np->base;
ian@0 1703
ian@0 1704 /* This adapter architecture needs no SMP locks. */
ian@0 1705 np->stats.tx_bytes = readl(ioaddr + 0x57010);
ian@0 1706 np->stats.rx_bytes = readl(ioaddr + 0x57044);
ian@0 1707 np->stats.tx_packets = readl(ioaddr + 0x57000);
ian@0 1708 np->stats.tx_aborted_errors =
ian@0 1709 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
ian@0 1710 np->stats.tx_window_errors = readl(ioaddr + 0x57018);
ian@0 1711 np->stats.collisions =
ian@0 1712 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
ian@0 1713
ian@0 1714 /* The chip only need report frame silently dropped. */
ian@0 1715 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
ian@0 1716 writew(0, ioaddr + RxDMAStatus);
ian@0 1717 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
ian@0 1718 np->stats.rx_frame_errors = readl(ioaddr + 0x57040);
ian@0 1719 np->stats.rx_length_errors = readl(ioaddr + 0x57058);
ian@0 1720 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
ian@0 1721
ian@0 1722 return &np->stats;
ian@0 1723 }
ian@0 1724
ian@0 1725
ian@0 1726 static void set_rx_mode(struct net_device *dev)
ian@0 1727 {
ian@0 1728 struct netdev_private *np = netdev_priv(dev);
ian@0 1729 void __iomem *ioaddr = np->base;
ian@0 1730 u32 rx_mode = MinVLANPrio;
ian@0 1731 struct dev_mc_list *mclist;
ian@0 1732 int i;
ian@0 1733 #ifdef VLAN_SUPPORT
ian@0 1734
ian@0 1735 rx_mode |= VlanMode;
ian@0 1736 if (np->vlgrp) {
ian@0 1737 int vlan_count = 0;
ian@0 1738 void __iomem *filter_addr = ioaddr + HashTable + 8;
ian@0 1739 for (i = 0; i < VLAN_VID_MASK; i++) {
ian@0 1740 if (np->vlgrp->vlan_devices[i]) {
ian@0 1741 if (vlan_count >= 32)
ian@0 1742 break;
ian@0 1743 writew(cpu_to_be16(i), filter_addr);
ian@0 1744 filter_addr += 16;
ian@0 1745 vlan_count++;
ian@0 1746 }
ian@0 1747 }
ian@0 1748 if (i == VLAN_VID_MASK) {
ian@0 1749 rx_mode |= PerfectFilterVlan;
ian@0 1750 while (vlan_count < 32) {
ian@0 1751 writew(0, filter_addr);
ian@0 1752 filter_addr += 16;
ian@0 1753 vlan_count++;
ian@0 1754 }
ian@0 1755 }
ian@0 1756 }
ian@0 1757 #endif /* VLAN_SUPPORT */
ian@0 1758
ian@0 1759 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
ian@0 1760 rx_mode |= AcceptAll;
ian@0 1761 } else if ((dev->mc_count > multicast_filter_limit)
ian@0 1762 || (dev->flags & IFF_ALLMULTI)) {
ian@0 1763 /* Too many to match, or accept all multicasts. */
ian@0 1764 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
ian@0 1765 } else if (dev->mc_count <= 14) {
ian@0 1766 /* Use the 16 element perfect filter, skip first two entries. */
ian@0 1767 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
ian@0 1768 u16 *eaddrs;
ian@0 1769 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
ian@0 1770 i++, mclist = mclist->next) {
ian@0 1771 eaddrs = (u16 *)mclist->dmi_addr;
ian@0 1772 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 4;
ian@0 1773 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4;
ian@0 1774 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 8;
ian@0 1775 }
ian@0 1776 eaddrs = (u16 *)dev->dev_addr;
ian@0 1777 while (i++ < 16) {
ian@0 1778 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4;
ian@0 1779 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4;
ian@0 1780 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8;
ian@0 1781 }
ian@0 1782 rx_mode |= AcceptBroadcast|PerfectFilter;
ian@0 1783 } else {
ian@0 1784 /* Must use a multicast hash table. */
ian@0 1785 void __iomem *filter_addr;
ian@0 1786 u16 *eaddrs;
ian@0 1787 u16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
ian@0 1788
ian@0 1789 memset(mc_filter, 0, sizeof(mc_filter));
ian@0 1790 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
ian@0 1791 i++, mclist = mclist->next) {
ian@0 1792 /* The chip uses the upper 9 CRC bits
ian@0 1793 as index into the hash table */
ian@0 1794 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
ian@0 1795 __u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1];
ian@0 1796
ian@0 1797 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
ian@0 1798 }
ian@0 1799 /* Clear the perfect filter list, skip first two entries. */
ian@0 1800 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
ian@0 1801 eaddrs = (u16 *)dev->dev_addr;
ian@0 1802 for (i = 2; i < 16; i++) {
ian@0 1803 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4;
ian@0 1804 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4;
ian@0 1805 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8;
ian@0 1806 }
ian@0 1807 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
ian@0 1808 writew(mc_filter[i], filter_addr);
ian@0 1809 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
ian@0 1810 }
ian@0 1811 writel(rx_mode, ioaddr + RxFilterMode);
ian@0 1812 }
ian@0 1813
ian@0 1814 static int check_if_running(struct net_device *dev)
ian@0 1815 {
ian@0 1816 if (!netif_running(dev))
ian@0 1817 return -EINVAL;
ian@0 1818 return 0;
ian@0 1819 }
ian@0 1820
ian@0 1821 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
ian@0 1822 {
ian@0 1823 struct netdev_private *np = netdev_priv(dev);
ian@0 1824 strcpy(info->driver, DRV_NAME);
ian@0 1825 strcpy(info->version, DRV_VERSION);
ian@0 1826 strcpy(info->bus_info, pci_name(np->pci_dev));
ian@0 1827 }
ian@0 1828
ian@0 1829 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
ian@0 1830 {
ian@0 1831 struct netdev_private *np = netdev_priv(dev);
ian@0 1832 spin_lock_irq(&np->lock);
ian@0 1833 mii_ethtool_gset(&np->mii_if, ecmd);
ian@0 1834 spin_unlock_irq(&np->lock);
ian@0 1835 return 0;
ian@0 1836 }
ian@0 1837
ian@0 1838 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
ian@0 1839 {
ian@0 1840 struct netdev_private *np = netdev_priv(dev);
ian@0 1841 int res;
ian@0 1842 spin_lock_irq(&np->lock);
ian@0 1843 res = mii_ethtool_sset(&np->mii_if, ecmd);
ian@0 1844 spin_unlock_irq(&np->lock);
ian@0 1845 check_duplex(dev);
ian@0 1846 return res;
ian@0 1847 }
ian@0 1848
ian@0 1849 static int nway_reset(struct net_device *dev)
ian@0 1850 {
ian@0 1851 struct netdev_private *np = netdev_priv(dev);
ian@0 1852 return mii_nway_restart(&np->mii_if);
ian@0 1853 }
ian@0 1854
ian@0 1855 static u32 get_link(struct net_device *dev)
ian@0 1856 {
ian@0 1857 struct netdev_private *np = netdev_priv(dev);
ian@0 1858 return mii_link_ok(&np->mii_if);
ian@0 1859 }
ian@0 1860
ian@0 1861 static u32 get_msglevel(struct net_device *dev)
ian@0 1862 {
ian@0 1863 return debug;
ian@0 1864 }
ian@0 1865
ian@0 1866 static void set_msglevel(struct net_device *dev, u32 val)
ian@0 1867 {
ian@0 1868 debug = val;
ian@0 1869 }
ian@0 1870
ian@0 1871 static struct ethtool_ops ethtool_ops = {
ian@0 1872 .begin = check_if_running,
ian@0 1873 .get_drvinfo = get_drvinfo,
ian@0 1874 .get_settings = get_settings,
ian@0 1875 .set_settings = set_settings,
ian@0 1876 .nway_reset = nway_reset,
ian@0 1877 .get_link = get_link,
ian@0 1878 .get_msglevel = get_msglevel,
ian@0 1879 .set_msglevel = set_msglevel,
ian@0 1880 };
ian@0 1881
ian@0 1882 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
ian@0 1883 {
ian@0 1884 struct netdev_private *np = netdev_priv(dev);
ian@0 1885 struct mii_ioctl_data *data = if_mii(rq);
ian@0 1886 int rc;
ian@0 1887
ian@0 1888 if (!netif_running(dev))
ian@0 1889 return -EINVAL;
ian@0 1890
ian@0 1891 spin_lock_irq(&np->lock);
ian@0 1892 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
ian@0 1893 spin_unlock_irq(&np->lock);
ian@0 1894
ian@0 1895 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
ian@0 1896 check_duplex(dev);
ian@0 1897
ian@0 1898 return rc;
ian@0 1899 }
ian@0 1900
ian@0 1901 static int netdev_close(struct net_device *dev)
ian@0 1902 {
ian@0 1903 struct netdev_private *np = netdev_priv(dev);
ian@0 1904 void __iomem *ioaddr = np->base;
ian@0 1905 int i;
ian@0 1906
ian@0 1907 netif_stop_queue(dev);
ian@0 1908
ian@0 1909 if (debug > 1) {
ian@0 1910 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
ian@0 1911 dev->name, (int) readl(ioaddr + IntrStatus));
ian@0 1912 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
ian@0 1913 dev->name, np->cur_tx, np->dirty_tx,
ian@0 1914 np->cur_rx, np->dirty_rx);
ian@0 1915 }
ian@0 1916
ian@0 1917 /* Disable interrupts by clearing the interrupt mask. */
ian@0 1918 writel(0, ioaddr + IntrEnable);
ian@0 1919
ian@0 1920 /* Stop the chip's Tx and Rx processes. */
ian@0 1921 writel(0, ioaddr + GenCtrl);
ian@0 1922 readl(ioaddr + GenCtrl);
ian@0 1923
ian@0 1924 if (debug > 5) {
ian@0 1925 printk(KERN_DEBUG" Tx ring at %#llx:\n",
ian@0 1926 (long long) np->tx_ring_dma);
ian@0 1927 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
ian@0 1928 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
ian@0 1929 i, le32_to_cpu(np->tx_ring[i].status),
ian@0 1930 (long long) dma_to_cpu(np->tx_ring[i].addr),
ian@0 1931 le32_to_cpu(np->tx_done_q[i].status));
ian@0 1932 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
ian@0 1933 (long long) np->rx_ring_dma, np->rx_done_q);
ian@0 1934 if (np->rx_done_q)
ian@0 1935 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
ian@0 1936 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
ian@0 1937 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
ian@0 1938 }
ian@0 1939 }
ian@0 1940
ian@0 1941 free_irq(dev->irq, dev);
ian@0 1942
ian@0 1943 /* Free all the skbuffs in the Rx queue. */
ian@0 1944 for (i = 0; i < RX_RING_SIZE; i++) {
ian@0 1945 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
ian@0 1946 if (np->rx_info[i].skb != NULL) {
ian@0 1947 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
ian@0 1948 dev_kfree_skb(np->rx_info[i].skb);
ian@0 1949 }
ian@0 1950 np->rx_info[i].skb = NULL;
ian@0 1951 np->rx_info[i].mapping = 0;
ian@0 1952 }
ian@0 1953 for (i = 0; i < TX_RING_SIZE; i++) {
ian@0 1954 struct sk_buff *skb = np->tx_info[i].skb;
ian@0 1955 if (skb == NULL)
ian@0 1956 continue;
ian@0 1957 pci_unmap_single(np->pci_dev,
ian@0 1958 np->tx_info[i].mapping,
ian@0 1959 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
ian@0 1960 np->tx_info[i].mapping = 0;
ian@0 1961 dev_kfree_skb(skb);
ian@0 1962 np->tx_info[i].skb = NULL;
ian@0 1963 }
ian@0 1964
ian@0 1965 return 0;
ian@0 1966 }
ian@0 1967
ian@0 1968 #ifdef CONFIG_PM
ian@0 1969 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
ian@0 1970 {
ian@0 1971 struct net_device *dev = pci_get_drvdata(pdev);
ian@0 1972
ian@0 1973 if (netif_running(dev)) {
ian@0 1974 netif_device_detach(dev);
ian@0 1975 netdev_close(dev);
ian@0 1976 }
ian@0 1977
ian@0 1978 pci_save_state(pdev);
ian@0 1979 pci_set_power_state(pdev, pci_choose_state(pdev,state));
ian@0 1980
ian@0 1981 return 0;
ian@0 1982 }
ian@0 1983
ian@0 1984 static int starfire_resume(struct pci_dev *pdev)
ian@0 1985 {
ian@0 1986 struct net_device *dev = pci_get_drvdata(pdev);
ian@0 1987
ian@0 1988 pci_set_power_state(pdev, PCI_D0);
ian@0 1989 pci_restore_state(pdev);
ian@0 1990
ian@0 1991 if (netif_running(dev)) {
ian@0 1992 netdev_open(dev);
ian@0 1993 netif_device_attach(dev);
ian@0 1994 }
ian@0 1995
ian@0 1996 return 0;
ian@0 1997 }
ian@0 1998 #endif /* CONFIG_PM */
ian@0 1999
ian@0 2000
ian@0 2001 static void __devexit starfire_remove_one (struct pci_dev *pdev)
ian@0 2002 {
ian@0 2003 struct net_device *dev = pci_get_drvdata(pdev);
ian@0 2004 struct netdev_private *np = netdev_priv(dev);
ian@0 2005
ian@0 2006 BUG_ON(!dev);
ian@0 2007
ian@0 2008 unregister_netdev(dev);
ian@0 2009
ian@0 2010 if (np->queue_mem)
ian@0 2011 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
ian@0 2012
ian@0 2013
ian@0 2014 /* XXX: add wakeup code -- requires firmware for MagicPacket */
ian@0 2015 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
ian@0 2016 pci_disable_device(pdev);
ian@0 2017
ian@0 2018 iounmap(np->base);
ian@0 2019 pci_release_regions(pdev);
ian@0 2020
ian@0 2021 pci_set_drvdata(pdev, NULL);
ian@0 2022 free_netdev(dev); /* Will also free np!! */
ian@0 2023 }
ian@0 2024
ian@0 2025
ian@0 2026 static struct pci_driver starfire_driver = {
ian@0 2027 .name = DRV_NAME,
ian@0 2028 .probe = starfire_init_one,
ian@0 2029 .remove = __devexit_p(starfire_remove_one),
ian@0 2030 #ifdef CONFIG_PM
ian@0 2031 .suspend = starfire_suspend,
ian@0 2032 .resume = starfire_resume,
ian@0 2033 #endif /* CONFIG_PM */
ian@0 2034 .id_table = starfire_pci_tbl,
ian@0 2035 };
ian@0 2036
ian@0 2037
ian@0 2038 static int __init starfire_init (void)
ian@0 2039 {
ian@0 2040 /* when a module, this is printed whether or not devices are found in probe */
ian@0 2041 #ifdef MODULE
ian@0 2042 printk(version);
ian@0 2043 #ifdef HAVE_NETDEV_POLL
ian@0 2044 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
ian@0 2045 #else
ian@0 2046 printk(KERN_INFO DRV_NAME ": polling (NAPI) disabled\n");
ian@0 2047 #endif
ian@0 2048 #endif
ian@0 2049
ian@0 2050 /* we can do this test only at run-time... sigh */
ian@0 2051 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) {
ian@0 2052 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
ian@0 2053 return -ENODEV;
ian@0 2054 }
ian@0 2055
ian@0 2056 return pci_module_init (&starfire_driver);
ian@0 2057 }
ian@0 2058
ian@0 2059
ian@0 2060 static void __exit starfire_cleanup (void)
ian@0 2061 {
ian@0 2062 pci_unregister_driver (&starfire_driver);
ian@0 2063 }
ian@0 2064
ian@0 2065
ian@0 2066 module_init(starfire_init);
ian@0 2067 module_exit(starfire_cleanup);
ian@0 2068
ian@0 2069
ian@0 2070 /*
ian@0 2071 * Local variables:
ian@0 2072 * c-basic-offset: 8
ian@0 2073 * tab-width: 8
ian@0 2074 * End:
ian@0 2075 */