ia64/linux-2.6.18-xen.hg

annotate drivers/atm/nicstar.h @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
rev   line source
ian@0 1 /******************************************************************************
ian@0 2 *
ian@0 3 * nicstar.h
ian@0 4 *
ian@0 5 * Header file for the nicstar device driver.
ian@0 6 *
ian@0 7 * Author: Rui Prior (rprior@inescn.pt)
ian@0 8 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
ian@0 9 *
ian@0 10 * (C) INESC 1998
ian@0 11 *
ian@0 12 ******************************************************************************/
ian@0 13
ian@0 14
ian@0 15 #ifndef _LINUX_NICSTAR_H_
ian@0 16 #define _LINUX_NICSTAR_H_
ian@0 17
ian@0 18
ian@0 19 /* Includes *******************************************************************/
ian@0 20
ian@0 21 #include <linux/types.h>
ian@0 22 #include <linux/pci.h>
ian@0 23 #include <linux/uio.h>
ian@0 24 #include <linux/skbuff.h>
ian@0 25 #include <linux/atmdev.h>
ian@0 26 #include <linux/atm_nicstar.h>
ian@0 27
ian@0 28
ian@0 29 /* Options ********************************************************************/
ian@0 30
ian@0 31 #undef NS_DEBUG_SPINLOCKS
ian@0 32
ian@0 33 #define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards
ian@0 34 controlled by the device driver. Must
ian@0 35 be <= 5 */
ian@0 36
ian@0 37 #undef RCQ_SUPPORT /* Do not define this for now */
ian@0 38
ian@0 39 #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
ian@0 40 #define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */
ian@0 41
ian@0 42 #define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */
ian@0 43 #define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */
ian@0 44 #define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */
ian@0 45 #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
ian@0 46
ian@0 47 #define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384.
ian@0 48 Define 4096 only if (all) your card(s)
ian@0 49 have 32K x 32bit SRAM, in which case
ian@0 50 setting this to 16384 will just waste a
ian@0 51 lot of memory.
ian@0 52 Setting this to 4096 for a card with
ian@0 53 128K x 32bit SRAM will limit the maximum
ian@0 54 VCI. */
ian@0 55
ian@0 56 /*#define NS_PCI_LATENCY 64*/ /* Must be a multiple of 32 */
ian@0 57
ian@0 58 /* Number of buffers initially allocated */
ian@0 59 #define NUM_SB 32 /* Must be even */
ian@0 60 #define NUM_LB 24 /* Must be even */
ian@0 61 #define NUM_HB 8 /* Pre-allocated huge buffers */
ian@0 62 #define NUM_IOVB 48 /* Iovec buffers */
ian@0 63
ian@0 64 /* Lower level for count of buffers */
ian@0 65 #define MIN_SB 8 /* Must be even */
ian@0 66 #define MIN_LB 8 /* Must be even */
ian@0 67 #define MIN_HB 6
ian@0 68 #define MIN_IOVB 8
ian@0 69
ian@0 70 /* Upper level for count of buffers */
ian@0 71 #define MAX_SB 64 /* Must be even, <= 508 */
ian@0 72 #define MAX_LB 48 /* Must be even, <= 508 */
ian@0 73 #define MAX_HB 10
ian@0 74 #define MAX_IOVB 80
ian@0 75
ian@0 76 /* These are the absolute maximum allowed for the ioctl() */
ian@0 77 #define TOP_SB 256 /* Must be even, <= 508 */
ian@0 78 #define TOP_LB 128 /* Must be even, <= 508 */
ian@0 79 #define TOP_HB 64
ian@0 80 #define TOP_IOVB 256
ian@0 81
ian@0 82
ian@0 83 #define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */
ian@0 84 #define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */
ian@0 85
ian@0 86 #undef ENABLE_TSQFIE
ian@0 87
ian@0 88 #define SCQFULL_TIMEOUT (5 * HZ)
ian@0 89
ian@0 90 #define NS_POLL_PERIOD (HZ)
ian@0 91
ian@0 92 #define PCR_TOLERANCE (1.0001)
ian@0 93
ian@0 94
ian@0 95
ian@0 96 /* ESI stuff ******************************************************************/
ian@0 97
ian@0 98 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
ian@0 99 #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
ian@0 100
ian@0 101
ian@0 102 /* #defines *******************************************************************/
ian@0 103
ian@0 104 #define NS_IOREMAP_SIZE 4096
ian@0 105
ian@0 106 /*
ian@0 107 * BUF_XX distinguish the Rx buffers depending on their (small/large) size.
ian@0 108 * BUG_SM and BUG_LG are both used by the driver and the device.
ian@0 109 * BUF_NONE is only used by the driver.
ian@0 110 */
ian@0 111 #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
ian@0 112 #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
ian@0 113 #define BUF_NONE 0xffffffff /* Software only: */
ian@0 114
ian@0 115 #define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */
ian@0 116 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
ian@0 117 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
ian@0 118 #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
ian@0 119
ian@0 120 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
ian@0 121 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
ian@0 122
ian@0 123 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
ian@0 124
ian@0 125 #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
ian@0 126 #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
ian@0 127
ian@0 128
ian@0 129 /* NICStAR structures located in host memory **********************************/
ian@0 130
ian@0 131
ian@0 132
ian@0 133 /* RSQ - Receive Status Queue
ian@0 134 *
ian@0 135 * Written by the NICStAR, read by the device driver.
ian@0 136 */
ian@0 137
ian@0 138 typedef struct ns_rsqe
ian@0 139 {
ian@0 140 u32 word_1;
ian@0 141 u32 buffer_handle;
ian@0 142 u32 final_aal5_crc32;
ian@0 143 u32 word_4;
ian@0 144 } ns_rsqe;
ian@0 145
ian@0 146 #define ns_rsqe_vpi(ns_rsqep) \
ian@0 147 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
ian@0 148 #define ns_rsqe_vci(ns_rsqep) \
ian@0 149 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
ian@0 150
ian@0 151 #define NS_RSQE_VALID 0x80000000
ian@0 152 #define NS_RSQE_NZGFC 0x00004000
ian@0 153 #define NS_RSQE_EOPDU 0x00002000
ian@0 154 #define NS_RSQE_BUFSIZE 0x00001000
ian@0 155 #define NS_RSQE_CONGESTION 0x00000800
ian@0 156 #define NS_RSQE_CLP 0x00000400
ian@0 157 #define NS_RSQE_CRCERR 0x00000200
ian@0 158
ian@0 159 #define NS_RSQE_BUFSIZE_SM 0x00000000
ian@0 160 #define NS_RSQE_BUFSIZE_LG 0x00001000
ian@0 161
ian@0 162 #define ns_rsqe_valid(ns_rsqep) \
ian@0 163 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
ian@0 164 #define ns_rsqe_nzgfc(ns_rsqep) \
ian@0 165 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
ian@0 166 #define ns_rsqe_eopdu(ns_rsqep) \
ian@0 167 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
ian@0 168 #define ns_rsqe_bufsize(ns_rsqep) \
ian@0 169 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
ian@0 170 #define ns_rsqe_congestion(ns_rsqep) \
ian@0 171 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
ian@0 172 #define ns_rsqe_clp(ns_rsqep) \
ian@0 173 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
ian@0 174 #define ns_rsqe_crcerr(ns_rsqep) \
ian@0 175 (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
ian@0 176
ian@0 177 #define ns_rsqe_cellcount(ns_rsqep) \
ian@0 178 (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
ian@0 179 #define ns_rsqe_init(ns_rsqep) \
ian@0 180 ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
ian@0 181
ian@0 182 #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
ian@0 183 #define NS_RSQ_ALIGNMENT NS_RSQSIZE
ian@0 184
ian@0 185
ian@0 186
ian@0 187 /* RCQ - Raw Cell Queue
ian@0 188 *
ian@0 189 * Written by the NICStAR, read by the device driver.
ian@0 190 */
ian@0 191
ian@0 192 typedef struct cell_payload
ian@0 193 {
ian@0 194 u32 word[12];
ian@0 195 } cell_payload;
ian@0 196
ian@0 197 typedef struct ns_rcqe
ian@0 198 {
ian@0 199 u32 word_1;
ian@0 200 u32 word_2;
ian@0 201 u32 word_3;
ian@0 202 u32 word_4;
ian@0 203 cell_payload payload;
ian@0 204 } ns_rcqe;
ian@0 205
ian@0 206 #define NS_RCQE_SIZE 64 /* bytes */
ian@0 207
ian@0 208 #define ns_rcqe_islast(ns_rcqep) \
ian@0 209 (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
ian@0 210 #define ns_rcqe_cellheader(ns_rcqep) \
ian@0 211 (le32_to_cpu((ns_rcqep)->word_1))
ian@0 212 #define ns_rcqe_nextbufhandle(ns_rcqep) \
ian@0 213 (le32_to_cpu((ns_rcqep)->word_2))
ian@0 214
ian@0 215
ian@0 216
ian@0 217 /* SCQ - Segmentation Channel Queue
ian@0 218 *
ian@0 219 * Written by the device driver, read by the NICStAR.
ian@0 220 */
ian@0 221
ian@0 222 typedef struct ns_scqe
ian@0 223 {
ian@0 224 u32 word_1;
ian@0 225 u32 word_2;
ian@0 226 u32 word_3;
ian@0 227 u32 word_4;
ian@0 228 } ns_scqe;
ian@0 229
ian@0 230 /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
ian@0 231 or TSR (Transmit Status Requests) */
ian@0 232
ian@0 233 #define NS_SCQE_TYPE_TBD 0x00000000
ian@0 234 #define NS_SCQE_TYPE_TSR 0x80000000
ian@0 235
ian@0 236
ian@0 237 #define NS_TBD_EOPDU 0x40000000
ian@0 238 #define NS_TBD_AAL0 0x00000000
ian@0 239 #define NS_TBD_AAL34 0x04000000
ian@0 240 #define NS_TBD_AAL5 0x08000000
ian@0 241
ian@0 242 #define NS_TBD_VPI_MASK 0x0FF00000
ian@0 243 #define NS_TBD_VCI_MASK 0x000FFFF0
ian@0 244 #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
ian@0 245
ian@0 246 #define NS_TBD_VPI_SHIFT 20
ian@0 247 #define NS_TBD_VCI_SHIFT 4
ian@0 248
ian@0 249 #define ns_tbd_mkword_1(flags, m, n, buflen) \
ian@0 250 (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
ian@0 251 #define ns_tbd_mkword_1_novbr(flags, buflen) \
ian@0 252 (cpu_to_le32((flags) | (buflen) | 0x00810000))
ian@0 253 #define ns_tbd_mkword_3(control, pdulen) \
ian@0 254 (cpu_to_le32((control) << 16 | (pdulen)))
ian@0 255 #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
ian@0 256 (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
ian@0 257
ian@0 258
ian@0 259 #define NS_TSR_INTENABLE 0x20000000
ian@0 260
ian@0 261 #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */
ian@0 262
ian@0 263 #define ns_tsr_mkword_1(flags) \
ian@0 264 (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
ian@0 265 #define ns_tsr_mkword_2(scdi, scqi) \
ian@0 266 (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
ian@0 267
ian@0 268 #define ns_scqe_is_tsr(ns_scqep) \
ian@0 269 (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
ian@0 270
ian@0 271 #define VBR_SCQ_NUM_ENTRIES 512
ian@0 272 #define VBR_SCQSIZE 8192
ian@0 273 #define CBR_SCQ_NUM_ENTRIES 64
ian@0 274 #define CBR_SCQSIZE 1024
ian@0 275
ian@0 276 #define NS_SCQE_SIZE 16
ian@0 277
ian@0 278
ian@0 279
ian@0 280 /* TSQ - Transmit Status Queue
ian@0 281 *
ian@0 282 * Written by the NICStAR, read by the device driver.
ian@0 283 */
ian@0 284
ian@0 285 typedef struct ns_tsi
ian@0 286 {
ian@0 287 u32 word_1;
ian@0 288 u32 word_2;
ian@0 289 } ns_tsi;
ian@0 290
ian@0 291 /* NOTE: The first word can be a status word copied from the TSR which
ian@0 292 originated the TSI, or a timer overflow indicator. In this last
ian@0 293 case, the value of the first word is all zeroes. */
ian@0 294
ian@0 295 #define NS_TSI_EMPTY 0x80000000
ian@0 296 #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
ian@0 297
ian@0 298 #define ns_tsi_isempty(ns_tsip) \
ian@0 299 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
ian@0 300 #define ns_tsi_gettimestamp(ns_tsip) \
ian@0 301 (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
ian@0 302
ian@0 303 #define ns_tsi_init(ns_tsip) \
ian@0 304 ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
ian@0 305
ian@0 306
ian@0 307 #define NS_TSQSIZE 8192
ian@0 308 #define NS_TSQ_NUM_ENTRIES 1024
ian@0 309 #define NS_TSQ_ALIGNMENT 8192
ian@0 310
ian@0 311
ian@0 312 #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
ian@0 313
ian@0 314 #define ns_tsi_tmrof(ns_tsip) \
ian@0 315 (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
ian@0 316 #define ns_tsi_getscdindex(ns_tsip) \
ian@0 317 ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
ian@0 318 #define ns_tsi_getscqpos(ns_tsip) \
ian@0 319 (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
ian@0 320
ian@0 321
ian@0 322
ian@0 323 /* NICStAR structures located in local SRAM ***********************************/
ian@0 324
ian@0 325
ian@0 326
ian@0 327 /* RCT - Receive Connection Table
ian@0 328 *
ian@0 329 * Written by both the NICStAR and the device driver.
ian@0 330 */
ian@0 331
ian@0 332 typedef struct ns_rcte
ian@0 333 {
ian@0 334 u32 word_1;
ian@0 335 u32 buffer_handle;
ian@0 336 u32 dma_address;
ian@0 337 u32 aal5_crc32;
ian@0 338 } ns_rcte;
ian@0 339
ian@0 340 #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */
ian@0 341 #define NS_RCTE_NZGFC 0x00100000
ian@0 342 #define NS_RCTE_CONNECTOPEN 0x00080000
ian@0 343 #define NS_RCTE_AALMASK 0x00070000
ian@0 344 #define NS_RCTE_AAL0 0x00000000
ian@0 345 #define NS_RCTE_AAL34 0x00010000
ian@0 346 #define NS_RCTE_AAL5 0x00020000
ian@0 347 #define NS_RCTE_RCQ 0x00030000
ian@0 348 #define NS_RCTE_RAWCELLINTEN 0x00008000
ian@0 349 #define NS_RCTE_RXCONSTCELLADDR 0x00004000
ian@0 350 #define NS_RCTE_BUFFVALID 0x00002000
ian@0 351 #define NS_RCTE_FBDSIZE 0x00001000
ian@0 352 #define NS_RCTE_EFCI 0x00000800
ian@0 353 #define NS_RCTE_CLP 0x00000400
ian@0 354 #define NS_RCTE_CRCERROR 0x00000200
ian@0 355 #define NS_RCTE_CELLCOUNT_MASK 0x000001FF
ian@0 356
ian@0 357 #define NS_RCTE_FBDSIZE_SM 0x00000000
ian@0 358 #define NS_RCTE_FBDSIZE_LG 0x00001000
ian@0 359
ian@0 360 #define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */
ian@0 361
ian@0 362 /* NOTE: We could make macros to contruct the first word of the RCTE,
ian@0 363 but that doesn't seem to make much sense... */
ian@0 364
ian@0 365
ian@0 366
ian@0 367 /* FBD - Free Buffer Descriptor
ian@0 368 *
ian@0 369 * Written by the device driver using via the command register.
ian@0 370 */
ian@0 371
ian@0 372 typedef struct ns_fbd
ian@0 373 {
ian@0 374 u32 buffer_handle;
ian@0 375 u32 dma_address;
ian@0 376 } ns_fbd;
ian@0 377
ian@0 378
ian@0 379
ian@0 380
ian@0 381 /* TST - Transmit Schedule Table
ian@0 382 *
ian@0 383 * Written by the device driver.
ian@0 384 */
ian@0 385
ian@0 386 typedef u32 ns_tste;
ian@0 387
ian@0 388 #define NS_TST_OPCODE_MASK 0x60000000
ian@0 389
ian@0 390 #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
ian@0 391 #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
ian@0 392 #define NS_TST_OPCODE_VARIABLE 0x40000000
ian@0 393 #define NS_TST_OPCODE_END 0x60000000 /* Jump */
ian@0 394
ian@0 395 #define ns_tste_make(opcode, sramad) (opcode | sramad)
ian@0 396
ian@0 397 /* NOTE:
ian@0 398
ian@0 399 - When the opcode is FIXED, sramad specifies the SRAM address of the
ian@0 400 SCD for that fixed rate channel.
ian@0 401 - When the opcode is END, sramad specifies the SRAM address of the
ian@0 402 location of the next TST entry to read.
ian@0 403 */
ian@0 404
ian@0 405
ian@0 406
ian@0 407 /* SCD - Segmentation Channel Descriptor
ian@0 408 *
ian@0 409 * Written by both the device driver and the NICStAR
ian@0 410 */
ian@0 411
ian@0 412 typedef struct ns_scd
ian@0 413 {
ian@0 414 u32 word_1;
ian@0 415 u32 word_2;
ian@0 416 u32 partial_aal5_crc;
ian@0 417 u32 reserved;
ian@0 418 ns_scqe cache_a;
ian@0 419 ns_scqe cache_b;
ian@0 420 } ns_scd;
ian@0 421
ian@0 422 #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
ian@0 423 #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
ian@0 424 #define NS_SCD_TAIL_MASK_VAR 0x00001FF0
ian@0 425 #define NS_SCD_TAIL_MASK_FIX 0x000003F0
ian@0 426 #define NS_SCD_HEAD_MASK_VAR 0x00001FF0
ian@0 427 #define NS_SCD_HEAD_MASK_FIX 0x000003F0
ian@0 428 #define NS_SCD_XMITFOREVER 0x02000000
ian@0 429
ian@0 430 /* NOTE: There are other fields in word 2 of the SCD, but as they should
ian@0 431 not be needed in the device driver they are not defined here. */
ian@0 432
ian@0 433
ian@0 434
ian@0 435
ian@0 436 /* NICStAR local SRAM memory map **********************************************/
ian@0 437
ian@0 438
ian@0 439 #define NS_RCT 0x00000
ian@0 440 #define NS_RCT_32_END 0x03FFF
ian@0 441 #define NS_RCT_128_END 0x0FFFF
ian@0 442 #define NS_UNUSED_32 0x04000
ian@0 443 #define NS_UNUSED_128 0x10000
ian@0 444 #define NS_UNUSED_END 0x1BFFF
ian@0 445 #define NS_TST_FRSCD 0x1C000
ian@0 446 #define NS_TST_FRSCD_END 0x1E7DB
ian@0 447 #define NS_VRSCD2 0x1E7DC
ian@0 448 #define NS_VRSCD2_END 0x1E7E7
ian@0 449 #define NS_VRSCD1 0x1E7E8
ian@0 450 #define NS_VRSCD1_END 0x1E7F3
ian@0 451 #define NS_VRSCD0 0x1E7F4
ian@0 452 #define NS_VRSCD0_END 0x1E7FF
ian@0 453 #define NS_RXFIFO 0x1E800
ian@0 454 #define NS_RXFIFO_END 0x1F7FF
ian@0 455 #define NS_SMFBQ 0x1F800
ian@0 456 #define NS_SMFBQ_END 0x1FBFF
ian@0 457 #define NS_LGFBQ 0x1FC00
ian@0 458 #define NS_LGFBQ_END 0x1FFFF
ian@0 459
ian@0 460
ian@0 461
ian@0 462 /* NISCtAR operation registers ************************************************/
ian@0 463
ian@0 464
ian@0 465 /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
ian@0 466
ian@0 467 enum ns_regs
ian@0 468 {
ian@0 469 DR0 = 0x00, /* Data Register 0 R/W*/
ian@0 470 DR1 = 0x04, /* Data Register 1 W */
ian@0 471 DR2 = 0x08, /* Data Register 2 W */
ian@0 472 DR3 = 0x0C, /* Data Register 3 W */
ian@0 473 CMD = 0x10, /* Command W */
ian@0 474 CFG = 0x14, /* Configuration R/W */
ian@0 475 STAT = 0x18, /* Status R/W */
ian@0 476 RSQB = 0x1C, /* Receive Status Queue Base W */
ian@0 477 RSQT = 0x20, /* Receive Status Queue Tail R */
ian@0 478 RSQH = 0x24, /* Receive Status Queue Head W */
ian@0 479 CDC = 0x28, /* Cell Drop Counter R/clear */
ian@0 480 VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
ian@0 481 ICC = 0x30, /* Invalid Cell Count R/clear */
ian@0 482 RAWCT = 0x34, /* Raw Cell Tail R */
ian@0 483 TMR = 0x38, /* Timer R */
ian@0 484 TSTB = 0x3C, /* Transmit Schedule Table Base R/W */
ian@0 485 TSQB = 0x40, /* Transmit Status Queue Base W */
ian@0 486 TSQT = 0x44, /* Transmit Status Queue Tail R */
ian@0 487 TSQH = 0x48, /* Transmit Status Queue Head W */
ian@0 488 GP = 0x4C, /* General Purpose R/W */
ian@0 489 VPM = 0x50 /* VPI/VCI Mask W */
ian@0 490 };
ian@0 491
ian@0 492
ian@0 493 /* NICStAR commands issued to the CMD register ********************************/
ian@0 494
ian@0 495
ian@0 496 /* Top 4 bits are command opcode, lower 28 are parameters. */
ian@0 497
ian@0 498 #define NS_CMD_NO_OPERATION 0x00000000
ian@0 499 /* params always 0 */
ian@0 500
ian@0 501 #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
ian@0 502 /* b19{1=open,0=close} b18-2{SRAM addr} */
ian@0 503
ian@0 504 #define NS_CMD_WRITE_SRAM 0x40000000
ian@0 505 /* b18-2{SRAM addr} b1-0{burst size} */
ian@0 506
ian@0 507 #define NS_CMD_READ_SRAM 0x50000000
ian@0 508 /* b18-2{SRAM addr} */
ian@0 509
ian@0 510 #define NS_CMD_WRITE_FREEBUFQ 0x60000000
ian@0 511 /* b0{large buf indicator} */
ian@0 512
ian@0 513 #define NS_CMD_READ_UTILITY 0x80000000
ian@0 514 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
ian@0 515
ian@0 516 #define NS_CMD_WRITE_UTILITY 0x90000000
ian@0 517 /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
ian@0 518
ian@0 519 #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
ian@0 520 #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
ian@0 521
ian@0 522
ian@0 523 /* NICStAR configuration bits *************************************************/
ian@0 524
ian@0 525 #define NS_CFG_SWRST 0x80000000 /* Software Reset */
ian@0 526 #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */
ian@0 527 #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */
ian@0 528 #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */
ian@0 529 #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue
ian@0 530 Interrupt Enable */
ian@0 531 #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */
ian@0 532 #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
ian@0 533 #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */
ian@0 534 #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */
ian@0 535 #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */
ian@0 536 #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
ian@0 537 #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt
ian@0 538 Handling */
ian@0 539 #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
ian@0 540 #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full
ian@0 541 Interrupt Enable */
ian@0 542 #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */
ian@0 543 #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt
ian@0 544 Enable */
ian@0 545 #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
ian@0 546 #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt
ian@0 547 Enable */
ian@0 548 #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
ian@0 549 Enable */
ian@0 550 #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
ian@0 551 #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full
ian@0 552 Interrupt Enable */
ian@0 553 #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
ian@0 554
ian@0 555 #define NS_CFG_SMBUFSIZE_48 0x00000000
ian@0 556 #define NS_CFG_SMBUFSIZE_96 0x08000000
ian@0 557 #define NS_CFG_SMBUFSIZE_240 0x10000000
ian@0 558 #define NS_CFG_SMBUFSIZE_2048 0x18000000
ian@0 559
ian@0 560 #define NS_CFG_LGBUFSIZE_2048 0x00000000
ian@0 561 #define NS_CFG_LGBUFSIZE_4096 0x02000000
ian@0 562 #define NS_CFG_LGBUFSIZE_8192 0x04000000
ian@0 563 #define NS_CFG_LGBUFSIZE_16384 0x06000000
ian@0 564
ian@0 565 #define NS_CFG_RSQSIZE_2048 0x00000000
ian@0 566 #define NS_CFG_RSQSIZE_4096 0x00400000
ian@0 567 #define NS_CFG_RSQSIZE_8192 0x00800000
ian@0 568
ian@0 569 #define NS_CFG_VPIBITS_0 0x00000000
ian@0 570 #define NS_CFG_VPIBITS_1 0x00040000
ian@0 571 #define NS_CFG_VPIBITS_2 0x00080000
ian@0 572 #define NS_CFG_VPIBITS_8 0x000C0000
ian@0 573
ian@0 574 #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000
ian@0 575 #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000
ian@0 576 #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
ian@0 577
ian@0 578 #define NS_CFG_RXINT_NOINT 0x00000000
ian@0 579 #define NS_CFG_RXINT_NODELAY 0x00001000
ian@0 580 #define NS_CFG_RXINT_314US 0x00002000
ian@0 581 #define NS_CFG_RXINT_624US 0x00003000
ian@0 582 #define NS_CFG_RXINT_899US 0x00004000
ian@0 583
ian@0 584
ian@0 585 /* NICStAR STATus bits ********************************************************/
ian@0 586
ian@0 587 #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
ian@0 588 #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
ian@0 589 #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */
ian@0 590 #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */
ian@0 591 #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */
ian@0 592 #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */
ian@0 593 #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */
ian@0 594 #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */
ian@0 595 #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */
ian@0 596 #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */
ian@0 597 #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */
ian@0 598 #define NS_STAT_EOPDU 0x00000020 /* End of PDU */
ian@0 599 #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
ian@0 600 #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */
ian@0 601 #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */
ian@0 602 #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
ian@0 603
ian@0 604 #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
ian@0 605 #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
ian@0 606
ian@0 607
ian@0 608
ian@0 609 /* #defines which depend on other #defines ************************************/
ian@0 610
ian@0 611
ian@0 612 #define NS_TST0 NS_TST_FRSCD
ian@0 613 #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
ian@0 614
ian@0 615 #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
ian@0 616 #define NS_FRSCD_SIZE 12 /* 12 dwords */
ian@0 617 #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
ian@0 618
ian@0 619 #if (NS_SMBUFSIZE == 48)
ian@0 620 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
ian@0 621 #elif (NS_SMBUFSIZE == 96)
ian@0 622 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
ian@0 623 #elif (NS_SMBUFSIZE == 240)
ian@0 624 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
ian@0 625 #elif (NS_SMBUFSIZE == 2048)
ian@0 626 #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
ian@0 627 #else
ian@0 628 #error NS_SMBUFSIZE is incorrect in nicstar.h
ian@0 629 #endif /* NS_SMBUFSIZE */
ian@0 630
ian@0 631 #if (NS_LGBUFSIZE == 2048)
ian@0 632 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
ian@0 633 #elif (NS_LGBUFSIZE == 4096)
ian@0 634 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
ian@0 635 #elif (NS_LGBUFSIZE == 8192)
ian@0 636 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
ian@0 637 #elif (NS_LGBUFSIZE == 16384)
ian@0 638 #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
ian@0 639 #else
ian@0 640 #error NS_LGBUFSIZE is incorrect in nicstar.h
ian@0 641 #endif /* NS_LGBUFSIZE */
ian@0 642
ian@0 643 #if (NS_RSQSIZE == 2048)
ian@0 644 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
ian@0 645 #elif (NS_RSQSIZE == 4096)
ian@0 646 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
ian@0 647 #elif (NS_RSQSIZE == 8192)
ian@0 648 #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
ian@0 649 #else
ian@0 650 #error NS_RSQSIZE is incorrect in nicstar.h
ian@0 651 #endif /* NS_RSQSIZE */
ian@0 652
ian@0 653 #if (NS_VPIBITS == 0)
ian@0 654 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
ian@0 655 #elif (NS_VPIBITS == 1)
ian@0 656 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
ian@0 657 #elif (NS_VPIBITS == 2)
ian@0 658 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
ian@0 659 #elif (NS_VPIBITS == 8)
ian@0 660 #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
ian@0 661 #else
ian@0 662 #error NS_VPIBITS is incorrect in nicstar.h
ian@0 663 #endif /* NS_VPIBITS */
ian@0 664
ian@0 665 #ifdef RCQ_SUPPORT
ian@0 666 #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
ian@0 667 #else
ian@0 668 #define NS_CFG_RAWIE_OPT 0x00000000
ian@0 669 #endif /* RCQ_SUPPORT */
ian@0 670
ian@0 671 #ifdef ENABLE_TSQFIE
ian@0 672 #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
ian@0 673 #else
ian@0 674 #define NS_CFG_TSQFIE_OPT 0x00000000
ian@0 675 #endif /* ENABLE_TSQFIE */
ian@0 676
ian@0 677
ian@0 678 /* PCI stuff ******************************************************************/
ian@0 679
ian@0 680 #ifndef PCI_VENDOR_ID_IDT
ian@0 681 #define PCI_VENDOR_ID_IDT 0x111D
ian@0 682 #endif /* PCI_VENDOR_ID_IDT */
ian@0 683
ian@0 684 #ifndef PCI_DEVICE_ID_IDT_IDT77201
ian@0 685 #define PCI_DEVICE_ID_IDT_IDT77201 0x0001
ian@0 686 #endif /* PCI_DEVICE_ID_IDT_IDT77201 */
ian@0 687
ian@0 688
ian@0 689
ian@0 690 /* Device driver structures ***************************************************/
ian@0 691
ian@0 692
ian@0 693 struct ns_skb_cb {
ian@0 694 u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */
ian@0 695 };
ian@0 696
ian@0 697 #define NS_SKB_CB(skb) ((struct ns_skb_cb *)((skb)->cb))
ian@0 698
ian@0 699 typedef struct tsq_info
ian@0 700 {
ian@0 701 void *org;
ian@0 702 ns_tsi *base;
ian@0 703 ns_tsi *next;
ian@0 704 ns_tsi *last;
ian@0 705 } tsq_info;
ian@0 706
ian@0 707
ian@0 708 typedef struct scq_info
ian@0 709 {
ian@0 710 void *org;
ian@0 711 ns_scqe *base;
ian@0 712 ns_scqe *last;
ian@0 713 ns_scqe *next;
ian@0 714 volatile ns_scqe *tail; /* Not related to the nicstar register */
ian@0 715 unsigned num_entries;
ian@0 716 struct sk_buff **skb; /* Pointer to an array of pointers
ian@0 717 to the sk_buffs used for tx */
ian@0 718 u32 scd; /* SRAM address of the corresponding
ian@0 719 SCD */
ian@0 720 int tbd_count; /* Only meaningful on variable rate */
ian@0 721 wait_queue_head_t scqfull_waitq;
ian@0 722 volatile char full; /* SCQ full indicator */
ian@0 723 spinlock_t lock; /* SCQ spinlock */
ian@0 724 #ifdef NS_DEBUG_SPINLOCKS
ian@0 725 volatile long has_lock;
ian@0 726 volatile int cpu_lock;
ian@0 727 #endif /* NS_DEBUG_SPINLOCKS */
ian@0 728 } scq_info;
ian@0 729
ian@0 730
ian@0 731
ian@0 732 typedef struct rsq_info
ian@0 733 {
ian@0 734 void *org;
ian@0 735 ns_rsqe *base;
ian@0 736 ns_rsqe *next;
ian@0 737 ns_rsqe *last;
ian@0 738 } rsq_info;
ian@0 739
ian@0 740
ian@0 741 typedef struct skb_pool
ian@0 742 {
ian@0 743 volatile int count; /* number of buffers in the queue */
ian@0 744 struct sk_buff_head queue;
ian@0 745 } skb_pool;
ian@0 746
ian@0 747 /* NOTE: for small and large buffer pools, the count is not used, as the
ian@0 748 actual value used for buffer management is the one read from the
ian@0 749 card. */
ian@0 750
ian@0 751
ian@0 752 typedef struct vc_map
ian@0 753 {
ian@0 754 volatile unsigned int tx:1; /* TX vc? */
ian@0 755 volatile unsigned int rx:1; /* RX vc? */
ian@0 756 struct atm_vcc *tx_vcc, *rx_vcc;
ian@0 757 struct sk_buff *rx_iov; /* RX iovector skb */
ian@0 758 scq_info *scq; /* To keep track of the SCQ */
ian@0 759 u32 cbr_scd; /* SRAM address of the corresponding
ian@0 760 SCD. 0x00000000 for UBR/VBR/ABR */
ian@0 761 int tbd_count;
ian@0 762 } vc_map;
ian@0 763
ian@0 764
ian@0 765 struct ns_skb_data
ian@0 766 {
ian@0 767 struct atm_vcc *vcc;
ian@0 768 int iovcnt;
ian@0 769 };
ian@0 770
ian@0 771 #define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb))
ian@0 772
ian@0 773
ian@0 774 typedef struct ns_dev
ian@0 775 {
ian@0 776 int index; /* Card ID to the device driver */
ian@0 777 int sram_size; /* In k x 32bit words. 32 or 128 */
ian@0 778 void __iomem *membase; /* Card's memory base address */
ian@0 779 unsigned long max_pcr;
ian@0 780 int rct_size; /* Number of entries */
ian@0 781 int vpibits;
ian@0 782 int vcibits;
ian@0 783 struct pci_dev *pcidev;
ian@0 784 struct atm_dev *atmdev;
ian@0 785 tsq_info tsq;
ian@0 786 rsq_info rsq;
ian@0 787 scq_info *scq0, *scq1, *scq2; /* VBR SCQs */
ian@0 788 skb_pool sbpool; /* Small buffers */
ian@0 789 skb_pool lbpool; /* Large buffers */
ian@0 790 skb_pool hbpool; /* Pre-allocated huge buffers */
ian@0 791 skb_pool iovpool; /* iovector buffers */
ian@0 792 volatile int efbie; /* Empty free buf. queue int. enabled */
ian@0 793 volatile u32 tst_addr; /* SRAM address of the TST in use */
ian@0 794 volatile int tst_free_entries;
ian@0 795 vc_map vcmap[NS_MAX_RCTSIZE];
ian@0 796 vc_map *tste2vc[NS_TST_NUM_ENTRIES];
ian@0 797 vc_map *scd2vc[NS_FRSCD_NUM];
ian@0 798 buf_nr sbnr;
ian@0 799 buf_nr lbnr;
ian@0 800 buf_nr hbnr;
ian@0 801 buf_nr iovnr;
ian@0 802 int sbfqc;
ian@0 803 int lbfqc;
ian@0 804 u32 sm_handle;
ian@0 805 u32 sm_addr;
ian@0 806 u32 lg_handle;
ian@0 807 u32 lg_addr;
ian@0 808 struct sk_buff *rcbuf; /* Current raw cell buffer */
ian@0 809 u32 rawch; /* Raw cell queue head */
ian@0 810 unsigned intcnt; /* Interrupt counter */
ian@0 811 spinlock_t int_lock; /* Interrupt lock */
ian@0 812 spinlock_t res_lock; /* Card resource lock */
ian@0 813 #ifdef NS_DEBUG_SPINLOCKS
ian@0 814 volatile long has_int_lock;
ian@0 815 volatile int cpu_int;
ian@0 816 volatile long has_res_lock;
ian@0 817 volatile int cpu_res;
ian@0 818 #endif /* NS_DEBUG_SPINLOCKS */
ian@0 819 } ns_dev;
ian@0 820
ian@0 821
ian@0 822 /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
ian@0 823 CBR vc. If the entry is not allocated, it must be NULL.
ian@0 824
ian@0 825 There are two TSTs so the driver can modify them on the fly
ian@0 826 without stopping the transmission.
ian@0 827
ian@0 828 scd2vc allows us to find out unused fixed rate SCDs, because
ian@0 829 they must have a NULL pointer here. */
ian@0 830
ian@0 831
ian@0 832 #endif /* _LINUX_NICSTAR_H_ */