ia64/linux-2.6.18-xen.hg

annotate arch/mips/pci/pci-ocelot.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * BRIEF MODULE DESCRIPTION
ian@0 3 * Galileo Evaluation Boards PCI support.
ian@0 4 *
ian@0 5 * The general-purpose functions to read/write and configure the GT64120A's
ian@0 6 * PCI registers (function names start with pci0 or pci1) are either direct
ian@0 7 * copies of functions written by Galileo Technology, or are modifications
ian@0 8 * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
ian@0 9 * are Copyright - Galileo Technology.
ian@0 10 *
ian@0 11 * Other functions are derived from other MIPS PCI implementations, or were
ian@0 12 * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
ian@0 13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
ian@0 14 *
ian@0 15 * Copyright 2001 MontaVista Software Inc.
ian@0 16 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
ian@0 17 *
ian@0 18 * This program is free software; you can redistribute it and/or modify it
ian@0 19 * under the terms of the GNU General Public License as published by the
ian@0 20 * Free Software Foundation; either version 2 of the License, or (at your
ian@0 21 * option) any later version.
ian@0 22 *
ian@0 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
ian@0 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
ian@0 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
ian@0 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
ian@0 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
ian@0 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
ian@0 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ian@0 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ian@0 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
ian@0 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ian@0 33 *
ian@0 34 * You should have received a copy of the GNU General Public License along
ian@0 35 * with this program; if not, write to the Free Software Foundation, Inc.,
ian@0 36 * 675 Mass Ave, Cambridge, MA 02139, USA.
ian@0 37 */
ian@0 38 #include <linux/init.h>
ian@0 39 #include <linux/types.h>
ian@0 40 #include <linux/pci.h>
ian@0 41 #include <linux/kernel.h>
ian@0 42 #include <linux/slab.h>
ian@0 43 #include <linux/cache.h>
ian@0 44 #include <asm/pci.h>
ian@0 45 #include <asm/io.h>
ian@0 46 #include <asm/gt64120.h>
ian@0 47
ian@0 48 static inline unsigned int pci0ReadConfigReg(unsigned int offset)
ian@0 49 {
ian@0 50 unsigned int DataForRegCf8;
ian@0 51 unsigned int data;
ian@0 52
ian@0 53 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
ian@0 54 (PCI_FUNC(device->devfn) << 8) |
ian@0 55 (offset & ~0x3)) | 0x80000000;
ian@0 56 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
ian@0 57 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
ian@0 58
ian@0 59 return data;
ian@0 60 }
ian@0 61
ian@0 62 static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data)
ian@0 63 {
ian@0 64 unsigned int DataForRegCf8;
ian@0 65
ian@0 66 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
ian@0 67 (PCI_FUNC(device->devfn) << 8) |
ian@0 68 (offset & ~0x3)) | 0x80000000;
ian@0 69 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
ian@0 70 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
ian@0 71 }
ian@0 72
ian@0 73 static struct resource ocelot_mem_resource = {
ian@0 74 start = GT_PCI_MEM_BASE;
ian@0 75 end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
ian@0 76 };
ian@0 77
ian@0 78 static struct resource ocelot_io_resource = {
ian@0 79 start = GT_PCI_IO_BASE;
ian@0 80 end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
ian@0 81 };
ian@0 82
ian@0 83 static struct pci_controller ocelot_pci_controller = {
ian@0 84 .pci_ops = gt64120_pci_ops;
ian@0 85 .mem_resource = &ocelot_mem_resource;
ian@0 86 .io_resource = &ocelot_io_resource;
ian@0 87 };
ian@0 88
ian@0 89 static int __init ocelot_pcibios_init(void)
ian@0 90 {
ian@0 91 u32 tmp;
ian@0 92
ian@0 93 GT_READ(GT_PCI0_CMD_OFS, &tmp);
ian@0 94 GT_READ(GT_PCI0_BARE_OFS, &tmp);
ian@0 95
ian@0 96 /*
ian@0 97 * You have to enable bus mastering to configure any other
ian@0 98 * card on the bus.
ian@0 99 */
ian@0 100 tmp = pci0ReadConfigReg(PCI_COMMAND);
ian@0 101 tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
ian@0 102 pci0WriteConfigReg(PCI_COMMAND, tmp);
ian@0 103
ian@0 104 register_pci_controller(&ocelot_pci_controller);
ian@0 105 }
ian@0 106
ian@0 107 arch_initcall(ocelot_pcibios_init);