ia64/linux-2.6.18-xen.hg

annotate arch/mips/pci/fixup-malta.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
rev   line source
ian@0 1 #include <linux/init.h>
ian@0 2 #include <linux/pci.h>
ian@0 3
ian@0 4 /* PCI interrupt pins */
ian@0 5 #define PCIA 1
ian@0 6 #define PCIB 2
ian@0 7 #define PCIC 3
ian@0 8 #define PCID 4
ian@0 9
ian@0 10 /* This table is filled in by interrogating the PIIX4 chip */
ian@0 11 static char pci_irq[5] __initdata;
ian@0 12
ian@0 13 static char irq_tab[][5] __initdata = {
ian@0 14 /* INTA INTB INTC INTD */
ian@0 15 {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
ian@0 16 {0, 0, 0, 0, 0 }, /* 1: Unused */
ian@0 17 {0, 0, 0, 0, 0 }, /* 2: Unused */
ian@0 18 {0, 0, 0, 0, 0 }, /* 3: Unused */
ian@0 19 {0, 0, 0, 0, 0 }, /* 4: Unused */
ian@0 20 {0, 0, 0, 0, 0 }, /* 5: Unused */
ian@0 21 {0, 0, 0, 0, 0 }, /* 6: Unused */
ian@0 22 {0, 0, 0, 0, 0 }, /* 7: Unused */
ian@0 23 {0, 0, 0, 0, 0 }, /* 8: Unused */
ian@0 24 {0, 0, 0, 0, 0 }, /* 9: Unused */
ian@0 25 {0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */
ian@0 26 {0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */
ian@0 27 {0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */
ian@0 28 {0, 0, 0, 0, 0 }, /* 13: Unused */
ian@0 29 {0, 0, 0, 0, 0 }, /* 14: Unused */
ian@0 30 {0, 0, 0, 0, 0 }, /* 15: Unused */
ian@0 31 {0, 0, 0, 0, 0 }, /* 16: Unused */
ian@0 32 {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
ian@0 33 {0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
ian@0 34 {0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
ian@0 35 {0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
ian@0 36 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
ian@0 37 };
ian@0 38
ian@0 39 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
ian@0 40 {
ian@0 41 int virq;
ian@0 42 virq = irq_tab[slot][pin];
ian@0 43 return pci_irq[virq];
ian@0 44 }
ian@0 45
ian@0 46 /* Do platform specific device initialization at pci_enable_device() time */
ian@0 47 int pcibios_plat_dev_init(struct pci_dev *dev)
ian@0 48 {
ian@0 49 return 0;
ian@0 50 }
ian@0 51
ian@0 52 static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
ian@0 53 {
ian@0 54 unsigned char reg_val;
ian@0 55 static int piixirqmap[16] __initdata = { /* PIIX PIRQC[A:D] irq mappings */
ian@0 56 0, 0, 0, 3,
ian@0 57 4, 5, 6, 7,
ian@0 58 0, 9, 10, 11,
ian@0 59 12, 0, 14, 15
ian@0 60 };
ian@0 61 int i;
ian@0 62
ian@0 63 /* Interrogate PIIX4 to get PCI IRQ mapping */
ian@0 64 for (i = 0; i <= 3; i++) {
ian@0 65 pci_read_config_byte(pdev, 0x60+i, &reg_val);
ian@0 66 if (reg_val & 0x80)
ian@0 67 pci_irq[PCIA+i] = 0; /* Disabled */
ian@0 68 else
ian@0 69 pci_irq[PCIA+i] = piixirqmap[reg_val & 15];
ian@0 70 }
ian@0 71
ian@0 72 /* Done by YAMON 2.00 onwards */
ian@0 73 if (PCI_SLOT(pdev->devfn) == 10) {
ian@0 74 /*
ian@0 75 * Set top of main memory accessible by ISA or DMA
ian@0 76 * devices to 16 Mb.
ian@0 77 */
ian@0 78 pci_read_config_byte(pdev, 0x69, &reg_val);
ian@0 79 pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
ian@0 80 }
ian@0 81 }
ian@0 82
ian@0 83 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
ian@0 84 malta_piix_func0_fixup);
ian@0 85
ian@0 86 static void __init malta_piix_func1_fixup(struct pci_dev *pdev)
ian@0 87 {
ian@0 88 unsigned char reg_val;
ian@0 89
ian@0 90 /* Done by YAMON 2.02 onwards */
ian@0 91 if (PCI_SLOT(pdev->devfn) == 10) {
ian@0 92 /*
ian@0 93 * IDE Decode enable.
ian@0 94 */
ian@0 95 pci_read_config_byte(pdev, 0x41, &reg_val);
ian@0 96 pci_write_config_byte(pdev, 0x41, reg_val|0x80);
ian@0 97 pci_read_config_byte(pdev, 0x43, &reg_val);
ian@0 98 pci_write_config_byte(pdev, 0x43, reg_val|0x80);
ian@0 99 }
ian@0 100 }
ian@0 101
ian@0 102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
ian@0 103 malta_piix_func1_fixup);