ia64/linux-2.6.18-xen.hg

annotate arch/alpha/kernel/sys_rawhide.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * linux/arch/alpha/kernel/sys_rawhide.c
ian@0 3 *
ian@0 4 * Copyright (C) 1995 David A Rusling
ian@0 5 * Copyright (C) 1996 Jay A Estabrook
ian@0 6 * Copyright (C) 1998, 1999 Richard Henderson
ian@0 7 *
ian@0 8 * Code supporting the RAWHIDE.
ian@0 9 */
ian@0 10
ian@0 11 #include <linux/kernel.h>
ian@0 12 #include <linux/types.h>
ian@0 13 #include <linux/mm.h>
ian@0 14 #include <linux/sched.h>
ian@0 15 #include <linux/pci.h>
ian@0 16 #include <linux/init.h>
ian@0 17
ian@0 18 #include <asm/ptrace.h>
ian@0 19 #include <asm/system.h>
ian@0 20 #include <asm/dma.h>
ian@0 21 #include <asm/irq.h>
ian@0 22 #include <asm/mmu_context.h>
ian@0 23 #include <asm/io.h>
ian@0 24 #include <asm/pgtable.h>
ian@0 25 #include <asm/core_mcpcia.h>
ian@0 26 #include <asm/tlbflush.h>
ian@0 27
ian@0 28 #include "proto.h"
ian@0 29 #include "irq_impl.h"
ian@0 30 #include "pci_impl.h"
ian@0 31 #include "machvec_impl.h"
ian@0 32
ian@0 33
ian@0 34 /*
ian@0 35 * HACK ALERT! only the boot cpu is used for interrupts.
ian@0 36 */
ian@0 37
ian@0 38
ian@0 39 /* Note mask bit is true for ENABLED irqs. */
ian@0 40
ian@0 41 static unsigned int hose_irq_masks[4] = {
ian@0 42 0xff0000, 0xfe0000, 0xff0000, 0xff0000
ian@0 43 };
ian@0 44 static unsigned int cached_irq_masks[4];
ian@0 45 DEFINE_SPINLOCK(rawhide_irq_lock);
ian@0 46
ian@0 47 static inline void
ian@0 48 rawhide_update_irq_hw(int hose, int mask)
ian@0 49 {
ian@0 50 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask;
ian@0 51 mb();
ian@0 52 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose));
ian@0 53 }
ian@0 54
ian@0 55 static inline void
ian@0 56 rawhide_enable_irq(unsigned int irq)
ian@0 57 {
ian@0 58 unsigned int mask, hose;
ian@0 59
ian@0 60 irq -= 16;
ian@0 61 hose = irq / 24;
ian@0 62 irq -= hose * 24;
ian@0 63 mask = 1 << irq;
ian@0 64
ian@0 65 spin_lock(&rawhide_irq_lock);
ian@0 66 mask |= cached_irq_masks[hose];
ian@0 67 cached_irq_masks[hose] = mask;
ian@0 68 rawhide_update_irq_hw(hose, mask);
ian@0 69 spin_unlock(&rawhide_irq_lock);
ian@0 70 }
ian@0 71
ian@0 72 static void
ian@0 73 rawhide_disable_irq(unsigned int irq)
ian@0 74 {
ian@0 75 unsigned int mask, hose;
ian@0 76
ian@0 77 irq -= 16;
ian@0 78 hose = irq / 24;
ian@0 79 irq -= hose * 24;
ian@0 80 mask = ~(1 << irq) | hose_irq_masks[hose];
ian@0 81
ian@0 82 spin_lock(&rawhide_irq_lock);
ian@0 83 mask &= cached_irq_masks[hose];
ian@0 84 cached_irq_masks[hose] = mask;
ian@0 85 rawhide_update_irq_hw(hose, mask);
ian@0 86 spin_unlock(&rawhide_irq_lock);
ian@0 87 }
ian@0 88
ian@0 89 static void
ian@0 90 rawhide_mask_and_ack_irq(unsigned int irq)
ian@0 91 {
ian@0 92 unsigned int mask, mask1, hose;
ian@0 93
ian@0 94 irq -= 16;
ian@0 95 hose = irq / 24;
ian@0 96 irq -= hose * 24;
ian@0 97 mask1 = 1 << irq;
ian@0 98 mask = ~mask1 | hose_irq_masks[hose];
ian@0 99
ian@0 100 spin_lock(&rawhide_irq_lock);
ian@0 101
ian@0 102 mask &= cached_irq_masks[hose];
ian@0 103 cached_irq_masks[hose] = mask;
ian@0 104 rawhide_update_irq_hw(hose, mask);
ian@0 105
ian@0 106 /* Clear the interrupt. */
ian@0 107 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1;
ian@0 108
ian@0 109 spin_unlock(&rawhide_irq_lock);
ian@0 110 }
ian@0 111
ian@0 112 static unsigned int
ian@0 113 rawhide_startup_irq(unsigned int irq)
ian@0 114 {
ian@0 115 rawhide_enable_irq(irq);
ian@0 116 return 0;
ian@0 117 }
ian@0 118
ian@0 119 static void
ian@0 120 rawhide_end_irq(unsigned int irq)
ian@0 121 {
ian@0 122 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
ian@0 123 rawhide_enable_irq(irq);
ian@0 124 }
ian@0 125
ian@0 126 static struct hw_interrupt_type rawhide_irq_type = {
ian@0 127 .typename = "RAWHIDE",
ian@0 128 .startup = rawhide_startup_irq,
ian@0 129 .shutdown = rawhide_disable_irq,
ian@0 130 .enable = rawhide_enable_irq,
ian@0 131 .disable = rawhide_disable_irq,
ian@0 132 .ack = rawhide_mask_and_ack_irq,
ian@0 133 .end = rawhide_end_irq,
ian@0 134 };
ian@0 135
ian@0 136 static void
ian@0 137 rawhide_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
ian@0 138 {
ian@0 139 int irq;
ian@0 140
ian@0 141 irq = (vector - 0x800) >> 4;
ian@0 142
ian@0 143 /*
ian@0 144 * The RAWHIDE SRM console reports PCI interrupts with a vector
ian@0 145 * 0x80 *higher* than one might expect, as PCI IRQ 0 (ie bit 0)
ian@0 146 * shows up as IRQ 24, etc, etc. We adjust it down by 8 to have
ian@0 147 * it line up with the actual bit numbers from the REQ registers,
ian@0 148 * which is how we manage the interrupts/mask. Sigh...
ian@0 149 *
ian@0 150 * Also, PCI #1 interrupts are offset some more... :-(
ian@0 151 */
ian@0 152
ian@0 153 if (irq == 52) {
ian@0 154 /* SCSI on PCI1 is special. */
ian@0 155 irq = 72;
ian@0 156 }
ian@0 157
ian@0 158 /* Adjust by which hose it is from. */
ian@0 159 irq -= ((irq + 16) >> 2) & 0x38;
ian@0 160
ian@0 161 handle_irq(irq, regs);
ian@0 162 }
ian@0 163
ian@0 164 static void __init
ian@0 165 rawhide_init_irq(void)
ian@0 166 {
ian@0 167 struct pci_controller *hose;
ian@0 168 long i;
ian@0 169
ian@0 170 mcpcia_init_hoses();
ian@0 171
ian@0 172 for (hose = hose_head; hose; hose = hose->next) {
ian@0 173 unsigned int h = hose->index;
ian@0 174 unsigned int mask = hose_irq_masks[h];
ian@0 175
ian@0 176 cached_irq_masks[h] = mask;
ian@0 177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask;
ian@0 178 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0;
ian@0 179 }
ian@0 180
ian@0 181 for (i = 16; i < 128; ++i) {
ian@0 182 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
ian@0 183 irq_desc[i].chip = &rawhide_irq_type;
ian@0 184 }
ian@0 185
ian@0 186 init_i8259a_irqs();
ian@0 187 common_init_isa_dma();
ian@0 188 }
ian@0 189
ian@0 190 /*
ian@0 191 * PCI Fixup configuration.
ian@0 192 *
ian@0 193 * Summary @ MCPCIA_PCI0_INT_REQ:
ian@0 194 * Bit Meaning
ian@0 195 * 0 Interrupt Line A from slot 2 PCI0
ian@0 196 * 1 Interrupt Line B from slot 2 PCI0
ian@0 197 * 2 Interrupt Line C from slot 2 PCI0
ian@0 198 * 3 Interrupt Line D from slot 2 PCI0
ian@0 199 * 4 Interrupt Line A from slot 3 PCI0
ian@0 200 * 5 Interrupt Line B from slot 3 PCI0
ian@0 201 * 6 Interrupt Line C from slot 3 PCI0
ian@0 202 * 7 Interrupt Line D from slot 3 PCI0
ian@0 203 * 8 Interrupt Line A from slot 4 PCI0
ian@0 204 * 9 Interrupt Line B from slot 4 PCI0
ian@0 205 * 10 Interrupt Line C from slot 4 PCI0
ian@0 206 * 11 Interrupt Line D from slot 4 PCI0
ian@0 207 * 12 Interrupt Line A from slot 5 PCI0
ian@0 208 * 13 Interrupt Line B from slot 5 PCI0
ian@0 209 * 14 Interrupt Line C from slot 5 PCI0
ian@0 210 * 15 Interrupt Line D from slot 5 PCI0
ian@0 211 * 16 EISA interrupt (PCI 0) or SCSI interrupt (PCI 1)
ian@0 212 * 17-23 NA
ian@0 213 *
ian@0 214 * IdSel
ian@0 215 * 1 EISA bridge (PCI bus 0 only)
ian@0 216 * 2 PCI option slot 2
ian@0 217 * 3 PCI option slot 3
ian@0 218 * 4 PCI option slot 4
ian@0 219 * 5 PCI option slot 5
ian@0 220 *
ian@0 221 */
ian@0 222
ian@0 223 static int __init
ian@0 224 rawhide_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
ian@0 225 {
ian@0 226 static char irq_tab[5][5] __initdata = {
ian@0 227 /*INT INTA INTB INTC INTD */
ian@0 228 { 16+16, 16+16, 16+16, 16+16, 16+16}, /* IdSel 1 SCSI PCI 1 */
ian@0 229 { 16+ 0, 16+ 0, 16+ 1, 16+ 2, 16+ 3}, /* IdSel 2 slot 2 */
ian@0 230 { 16+ 4, 16+ 4, 16+ 5, 16+ 6, 16+ 7}, /* IdSel 3 slot 3 */
ian@0 231 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 4 slot 4 */
ian@0 232 { 16+12, 16+12, 16+13, 16+14, 16+15} /* IdSel 5 slot 5 */
ian@0 233 };
ian@0 234 const long min_idsel = 1, max_idsel = 5, irqs_per_slot = 5;
ian@0 235
ian@0 236 struct pci_controller *hose = dev->sysdata;
ian@0 237 int irq = COMMON_TABLE_LOOKUP;
ian@0 238 if (irq >= 0)
ian@0 239 irq += 24 * hose->index;
ian@0 240 return irq;
ian@0 241 }
ian@0 242
ian@0 243
ian@0 244 /*
ian@0 245 * The System Vector
ian@0 246 */
ian@0 247
ian@0 248 struct alpha_machine_vector rawhide_mv __initmv = {
ian@0 249 .vector_name = "Rawhide",
ian@0 250 DO_EV5_MMU,
ian@0 251 DO_DEFAULT_RTC,
ian@0 252 DO_MCPCIA_IO,
ian@0 253 .machine_check = mcpcia_machine_check,
ian@0 254 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
ian@0 255 .min_io_address = DEFAULT_IO_BASE,
ian@0 256 .min_mem_address = MCPCIA_DEFAULT_MEM_BASE,
ian@0 257 .pci_dac_offset = MCPCIA_DAC_OFFSET,
ian@0 258
ian@0 259 .nr_irqs = 128,
ian@0 260 .device_interrupt = rawhide_srm_device_interrupt,
ian@0 261
ian@0 262 .init_arch = mcpcia_init_arch,
ian@0 263 .init_irq = rawhide_init_irq,
ian@0 264 .init_rtc = common_init_rtc,
ian@0 265 .init_pci = common_init_pci,
ian@0 266 .kill_arch = NULL,
ian@0 267 .pci_map_irq = rawhide_map_irq,
ian@0 268 .pci_swizzle = common_swizzle,
ian@0 269 };
ian@0 270 ALIAS_MV(rawhide)