ia64/linux-2.6.18-xen.hg

annotate arch/alpha/kernel/irq_pyxis.c @ 897:329ea0ccb344

balloon: try harder to balloon up under memory pressure.

Currently if the balloon driver is unable to increase the guest's
reservation it assumes the failure was due to reaching its full
allocation, gives up on the ballooning operation and records the limit
it reached as the "hard limit". The driver will not try again until
the target is set again (even to the same value).

However it is possible that ballooning has in fact failed due to
memory pressure in the host and therefore it is desirable to keep
attempting to reach the target in case memory becomes available. The
most likely scenario is that some guests are ballooning down while
others are ballooning up and therefore there is temporary memory
pressure while things stabilise. You would not expect a well behaved
toolstack to ask a domain to balloon to more than its allocation nor
would you expect it to deliberately over-commit memory by setting
balloon targets which exceed the total host memory.

This patch drops the concept of a hard limit and causes the balloon
driver to retry increasing the reservation on a timer in the same
manner as when decreasing the reservation.

Also if we partially succeed in increasing the reservation
(i.e. receive less pages than we asked for) then we may as well keep
those pages rather than returning them to Xen.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 05 14:01:20 2009 +0100 (2009-06-05)
parents 831230e53067
children
rev   line source
ian@0 1 /*
ian@0 2 * linux/arch/alpha/kernel/irq_pyxis.c
ian@0 3 *
ian@0 4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
ian@0 5 *
ian@0 6 * IRQ Code common to all PYXIS core logic chips.
ian@0 7 */
ian@0 8
ian@0 9 #include <linux/init.h>
ian@0 10 #include <linux/sched.h>
ian@0 11 #include <linux/irq.h>
ian@0 12
ian@0 13 #include <asm/io.h>
ian@0 14 #include <asm/core_cia.h>
ian@0 15
ian@0 16 #include "proto.h"
ian@0 17 #include "irq_impl.h"
ian@0 18
ian@0 19
ian@0 20 /* Note mask bit is true for ENABLED irqs. */
ian@0 21 static unsigned long cached_irq_mask;
ian@0 22
ian@0 23 static inline void
ian@0 24 pyxis_update_irq_hw(unsigned long mask)
ian@0 25 {
ian@0 26 *(vulp)PYXIS_INT_MASK = mask;
ian@0 27 mb();
ian@0 28 *(vulp)PYXIS_INT_MASK;
ian@0 29 }
ian@0 30
ian@0 31 static inline void
ian@0 32 pyxis_enable_irq(unsigned int irq)
ian@0 33 {
ian@0 34 pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
ian@0 35 }
ian@0 36
ian@0 37 static void
ian@0 38 pyxis_disable_irq(unsigned int irq)
ian@0 39 {
ian@0 40 pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
ian@0 41 }
ian@0 42
ian@0 43 static unsigned int
ian@0 44 pyxis_startup_irq(unsigned int irq)
ian@0 45 {
ian@0 46 pyxis_enable_irq(irq);
ian@0 47 return 0;
ian@0 48 }
ian@0 49
ian@0 50 static void
ian@0 51 pyxis_end_irq(unsigned int irq)
ian@0 52 {
ian@0 53 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
ian@0 54 pyxis_enable_irq(irq);
ian@0 55 }
ian@0 56
ian@0 57 static void
ian@0 58 pyxis_mask_and_ack_irq(unsigned int irq)
ian@0 59 {
ian@0 60 unsigned long bit = 1UL << (irq - 16);
ian@0 61 unsigned long mask = cached_irq_mask &= ~bit;
ian@0 62
ian@0 63 /* Disable the interrupt. */
ian@0 64 *(vulp)PYXIS_INT_MASK = mask;
ian@0 65 wmb();
ian@0 66 /* Ack PYXIS PCI interrupt. */
ian@0 67 *(vulp)PYXIS_INT_REQ = bit;
ian@0 68 mb();
ian@0 69 /* Re-read to force both writes. */
ian@0 70 *(vulp)PYXIS_INT_MASK;
ian@0 71 }
ian@0 72
ian@0 73 static struct hw_interrupt_type pyxis_irq_type = {
ian@0 74 .typename = "PYXIS",
ian@0 75 .startup = pyxis_startup_irq,
ian@0 76 .shutdown = pyxis_disable_irq,
ian@0 77 .enable = pyxis_enable_irq,
ian@0 78 .disable = pyxis_disable_irq,
ian@0 79 .ack = pyxis_mask_and_ack_irq,
ian@0 80 .end = pyxis_end_irq,
ian@0 81 };
ian@0 82
ian@0 83 void
ian@0 84 pyxis_device_interrupt(unsigned long vector, struct pt_regs *regs)
ian@0 85 {
ian@0 86 unsigned long pld;
ian@0 87 unsigned int i;
ian@0 88
ian@0 89 /* Read the interrupt summary register of PYXIS */
ian@0 90 pld = *(vulp)PYXIS_INT_REQ;
ian@0 91 pld &= cached_irq_mask;
ian@0 92
ian@0 93 /*
ian@0 94 * Now for every possible bit set, work through them and call
ian@0 95 * the appropriate interrupt handler.
ian@0 96 */
ian@0 97 while (pld) {
ian@0 98 i = ffz(~pld);
ian@0 99 pld &= pld - 1; /* clear least bit set */
ian@0 100 if (i == 7)
ian@0 101 isa_device_interrupt(vector, regs);
ian@0 102 else
ian@0 103 handle_irq(16+i, regs);
ian@0 104 }
ian@0 105 }
ian@0 106
ian@0 107 void __init
ian@0 108 init_pyxis_irqs(unsigned long ignore_mask)
ian@0 109 {
ian@0 110 long i;
ian@0 111
ian@0 112 *(vulp)PYXIS_INT_MASK = 0; /* disable all */
ian@0 113 *(vulp)PYXIS_INT_REQ = -1; /* flush all */
ian@0 114 mb();
ian@0 115
ian@0 116 /* Send -INTA pulses to clear any pending interrupts ...*/
ian@0 117 *(vuip) CIA_IACK_SC;
ian@0 118
ian@0 119 for (i = 16; i < 48; ++i) {
ian@0 120 if ((ignore_mask >> i) & 1)
ian@0 121 continue;
ian@0 122 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
ian@0 123 irq_desc[i].chip = &pyxis_irq_type;
ian@0 124 }
ian@0 125
ian@0 126 setup_irq(16+7, &isa_cascade_irqaction);
ian@0 127 }