direct-io.hg

changeset 11524:fd79d6295111

[POWERPC][XEN] Add newlines on multiline output and dump SLB on SLB errors

Signed-off-by: Jimi Xenidis <jimix@watson.ibm.com>
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
author Jimi Xenidis <jimix@watson.ibm.com>
date Fri Sep 15 18:20:55 2006 -0400 (2006-09-15)
parents 6486bc1937a4
children a3762039dc23
files xen/arch/powerpc/powerpc64/ppc970_machinecheck.c
line diff
     1.1 --- a/xen/arch/powerpc/powerpc64/ppc970_machinecheck.c	Fri Sep 15 18:19:46 2006 -0400
     1.2 +++ b/xen/arch/powerpc/powerpc64/ppc970_machinecheck.c	Fri Sep 15 18:20:55 2006 -0400
     1.3 @@ -56,61 +56,65 @@ int cpu_machinecheck(struct cpu_user_reg
     1.4  
     1.5      printk("SRR1: 0x%016lx\n", regs->msr);
     1.6      if (regs->msr & MCK_SRR1_INSN_FETCH_UNIT)
     1.7 -        printk("42: Exception caused by Instruction Fetch Unit (IFU) "
     1.8 -               "detection of a hardware uncorrectable error (UE).\n");
     1.9 +        printk("42: Exception caused by Instruction Fetch Unit (IFU)\n"
    1.10 +               "    detection of a hardware uncorrectable error (UE).\n");
    1.11  
    1.12      if (regs->msr & MCK_SRR1_LOAD_STORE)
    1.13 -        printk("43: Exception caused by load/store detection of error "
    1.14 -               "(see DSISR)\n");
    1.15 +        printk("43: Exception caused by load/store detection of error\n"
    1.16 +               "    (see DSISR)\n");
    1.17  
    1.18      switch (regs->msr & MCK_SRR1_CAUSE_MASK) {
    1.19 +    case 0:
    1.20 +        printk("0b00: Likely caused by an asynchronous machine check,\n"
    1.21 +               "see SCOM Asynchronous Machine Check Register\n");
    1.22 +        break;
    1.23      case MCK_SRR1_CAUSE_SLB_PAR:
    1.24 -        printk("0b01: Exception caused by an SLB parity error detected "
    1.25 -               "while translating an instruction fetch address.\n");
    1.26 +        printk("0b01: Exception caused by an SLB parity error detected\n"
    1.27 +               "      while translating an instruction fetch address.\n");
    1.28          break;
    1.29      case MCK_SRR1_CAUSE_TLB_PAR:
    1.30 -        printk("0b10: Exception caused by a TLB parity error detected "
    1.31 -               "while translating an instruction fetch address.\n");
    1.32 +        printk("0b10: Exception caused by a TLB parity error detected\n"
    1.33 +               "      while translating an instruction fetch address.\n");
    1.34          break;
    1.35      case MCK_SRR1_CAUSE_UE:
    1.36 -        printk("0b11: Exception caused by a hardware uncorrectable "
    1.37 -               "error (UE) detected while doing a reload of an "
    1.38 -               "instruction-fetch TLB tablewalk.\n");
    1.39 -        break;
    1.40 -    default:
    1.41 +        printk("0b11: Exception caused by a hardware uncorrectable\n"
    1.42 +               "      error (UE) detected while doing a reload of an\n"
    1.43 +               "      instruction-fetch TLB tablewalk.\n");
    1.44          break;
    1.45      }
    1.46  
    1.47 -    printk("\nDSIDR: 0x%08x\n", dsisr);
    1.48 +    printk("\nDSISR: 0x%08x\n", dsisr);
    1.49      if (dsisr & MCK_DSISR_UE)
    1.50 -        printk("16: Exception caused by a UE deferred error "
    1.51 -               "(DAR is undefined).\n");
    1.52 +        printk("16: Exception caused by a UE deferred error\n"
    1.53 +               "    (DAR is undefined).\n");
    1.54      
    1.55      if (dsisr & MCK_DSISR_UE_TABLE_WALK)
    1.56 -        printk("17: Exception caused by a UE deferred error "
    1.57 -               "during a tablewalk (D-side).\n"); 
    1.58 +        printk("17: Exception caused by a UE deferred error\n"
    1.59 +               "    during a tablewalk (D-side).\n"); 
    1.60  
    1.61      if (dsisr & MCK_DSISR_L1_DCACHE_PAR)
    1.62 -        printk("18: Exception was caused by a software recoverable "
    1.63 -               "parity error in the L1 D-cache.\n");
    1.64 +        printk("18: Exception was caused by a software recoverable\n"
    1.65 +               "    parity error in the L1 D-cache.\n");
    1.66  
    1.67      if (dsisr & MCK_DSISR_L1_DCACHE_TAG_PAR)
    1.68 -        printk("19: Exception was caused by a software recoverable "
    1.69 -               "parity error in the L1 D-cache tag.\n");
    1.70 +        printk("19: Exception was caused by a software recoverable\n"
    1.71 +               "    parity error in the L1 D-cache tag.\n");
    1.72  
    1.73      if (dsisr & MCK_DSISR_D_ERAT_PAR)
    1.74 -        printk("20: Exception was caused by a software recoverable parity "
    1.75 -               "error in the D-ERAT.\n");
    1.76 +        printk("20: Exception was caused by a software recoverable parity\n"
    1.77 +               "    error in the D-ERAT.\n");
    1.78          
    1.79      if (dsisr & MCK_DSISR_TLB_PAR)
    1.80 -        printk("21: Exception was caused by a software recoverable parity "
    1.81 -               "error in the TLB.\n");
    1.82 +        printk("21: Exception was caused by a software recoverable parity\n"
    1.83 +               "    error in the TLB.\n");
    1.84  
    1.85 -    if (dsisr & MCK_DSISR_SLB_PAR)
    1.86 -        printk("23: Exception was caused by an SLB parity error (may not be "
    1.87 -               "recoverable). This condition could occur if the "
    1.88 -               "effective segment ID (ESID) fields of two or more SLB "
    1.89 -               "entries contain the same value.");
    1.90 +    if (dsisr & MCK_DSISR_SLB_PAR) {
    1.91 +        printk("23: Exception was caused by an SLB parity error (may not be\n"
    1.92 +               "    recoverable). This condition could occur if the\n"
    1.93 +               "    effective segment ID (ESID) fields of two or more SLB\n"
    1.94 +               "    entries contain the same value.\n");
    1.95 +        dump_segments(0);
    1.96 +    }
    1.97  
    1.98      return 0; /* for now lets not recover; */
    1.99  }