direct-io.hg

changeset 11303:fa584e5d17b6

[IA64] initial cleanup of ivt.S

This patch reflects a patch I recently posted to the linux-ia64
mailing list to do essentially the same thing for ivt.S in upstream
source.

I've reformatted the contents of the Xen version of ivt.S so that
they are now readable on 80-column displays, in accordance with
Linux coding standards. This is really just a first pass at
cleaning up this code.

In all of this patch, I only changed one line of assembly; there
was a 'mov r31=pr;' in entry 23 (daccess_rights) that I changed
to 'mov r31=pr;;' which is most likely what was meant. No other
instructions were changed. Hopefully, I didn't harm any other
white space formatting.

Signed-off-by: Al Stone <ahs3@fc.hp.com>
author awilliam@xenbuild.aw
date Mon Aug 14 13:30:17 2006 -0600 (2006-08-14)
parents 7c79d49033c6
children 741fd616f5dc
files xen/arch/ia64/xen/ivt.S
line diff
     1.1 --- a/xen/arch/ia64/xen/ivt.S	Mon Aug 14 13:20:40 2006 -0600
     1.2 +++ b/xen/arch/ia64/xen/ivt.S	Mon Aug 14 13:30:17 2006 -0600
     1.3 @@ -15,7 +15,8 @@
     1.4   *      Fenghua Yu <fenghua.yu@intel.com>
     1.5   *
     1.6   * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
     1.7 - * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
     1.8 + * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now
     1.9 + * uses virtual PT.
    1.10   */
    1.11  /*
    1.12   * This file defines the interruption vector table used by the CPU.
    1.13 @@ -69,10 +70,14 @@
    1.14  
    1.15  #if 0
    1.16    /*
    1.17 -   * This lets you track the last eight faults that occurred on the CPU.  Make sure ar.k2 isn't
    1.18 -   * needed for something else before enabling this...
    1.19 +   * This lets you track the last eight faults that occurred on the CPU.
    1.20 +   * Make sure ar.k2 isn't needed for something else before enabling this...
    1.21     */
    1.22 -# define DBG_FAULT(i)	mov r16=ar.k2;;	shl r16=r16,8;;	add r16=(i),r16;;mov ar.k2=r16
    1.23 +# define DBG_FAULT(i)		\
    1.24 +	mov r16=ar.k2;;		\
    1.25 +	shl r16=r16,8;;		\
    1.26 +	add r16=(i),r16;;	\
    1.27 +	mov ar.k2=r16
    1.28  #else
    1.29  # define DBG_FAULT(i)
    1.30  #endif
    1.31 @@ -80,18 +85,18 @@
    1.32  #define MINSTATE_VIRT	/* needed by minstate.h */
    1.33  #include "minstate.h"
    1.34  
    1.35 -#define FAULT(n)									\
    1.36 -	mov r19=n;			/* prepare to save predicates */		\
    1.37 -	mov r31=pr;									\
    1.38 +#define FAULT(n)							\
    1.39 +	mov r19=n;		/* prepare to save predicates */	\
    1.40 +	mov r31=pr;							\
    1.41  	br.sptk.many dispatch_to_fault_handler
    1.42  
    1.43 -#define FAULT_OR_REFLECT(n)								\
    1.44 -	mov r20=cr.ipsr;								\
    1.45 -	mov r19=n;	/* prepare to save predicates */				\
    1.46 -	mov r31=pr;;	 	 							\
    1.47 -	extr.u r20=r20,IA64_PSR_CPL0_BIT,2;;   						\
    1.48 -	cmp.ne p6,p0=r0,r20; 	/* cpl != 0?*/						\
    1.49 -(p6)	br.dptk.many dispatch_reflection;						\
    1.50 +#define FAULT_OR_REFLECT(n)						\
    1.51 +	mov r20=cr.ipsr;						\
    1.52 +	mov r19=n;		/* prepare to save predicates */	\
    1.53 +	mov r31=pr;;	 	 					\
    1.54 +	extr.u r20=r20,IA64_PSR_CPL0_BIT,2;;   				\
    1.55 +	cmp.ne p6,p0=r0,r20; 	/* cpl != 0?*/				\
    1.56 +(p6)	br.dptk.many dispatch_reflection;				\
    1.57  	br.sptk.few dispatch_to_fault_handler
    1.58  
    1.59  	.section .text.ivt,"ax"
    1.60 @@ -99,7 +104,7 @@
    1.61  	.align 32768	// align on 32KB boundary
    1.62  	.global ia64_ivt
    1.63  ia64_ivt:
    1.64 -/////////////////////////////////////////////////////////////////////////////////////////
    1.65 +//////////////////////////////////////////////////////////////////////////
    1.66  // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
    1.67  ENTRY(vhpt_miss)
    1.68  	DBG_FAULT(0)
    1.69 @@ -107,33 +112,34 @@ ENTRY(vhpt_miss)
    1.70  	FAULT(0)
    1.71  #else
    1.72  	/*
    1.73 -	 * The VHPT vector is invoked when the TLB entry for the virtual page table
    1.74 -	 * is missing.  This happens only as a result of a previous
    1.75 -	 * (the "original") TLB miss, which may either be caused by an instruction
    1.76 -	 * fetch or a data access (or non-access).
    1.77 +	 * The VHPT vector is invoked when the TLB entry for the virtual
    1.78 +	 * page table is missing.  This happens only as a result of a 
    1.79 +	 * previous (the "original") TLB miss, which may either be caused
    1.80 +	 * by an instruction fetch or a data access (or non-access).
    1.81  	 *
    1.82 -	 * What we do here is normal TLB miss handing for the _original_ miss, followed
    1.83 -	 * by inserting the TLB entry for the virtual page table page that the VHPT
    1.84 -	 * walker was attempting to access.  The latter gets inserted as long
    1.85 -	 * as both L1 and L2 have valid mappings for the faulting address.
    1.86 -	 * The TLB entry for the original miss gets inserted only if
    1.87 -	 * the L3 entry indicates that the page is present.
    1.88 +	 * What we do here is normal TLB miss handing for the _original_ 
    1.89 +	 * miss, followed by inserting the TLB entry for the virtual page
    1.90 +	 * table page that the VHPT walker was attempting to access.  The
    1.91 +	 * latter gets inserted as long as both L1 and L2 have valid 
    1.92 +	 * mappings for the faulting address.  The TLB entry for the 
    1.93 +	 * original miss gets inserted only if the L3 entry indicates
    1.94 +	 * that the page is present.
    1.95  	 *
    1.96  	 * do_page_fault gets invoked in the following cases:
    1.97  	 *	- the faulting virtual address uses unimplemented address bits
    1.98  	 *	- the faulting virtual address has no L1, L2, or L3 mapping
    1.99  	 */
   1.100 -	mov r16=cr.ifa				// get address that caused the TLB miss
   1.101 +	mov r16=cr.ifa			// get address that caused the TLB miss
   1.102  #ifdef CONFIG_HUGETLB_PAGE
   1.103  	movl r18=PAGE_SHIFT
   1.104  	mov r25=cr.itir
   1.105  #endif
   1.106  	;;
   1.107 -	rsm psr.dt				// use physical addressing for data
   1.108 -	mov r31=pr				// save the predicate registers
   1.109 -	mov r19=IA64_KR(PT_BASE)		// get page table base address
   1.110 -	shl r21=r16,3				// shift bit 60 into sign bit
   1.111 -	shr.u r17=r16,61			// get the region number into r17
   1.112 +	rsm psr.dt			// use physical addressing for data
   1.113 +	mov r31=pr			// save the predicate registers
   1.114 +	mov r19=IA64_KR(PT_BASE)	// get page table base address
   1.115 +	shl r21=r16,3			// shift bit 60 into sign bit
   1.116 +	shr.u r17=r16,61		// get the region number into r17
   1.117  	;;
   1.118  	shr r22=r21,3
   1.119  #ifdef CONFIG_HUGETLB_PAGE
   1.120 @@ -146,56 +152,68 @@ ENTRY(vhpt_miss)
   1.121  (p8)	shr r22=r22,r27
   1.122  #endif
   1.123  	;;
   1.124 -	cmp.eq p6,p7=5,r17			// is IFA pointing into to region 5?
   1.125 -	shr.u r18=r22,PGDIR_SHIFT		// get bits 33-63 of the faulting address
   1.126 +	cmp.eq p6,p7=5,r17		// is IFA pointing into to region 5?
   1.127 +	shr.u r18=r22,PGDIR_SHIFT	// get bits 33-63 of faulting address
   1.128  	;;
   1.129 -(p7)	dep r17=r17,r19,(PAGE_SHIFT-3),3	// put region number bits in place
   1.130 +(p7)	dep r17=r17,r19,(PAGE_SHIFT-3),3  // put region number bits in place
   1.131  
   1.132  	srlz.d
   1.133 -	LOAD_PHYSICAL(p6, r19, swapper_pg_dir)	// region 5 is rooted at swapper_pg_dir
   1.134 +	LOAD_PHYSICAL(p6, r19, swapper_pg_dir)	// region 5 is rooted at 
   1.135 +						//   swapper_pg_dir
   1.136  
   1.137  	.pred.rel "mutex", p6, p7
   1.138  (p6)	shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
   1.139  (p7)	shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
   1.140  	;;
   1.141  (p6)	dep r17=r18,r19,3,(PAGE_SHIFT-3)	// r17=PTA + IFA(33,42)*8
   1.142 -(p7)	dep r17=r18,r17,3,(PAGE_SHIFT-6)	// r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
   1.143 -	cmp.eq p7,p6=0,r21			// unused address bits all zeroes?
   1.144 +(p7)	dep r17=r18,r17,3,(PAGE_SHIFT-6)	// r17=PTA + 
   1.145 +						//     (((IFA(61,63) << 7) |
   1.146 +						//      IFA(33,39))*8)
   1.147 +	cmp.eq p7,p6=0,r21			// unused address bits all zero?
   1.148  	shr.u r18=r22,PMD_SHIFT			// shift L2 index into position
   1.149  	;;
   1.150  	ld8 r17=[r17]				// fetch the L1 entry (may be 0)
   1.151  	;;
   1.152  (p7)	cmp.eq p6,p7=r17,r0			// was L1 entry NULL?
   1.153 -	dep r17=r18,r17,3,(PAGE_SHIFT-3)	// compute address of L2 page table entry
   1.154 +	dep r17=r18,r17,3,(PAGE_SHIFT-3)	// compute address of L2 page
   1.155 +						//   table entry
   1.156  	;;
   1.157  (p7)	ld8 r20=[r17]				// fetch the L2 entry (may be 0)
   1.158  	shr.u r19=r22,PAGE_SHIFT		// shift L3 index into position
   1.159  	;;
   1.160  (p7)	cmp.eq.or.andcm p6,p7=r20,r0		// was L2 entry NULL?
   1.161 -	dep r21=r19,r20,3,(PAGE_SHIFT-3)	// compute address of L3 page table entry
   1.162 +	dep r21=r19,r20,3,(PAGE_SHIFT-3)	// compute address of L3 page
   1.163 +						//   table entry
   1.164  	;;
   1.165  (p7)	ld8 r18=[r21]				// read the L3 PTE
   1.166 -	mov r19=cr.isr				// cr.isr bit 0 tells us if this is an insn miss
   1.167 +	mov r19=cr.isr				// cr.isr bit 0 tells us if
   1.168 +						//   this is an insn miss
   1.169  	;;
   1.170  (p7)	tbit.z p6,p7=r18,_PAGE_P_BIT		// page present bit cleared?
   1.171 -	mov r22=cr.iha				// get the VHPT address that caused the TLB miss
   1.172 +	mov r22=cr.iha				// get the VHPT address that
   1.173 +						//   caused the TLB miss
   1.174  	;;					// avoid RAW on p7
   1.175 -(p7)	tbit.nz.unc p10,p11=r19,32		// is it an instruction TLB miss?
   1.176 -	dep r23=0,r20,0,PAGE_SHIFT		// clear low bits to get page address
   1.177 +(p7)	tbit.nz.unc p10,p11=r19,32		// is it an instruction TLB
   1.178 +						//   miss?
   1.179 +	dep r23=0,r20,0,PAGE_SHIFT		// clear low bits to get page
   1.180 +						//   address
   1.181  	;;
   1.182 -(p10)	itc.i r18				// insert the instruction TLB entry
   1.183 +(p10)	itc.i r18				// insert the instruction TLB
   1.184 +						//   entry
   1.185  (p11)	itc.d r18				// insert the data TLB entry
   1.186 -(p6)	br.cond.spnt.many page_fault		// handle bad address/page not present (page fault)
   1.187 +(p6)	br.cond.spnt.many page_fault		// handle bad address/page not
   1.188 +						//   present (page fault)
   1.189  	mov cr.ifa=r22
   1.190  
   1.191  #ifdef CONFIG_HUGETLB_PAGE
   1.192 -(p8)	mov cr.itir=r25				// change to default page-size for VHPT
   1.193 +(p8)	mov cr.itir=r25				// change to default page-size
   1.194 +						//   for VHPT
   1.195  #endif
   1.196  
   1.197  	/*
   1.198 -	 * Now compute and insert the TLB entry for the virtual page table.  We never
   1.199 -	 * execute in a page table page so there is no need to set the exception deferral
   1.200 -	 * bit.
   1.201 +	 * Now compute and insert the TLB entry for the virtual page table.
   1.202 +	 * We never execute in a page table page so there is no need to set
   1.203 +	 * the exception deferral bit.
   1.204  	 */
   1.205  	adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
   1.206  	;;
   1.207 @@ -203,15 +221,15 @@ ENTRY(vhpt_miss)
   1.208  	;;
   1.209  #ifdef CONFIG_SMP
   1.210  	/*
   1.211 -	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
   1.212 -	 * cannot possibly affect the following loads:
   1.213 +	 * Tell the assemblers dependency-violation checker that the above
   1.214 +	 * "itc" instructions cannot possibly affect the following loads:
   1.215  	 */
   1.216  	dv_serialize_data
   1.217  
   1.218  	/*
   1.219 -	 * Re-check L2 and L3 pagetable.  If they changed, we may have received a ptc.g
   1.220 -	 * between reading the pagetable and the "itc".  If so, flush the entry we
   1.221 -	 * inserted and retry.
   1.222 +	 * Re-check L2 and L3 pagetable.  If they changed, we may have 
   1.223 +	 * received a ptc.g between reading the pagetable and the "itc".
   1.224 +	 * If so, flush the entry we inserted and retry.
   1.225  	 */
   1.226  	ld8 r25=[r21]				// read L3 PTE again
   1.227  	ld8 r26=[r17]				// read L2 entry again
   1.228 @@ -231,7 +249,7 @@ ENTRY(vhpt_miss)
   1.229  END(vhpt_miss)
   1.230  
   1.231  	.org ia64_ivt+0x400
   1.232 -/////////////////////////////////////////////////////////////////////////////////////////
   1.233 +//////////////////////////////////////////////////////////////////////////
   1.234  // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
   1.235  ENTRY(itlb_miss)
   1.236  	DBG_FAULT(1)
   1.237 @@ -266,7 +284,8 @@ ENTRY(itlb_miss)
   1.238  	mov r31=pr				// save predicates
   1.239  .itlb_fault:
   1.240  	mov r17=cr.iha				// get virtual address of L3 PTE
   1.241 -	movl r30=1f				// load nested fault continuation point
   1.242 +	movl r30=1f				// load nested fault 
   1.243 +						//   continuation point
   1.244  	;;
   1.245  1:	ld8 r18=[r17]				// read L3 PTE
   1.246  	;;
   1.247 @@ -278,13 +297,13 @@ 1:	ld8 r18=[r17]				// read L3 PTE
   1.248  	;;
   1.249  #ifdef CONFIG_SMP
   1.250  	/*
   1.251 -	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
   1.252 -	 * cannot possibly affect the following loads:
   1.253 +	 * Tell the assemblers dependency-violation checker that the above
   1.254 +	 * "itc" instructions cannot possibly affect the following loads:
   1.255  	 */
   1.256  	dv_serialize_data
   1.257  
   1.258 -	ld8 r19=[r17]				// read L3 PTE again and see if same
   1.259 -	mov r20=PAGE_SHIFT<<2			// setup page size for purge
   1.260 +	ld8 r19=[r17]			// read L3 PTE again and see if same
   1.261 +	mov r20=PAGE_SHIFT<<2		// setup page size for purge
   1.262  	;;
   1.263  	cmp.ne p7,p0=r18,r19
   1.264  	;;
   1.265 @@ -295,26 +314,25 @@ 1:	ld8 r18=[r17]				// read L3 PTE
   1.266  END(itlb_miss)
   1.267  
   1.268  	.org ia64_ivt+0x0800
   1.269 -/////////////////////////////////////////////////////////////////////////////////////////
   1.270 +//////////////////////////////////////////////////////////////////////////
   1.271  // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
   1.272  ENTRY(dtlb_miss)
   1.273  	DBG_FAULT(2)
   1.274  #ifdef XEN
   1.275 -	mov r16=cr.ifa				// get virtual address
   1.276 +	mov r16=cr.ifa			// get virtual address
   1.277  	mov r31=pr
   1.278  	;;
   1.279  	extr.u r17=r16,59,5
   1.280  	;;
   1.281 -	/* If address belongs to VMM, go to alt tlb handler */
   1.282 -	cmp.eq p6,p0=0x1e,r17
   1.283 +	cmp.eq p6,p0=0x1e,r17		// if the address belongs to VMM, go
   1.284 +					//   to the alternate tlb handler
   1.285  (p6)	br.cond.spnt	late_alt_dtlb_miss
   1.286  	;;
   1.287  	cmp.eq p6,p0=0x1d,r17
   1.288  (p6)	br.cond.spnt	late_alt_dtlb_miss
   1.289  	;;
   1.290  #if VHPT_ENABLED
   1.291 -	// XXX TODO optimization
   1.292 -	mov r30=cr.ipsr
   1.293 +	mov r30=cr.ipsr			// XXX TODO optimization
   1.294  	mov r28=cr.iip			
   1.295  	mov r17=cr.isr
   1.296  	;;
   1.297 @@ -324,15 +342,14 @@ ENTRY(dtlb_miss)
   1.298  	cmp.ne p6, p0 = r0, r18			// cpl == 0?
   1.299  (p6)	br.cond.sptk 2f
   1.300  
   1.301 -	// is speculation bit on?
   1.302 -	tbit.nz p7,p0=r17,IA64_ISR_SP_BIT	
   1.303 +	tbit.nz p7,p0=r17,IA64_ISR_SP_BIT	// is speculation bit on?
   1.304  	;; 
   1.305  (p7)	br.cond.spnt 2f
   1.306  
   1.307 -	// Is the faulted iip in vmm area?
   1.308 -	// check [59:58] bit
   1.309 -	// 00, 11: guest
   1.310 -	// 01, 10: vmm
   1.311 +	// Is the faulted iip in the vmm area?
   1.312 +	//    -- check [59:58] bit
   1.313 +	//    -- if 00, 11: guest
   1.314 +	//    -- if 01, 10: vmm
   1.315  	extr.u r19 = r28, 58, 2
   1.316  	;; 
   1.317  	cmp.eq p10, p0 = 0x0, r19
   1.318 @@ -341,17 +358,16 @@ ENTRY(dtlb_miss)
   1.319  (p11)	br.cond.sptk 2f
   1.320  
   1.321  	// Is the faulted address is in the identity mapping area?
   1.322 -	// 0xf000... or 0xe8000...
   1.323 +	// must be either 0xf000... or 0xe8000...
   1.324  	extr.u r20 = r16, 59, 5
   1.325  	;; 
   1.326 -	cmp.eq p12, p0 = 0x1e, r20 // (0xf0 >> 3) = 0x1e
   1.327 +	cmp.eq p12, p0 = 0x1e, r20 	// (0xf0 >> 3) = 0x1e
   1.328  (p12)	br.cond.spnt 1f
   1.329 -	cmp.eq p0, p13 = 0x1d, r20 // (0xe8 >> 3) = 0x1d
   1.330 +	cmp.eq p0, p13 = 0x1d, r20 	// (0xe8 >> 3) = 0x1d
   1.331  (p13)	br.cond.sptk 2f
   1.332  
   1.333  1:
   1.334 -	// xen identity mappin area.
   1.335 -	movl r24=PAGE_KERNEL
   1.336 +	movl r24=PAGE_KERNEL 		// xen identity mapping area.
   1.337  	movl r25=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
   1.338  	;;
   1.339  	shr.u r26=r16,55	// move address bit 59 to bit 4
   1.340 @@ -361,7 +377,8 @@ 1:
   1.341  	;; 
   1.342  	or r25=r25,r24		// insert PTE control bits into r25
   1.343  	;;
   1.344 -	or r25=r25,r26		// set bit 4 (uncached) if the access was to region 6
   1.345 +	or r25=r25,r26		// set bit 4 (uncached) if the access was to
   1.346 +				//   region 6
   1.347  	;;
   1.348  	itc.d r25		// insert the TLB entry
   1.349  	mov pr=r31,-1
   1.350 @@ -388,7 +405,8 @@ 2:
   1.351  #endif
   1.352  dtlb_fault:
   1.353  	mov r17=cr.iha				// get virtual address of L3 PTE
   1.354 -	movl r30=1f				// load nested fault continuation point
   1.355 +	movl r30=1f				// load nested fault 
   1.356 +						//   continuation point
   1.357  	;;
   1.358  1:	ld8 r18=[r17]				// read L3 PTE
   1.359  	;;
   1.360 @@ -400,13 +418,13 @@ 1:	ld8 r18=[r17]				// read L3 PTE
   1.361  	;;
   1.362  #ifdef CONFIG_SMP
   1.363  	/*
   1.364 -	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
   1.365 -	 * cannot possibly affect the following loads:
   1.366 +	 * Tell the assemblers dependency-violation checker that the above
   1.367 +	 * "itc" instructions cannot possibly affect the following loads:
   1.368  	 */
   1.369  	dv_serialize_data
   1.370  
   1.371 -	ld8 r19=[r17]				// read L3 PTE again and see if same
   1.372 -	mov r20=PAGE_SHIFT<<2			// setup page size for purge
   1.373 +	ld8 r19=[r17]			// read L3 PTE again and see if same
   1.374 +	mov r20=PAGE_SHIFT<<2		// setup page size for purge
   1.375  	;;
   1.376  	cmp.ne p7,p0=r18,r19
   1.377  	;;
   1.378 @@ -417,7 +435,7 @@ 1:	ld8 r18=[r17]				// read L3 PTE
   1.379  END(dtlb_miss)
   1.380  
   1.381  	.org ia64_ivt+0x0c00
   1.382 -/////////////////////////////////////////////////////////////////////////////////////////
   1.383 +//////////////////////////////////////////////////////////////////////////
   1.384  // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
   1.385  ENTRY(alt_itlb_miss)
   1.386  	DBG_FAULT(3)
   1.387 @@ -439,14 +457,14 @@ late_alt_itlb_miss:
   1.388  	;;
   1.389  #endif
   1.390  #ifdef CONFIG_DISABLE_VHPT
   1.391 -	shr.u r22=r16,61			// get the region number into r21
   1.392 +	shr.u r22=r16,61		// get the region number into r21
   1.393  	;;
   1.394 -	cmp.gt p8,p0=6,r22			// user mode
   1.395 +	cmp.gt p8,p0=6,r22		// user mode
   1.396  	;;
   1.397  (p8)	thash r17=r16
   1.398  	;;
   1.399  (p8)	mov cr.iha=r17
   1.400 -(p8)	mov r29=b0				// save b0
   1.401 +(p8)	mov r29=b0			// save b0
   1.402  (p8)	br.cond.dptk .itlb_fault
   1.403  #endif
   1.404  	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
   1.405 @@ -463,7 +481,8 @@ late_alt_itlb_miss:
   1.406  	cmp.ne p8,p0=r0,r23	// psr.cpl != 0?
   1.407  	or r19=r17,r19		// insert PTE control bits into r19
   1.408  	;;
   1.409 -	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
   1.410 +	or r19=r19,r18		// set bit 4 (uncached) if the access was to
   1.411 +				//   region 6
   1.412  (p8)	br.cond.spnt page_fault
   1.413  	;;
   1.414  	itc.i r19		// insert the TLB entry
   1.415 @@ -472,7 +491,7 @@ late_alt_itlb_miss:
   1.416  END(alt_itlb_miss)
   1.417  
   1.418  	.org ia64_ivt+0x1000
   1.419 -/////////////////////////////////////////////////////////////////////////////////////////
   1.420 +//////////////////////////////////////////////////////////////////////////
   1.421  // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
   1.422  ENTRY(alt_dtlb_miss)
   1.423  	DBG_FAULT(4)
   1.424 @@ -503,13 +522,15 @@ late_alt_dtlb_miss:
   1.425  	tbit.nz p6,p7=r20,IA64_ISR_SP_BIT	// is speculation bit on?
   1.426  #ifdef XEN
   1.427  	shr.u r18=r16,55			// move address bit 59 to bit 4
   1.428 -	and r19=r19,r16				// clear ed, reserved bits, and PTE control bits
   1.429 +	and r19=r19,r16				// clear ed, reserved bits, and
   1.430 +						//   PTE control bits
   1.431  	tbit.nz p9,p0=r20,IA64_ISR_NA_BIT	// is non-access bit on?
   1.432  	;;
   1.433  	and r18=0x10,r18	// bit 4=address-bit(59)
   1.434  #else
   1.435  	shr.u r18=r16,57			// move address bit 61 to bit 4
   1.436 -	and r19=r19,r16				// clear ed, reserved bits, and PTE control bits
   1.437 +	and r19=r19,r16				// clear ed, reserved bits, and
   1.438 +						//   PTE control bits
   1.439  	tbit.nz p9,p0=r20,IA64_ISR_NA_BIT	// is non-access bit on?
   1.440  	;;
   1.441  	andcm r18=0x10,r18	// bit 4=~address-bit(61)
   1.442 @@ -520,36 +541,41 @@ late_alt_dtlb_miss:
   1.443  #ifdef XEN
   1.444  	;;
   1.445  #ifdef CONFIG_VIRTUAL_FRAME_TABLE
   1.446 -	// Test for the address of virtual frame_table
   1.447 -	shr r22=r16,56;;
   1.448 +	shr r22=r16,56	 	// Test for the address of virtual frame_table
   1.449 +	;;
   1.450  	cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
   1.451  (p8)	br.cond.sptk frametable_miss ;;
   1.452  #endif
   1.453 -	// Test for Xen address, if not handle via page_fault
   1.454 -	// note that 0xf000 (cached) and 0xe800 (uncached) addresses
   1.455 +	// If it is not a Xen address, handle it via page_fault.
   1.456 +	// Note that 0xf000 (cached) and 0xe800 (uncached) addresses
   1.457  	// should be OK.
   1.458 -	extr.u r22=r16,59,5;;
   1.459 +	extr.u r22=r16,59,5
   1.460 +	;;
   1.461  	cmp.eq p8,p0=0x1e,r22
   1.462 -(p8)	br.cond.spnt 1f;;
   1.463 +(p8)	br.cond.spnt 1f
   1.464 +	;;
   1.465  	cmp.ne p8,p0=0x1d,r22
   1.466 -(p8)	br.cond.sptk page_fault ;;
   1.467 +(p8)	br.cond.sptk page_fault
   1.468 +	;;
   1.469  1:
   1.470  #endif
   1.471  
   1.472  	dep r21=-1,r21,IA64_PSR_ED_BIT,1
   1.473  	or r19=r19,r17		// insert PTE control bits into r19
   1.474  	;;
   1.475 -	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
   1.476 +	or r19=r19,r18		// set bit 4 (uncached) if the access was to
   1.477 +				//   region 6
   1.478  (p6)	mov cr.ipsr=r21
   1.479  	;;
   1.480  (p7)	itc.d r19		// insert the TLB entry
   1.481  	mov pr=r31,-1
   1.482  	rfi
   1.483  END(alt_dtlb_miss)
   1.484 +
   1.485  #ifdef CONFIG_VIRTUAL_FRAME_TABLE	
   1.486  GLOBAL_ENTRY(frametable_miss)
   1.487  	rsm psr.dt		// switch to using physical data addressing
   1.488 -	movl r24=(frametable_pg_dir-PAGE_OFFSET)	// r24=__pa(frametable_pg_dir)
   1.489 +	movl r24=(frametable_pg_dir-PAGE_OFFSET)  // r24=__pa(frametable_pg_dir)
   1.490  	;;
   1.491  	srlz.d
   1.492  	extr.u r17=r16,PGDIR_SHIFT,(PAGE_SHIFT-3)
   1.493 @@ -583,6 +609,7 @@ GLOBAL_ENTRY(frametable_miss)
   1.494  	mov pr=r31,-1		// restore predicate registers
   1.495  	rfi
   1.496  END(frametable_miss)
   1.497 +
   1.498  ENTRY(frametable_fault)
   1.499  	ssm psr.dt		// switch to using virtual data addressing
   1.500  	mov r18=cr.iip
   1.501 @@ -590,7 +617,8 @@ ENTRY(frametable_fault)
   1.502  	;;
   1.503  	cmp.eq p6,p7=r18,r19	// is faulting addrress ia64_frametable_probe?
   1.504  	mov r8=0		// assumes that 'probe.r' uses r8
   1.505 -	dep r21=-1,r21,IA64_PSR_RI_BIT+1,1 // return to next instrucition in bundle 2
   1.506 +	dep r21=-1,r21,IA64_PSR_RI_BIT+1,1 // return to next instruction in
   1.507 +					   //   bundle 2
   1.508  	;;
   1.509  (p6)	mov cr.ipsr=r21
   1.510  	mov r19=4		// FAULT(4)
   1.511 @@ -599,6 +627,7 @@ ENTRY(frametable_fault)
   1.512  	mov pr=r31,-1
   1.513  	rfi
   1.514  END(frametable_fault)
   1.515 +
   1.516  GLOBAL_ENTRY(ia64_frametable_probe)
   1.517  	{
   1.518  	probe.r	r8=r32,0	// destination register must be r8
   1.519 @@ -615,18 +644,19 @@ ENTRY(nested_dtlb_miss)
   1.520  	DBG_FAULT(5)
   1.521  #ifdef XEN
   1.522  	mov b0=r30
   1.523 -	br.sptk.many b0				// return to continuation point
   1.524 +	br.sptk.many b0			// return to the continuation point
   1.525  	;;
   1.526  #else
   1.527  	/*
   1.528 -	 * In the absence of kernel bugs, we get here when the virtually mapped linear
   1.529 -	 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
   1.530 -	 * Access-bit, or Data Access-bit faults).  If the DTLB entry for the virtual page
   1.531 -	 * table is missing, a nested TLB miss fault is triggered and control is
   1.532 -	 * transferred to this point.  When this happens, we lookup the pte for the
   1.533 -	 * faulting address by walking the page table in physical mode and return to the
   1.534 -	 * continuation point passed in register r30 (or call page_fault if the address is
   1.535 -	 * not mapped).
   1.536 +	 * In the absence of kernel bugs, we get here when the virtually
   1.537 +	 * mapped linear page table is accessed non-speculatively (e.g.,
   1.538 +	 * in the Dirty-bit, Instruction Access-bit, or Data Access-bit 
   1.539 +	 * faults).  If the DTLB entry for the virtual page table is missing,
   1.540 +	 * a nested TLB miss fault is triggered and control is transferred 
   1.541 +	 * to this point.  When this happens, we lookup the pte for the
   1.542 +	 * faulting address by walking the page table in physical mode
   1.543 +	 * and return to the continuation point passed in register r30
   1.544 +	 * (or call page_fault if the address is not mapped).
   1.545  	 *
   1.546  	 * Input:	r16:	faulting address
   1.547  	 *		r29:	saved b0
   1.548 @@ -640,47 +670,52 @@ ENTRY(nested_dtlb_miss)
   1.549  	 *
   1.550  	 * Clobbered:	b0, r18, r19, r21, psr.dt (cleared)
   1.551  	 */
   1.552 -	rsm psr.dt				// switch to using physical data addressing
   1.553 -	mov r19=IA64_KR(PT_BASE)		// get the page table base address
   1.554 -	shl r21=r16,3				// shift bit 60 into sign bit
   1.555 +	rsm psr.dt			// switch to using physical data 
   1.556 +					//   addressing
   1.557 +	mov r19=IA64_KR(PT_BASE)	// get the page table base address
   1.558 +	shl r21=r16,3			// shift bit 60 into sign bit
   1.559  	;;
   1.560 -	shr.u r17=r16,61			// get the region number into r17
   1.561 +	shr.u r17=r16,61		// get the region number into r17
   1.562  	;;
   1.563 -	cmp.eq p6,p7=5,r17			// is faulting address in region 5?
   1.564 -	shr.u r18=r16,PGDIR_SHIFT		// get bits 33-63 of faulting address
   1.565 +	cmp.eq p6,p7=5,r17		// is faulting address in region 5?
   1.566 +	shr.u r18=r16,PGDIR_SHIFT	// get bits 33-63 of faulting address
   1.567  	;;
   1.568 -(p7)	dep r17=r17,r19,(PAGE_SHIFT-3),3	// put region number bits in place
   1.569 +(p7)	dep r17=r17,r19,(PAGE_SHIFT-3),3  // put region number bits in place
   1.570  
   1.571  	srlz.d
   1.572 -	LOAD_PHYSICAL(p6, r19, swapper_pg_dir)	// region 5 is rooted at swapper_pg_dir
   1.573 +	LOAD_PHYSICAL(p6, r19, swapper_pg_dir)	// region 5 is rooted at 
   1.574 +						//   swapper_pg_dir
   1.575  
   1.576  	.pred.rel "mutex", p6, p7
   1.577  (p6)	shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
   1.578  (p7)	shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
   1.579  	;;
   1.580 -(p6)	dep r17=r18,r19,3,(PAGE_SHIFT-3)	// r17=PTA + IFA(33,42)*8
   1.581 -(p7)	dep r17=r18,r17,3,(PAGE_SHIFT-6)	// r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
   1.582 -	cmp.eq p7,p6=0,r21			// unused address bits all zeroes?
   1.583 -	shr.u r18=r16,PMD_SHIFT			// shift L2 index into position
   1.584 +(p6)	dep r17=r18,r19,3,(PAGE_SHIFT-3)  // r17=PTA + IFA(33,42)*8
   1.585 +(p7)	dep r17=r18,r17,3,(PAGE_SHIFT-6)  // r17=PTA + (((IFA(61,63) << 7) |
   1.586 +					  //            IFA(33,39))*8)
   1.587 +	cmp.eq p7,p6=0,r21		// unused address bits all zeroes?
   1.588 +	shr.u r18=r16,PMD_SHIFT		// shift L2 index into position
   1.589  	;;
   1.590 -	ld8 r17=[r17]				// fetch the L1 entry (may be 0)
   1.591 +	ld8 r17=[r17]			// fetch the L1 entry (may be 0)
   1.592  	;;
   1.593 -(p7)	cmp.eq p6,p7=r17,r0			// was L1 entry NULL?
   1.594 -	dep r17=r18,r17,3,(PAGE_SHIFT-3)	// compute address of L2 page table entry
   1.595 +(p7)	cmp.eq p6,p7=r17,r0		// was L1 entry NULL?
   1.596 +	dep r17=r18,r17,3,(PAGE_SHIFT-3)  // compute address of L2 page table
   1.597 +					  //   entry
   1.598  	;;
   1.599 -(p7)	ld8 r17=[r17]				// fetch the L2 entry (may be 0)
   1.600 -	shr.u r19=r16,PAGE_SHIFT		// shift L3 index into position
   1.601 +(p7)	ld8 r17=[r17]			// fetch the L2 entry (may be 0)
   1.602 +	shr.u r19=r16,PAGE_SHIFT	// shift L3 index into position
   1.603  	;;
   1.604 -(p7)	cmp.eq.or.andcm p6,p7=r17,r0		// was L2 entry NULL?
   1.605 -	dep r17=r19,r17,3,(PAGE_SHIFT-3)	// compute address of L3 page table entry
   1.606 +(p7)	cmp.eq.or.andcm p6,p7=r17,r0	// was L2 entry NULL?
   1.607 +	dep r17=r19,r17,3,(PAGE_SHIFT-3)  // compute address of L3 page table
   1.608 +					  //   entry
   1.609  (p6)	br.cond.spnt page_fault
   1.610  	mov b0=r30
   1.611 -	br.sptk.many b0				// return to continuation point
   1.612 +	br.sptk.many b0			// return to continuation point
   1.613  #endif
   1.614  END(nested_dtlb_miss)
   1.615  
   1.616  	.org ia64_ivt+0x1800
   1.617 -/////////////////////////////////////////////////////////////////////////////////////////
   1.618 +//////////////////////////////////////////////////////////////////////////
   1.619  // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
   1.620  ENTRY(ikey_miss)
   1.621  	DBG_FAULT(6)
   1.622 @@ -691,8 +726,9 @@ ENTRY(ikey_miss)
   1.623  #endif
   1.624  END(ikey_miss)
   1.625  
   1.626 -	//-----------------------------------------------------------------------------------
   1.627 -	// call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
   1.628 +	//----------------------------------------------------------------
   1.629 +	// call do_page_fault (predicates are in r31, psr.dt may be off, 
   1.630 +	// r16 is faulting address)
   1.631  #ifdef XEN
   1.632  GLOBAL_ENTRY(page_fault)
   1.633  #else
   1.634 @@ -713,24 +749,25 @@ ENTRY(page_fault)
   1.635  	mov out0=cr.ifa
   1.636  	mov out1=cr.isr
   1.637  #endif
   1.638 -	adds r3=8,r2				// set up second base pointer
   1.639 +	adds r3=8,r2			// set up second base pointer
   1.640  	;;
   1.641  	ssm psr.ic | PSR_DEFAULT_BITS
   1.642  	;;
   1.643 -	srlz.i					// guarantee that interruption collectin is on
   1.644 +	srlz.i				// guarantee that interruption 
   1.645 +					//   collection is on
   1.646  	;;
   1.647 -(p15)	ssm psr.i				// restore psr.i
   1.648 +(p15)	ssm psr.i			// restore psr.i
   1.649  	movl r14=ia64_leave_kernel
   1.650  	;;
   1.651  	SAVE_REST
   1.652  	mov rp=r14
   1.653  	;;
   1.654 -	adds out2=16,r12			// out2 = pointer to pt_regs
   1.655 +	adds out2=16,r12		// out2 = pointer to pt_regs
   1.656  	br.call.sptk.many b6=ia64_do_page_fault	// ignore return address
   1.657  END(page_fault)
   1.658  
   1.659  	.org ia64_ivt+0x1c00
   1.660 -/////////////////////////////////////////////////////////////////////////////////////////
   1.661 +//////////////////////////////////////////////////////////////////////////
   1.662  // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
   1.663  ENTRY(dkey_miss)
   1.664  	DBG_FAULT(7)
   1.665 @@ -742,32 +779,33 @@ ENTRY(dkey_miss)
   1.666  END(dkey_miss)
   1.667  
   1.668  	.org ia64_ivt+0x2000
   1.669 -/////////////////////////////////////////////////////////////////////////////////////////
   1.670 +//////////////////////////////////////////////////////////////////////////
   1.671  // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
   1.672  ENTRY(dirty_bit)
   1.673  	DBG_FAULT(8)
   1.674  #ifdef XEN
   1.675  	mov r20=cr.ipsr
   1.676 -	mov r31=pr;;
   1.677 -	extr.u r20=r20,IA64_PSR_CPL0_BIT,2;;
   1.678 -	mov r19=8	/* prepare to save predicates */
   1.679 -	cmp.eq p6,p0=r0,r20 	/* cpl == 0?*/
   1.680 +	mov r31=pr
   1.681 +	;;
   1.682 +	extr.u r20=r20,IA64_PSR_CPL0_BIT,2
   1.683 +	;;
   1.684 +	mov r19=8			// prepare to save predicates
   1.685 +	cmp.eq p6,p0=r0,r20 		// cpl == 0?
   1.686  (p6)	br.sptk.few dispatch_to_fault_handler
   1.687 -	/* If shadow mode is not enabled, reflect the fault.  */
   1.688 +	// If shadow mode is not enabled, reflect the fault.
   1.689  	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
   1.690  	;;
   1.691  	ld8 r22=[r22]
   1.692  	;;
   1.693  	add r22=IA64_VCPU_DOMAIN_OFFSET,r22
   1.694  	;;
   1.695 -	/* Read domain.  */
   1.696 -	ld8 r22=[r22]
   1.697 +	ld8 r22=[r22]			// read domain
   1.698  	;;
   1.699  	add r22=IA64_DOMAIN_SHADOW_BITMAP_OFFSET,r22
   1.700  	;;
   1.701  	ld8 r22=[r22]
   1.702  	;;
   1.703 -	cmp.eq p6,p0=r0,r22 	/* !shadow_bitmap ?*/
   1.704 +	cmp.eq p6,p0=r0,r22 		// !shadow_bitmap ?
   1.705  (p6)	br.dptk.many dispatch_reflection
   1.706  
   1.707  	SAVE_MIN_WITH_COVER
   1.708 @@ -779,10 +817,11 @@ ENTRY(dirty_bit)
   1.709  
   1.710  	ssm psr.ic | PSR_DEFAULT_BITS
   1.711  	;;
   1.712 -	srlz.i					// guarantee that interruption collection is on
   1.713 +	srlz.i				// guarantee that interruption 
   1.714 +					//   collection is on
   1.715  	;;
   1.716 -(p15)	ssm psr.i				// restore psr.i
   1.717 -	adds r3=8,r2				// set up second base pointer
   1.718 +(p15)	ssm psr.i			// restore psr.i
   1.719 +	adds r3=8,r2			// set up second base pointer
   1.720  	;;
   1.721  	SAVE_REST
   1.722  	movl r14=ia64_leave_kernel
   1.723 @@ -791,65 +830,69 @@ ENTRY(dirty_bit)
   1.724  	br.call.sptk.many b6=ia64_shadow_fault
   1.725  #else
   1.726  	/*
   1.727 -	 * What we do here is to simply turn on the dirty bit in the PTE.  We need to
   1.728 -	 * update both the page-table and the TLB entry.  To efficiently access the PTE,
   1.729 -	 * we address it through the virtual page table.  Most likely, the TLB entry for
   1.730 -	 * the relevant virtual page table page is still present in the TLB so we can
   1.731 -	 * normally do this without additional TLB misses.  In case the necessary virtual
   1.732 -	 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
   1.733 -	 * up the physical address of the L3 PTE and then continue at label 1 below.
   1.734 +	 * What we do here is to simply turn on the dirty bit in the PTE.
   1.735 +	 * We need to update both the page-table and the TLB entry.  To 
   1.736 +	 * efficiently access the PTE, we address it through the virtual
   1.737 +	 * page table.  Most likely, the TLB entry for the relevant virtual
   1.738 +	 * page table page is still present in the TLB so we can normally 
   1.739 +	 * do this without additional TLB misses.  In case the necessary 
   1.740 +	 * virtual page table TLB entry isn't present, we take a nested 
   1.741 +	 * TLB miss hit where we look up the physical address of the L3
   1.742 +	 * PTE and then continue at label 1 below.
   1.743  	 */
   1.744 -	mov r16=cr.ifa				// get the address that caused the fault
   1.745 -	movl r30=1f				// load continuation point in case of nested fault
   1.746 +	mov r16=cr.ifa			// get the address that caused the 
   1.747 +					//   fault
   1.748 +	movl r30=1f			// load continuation point in case 
   1.749 +					//   of nested fault
   1.750  	;;
   1.751 -	thash r17=r16				// compute virtual address of L3 PTE
   1.752 -	mov r29=b0				// save b0 in case of nested fault
   1.753 -	mov r31=pr				// save pr
   1.754 +	thash r17=r16			// compute virtual address of L3 PTE
   1.755 +	mov r29=b0			// save b0 in case of nested fault
   1.756 +	mov r31=pr			// save pr
   1.757  #ifdef CONFIG_SMP
   1.758 -	mov r28=ar.ccv				// save ar.ccv
   1.759 +	mov r28=ar.ccv			// save ar.ccv
   1.760  	;;
   1.761  1:	ld8 r18=[r17]
   1.762 -	;;					// avoid RAW on r18
   1.763 -	mov ar.ccv=r18				// set compare value for cmpxchg
   1.764 -	or r25=_PAGE_D|_PAGE_A,r18		// set the dirty and accessed bits
   1.765 +	;;				// avoid RAW on r18
   1.766 +	mov ar.ccv=r18			// set compare value for cmpxchg
   1.767 +	or r25=_PAGE_D|_PAGE_A,r18	// set the dirty and accessed bits
   1.768  	;;
   1.769  	cmpxchg8.acq r26=[r17],r25,ar.ccv
   1.770  	mov r24=PAGE_SHIFT<<2
   1.771  	;;
   1.772  	cmp.eq p6,p7=r26,r18
   1.773  	;;
   1.774 -(p6)	itc.d r25				// install updated PTE
   1.775 +(p6)	itc.d r25			// install updated PTE
   1.776  	;;
   1.777  	/*
   1.778 -	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
   1.779 -	 * cannot possibly affect the following loads:
   1.780 +	 * Tell the assemblers dependency-violation checker that the above
   1.781 +	 * "itc" instructions cannot possibly affect the following loads:
   1.782  	 */
   1.783  	dv_serialize_data
   1.784  
   1.785 -	ld8 r18=[r17]				// read PTE again
   1.786 +	ld8 r18=[r17]			// read PTE again
   1.787  	;;
   1.788 -	cmp.eq p6,p7=r18,r25			// is it same as the newly installed
   1.789 +	cmp.eq p6,p7=r18,r25		// is it same as the newly installed
   1.790  	;;
   1.791  (p7)	ptc.l r16,r24
   1.792 -	mov b0=r29				// restore b0
   1.793 +	mov b0=r29			// restore b0
   1.794  	mov ar.ccv=r28
   1.795  #else
   1.796  	;;
   1.797  1:	ld8 r18=[r17]
   1.798 -	;;					// avoid RAW on r18
   1.799 -	or r18=_PAGE_D|_PAGE_A,r18		// set the dirty and accessed bits
   1.800 -	mov b0=r29				// restore b0
   1.801 +	;;				// avoid RAW on r18
   1.802 +	or r18=_PAGE_D|_PAGE_A,r18	// set the dirty and accessed bits
   1.803 +	mov b0=r29			// restore b0
   1.804  	;;
   1.805 -	st8 [r17]=r18				// store back updated PTE
   1.806 -	itc.d r18				// install updated PTE
   1.807 +	st8 [r17]=r18			// store back updated PTE
   1.808 +	itc.d r18			// install updated PTE
   1.809  #endif
   1.810 -	mov pr=r31,-1				// restore pr
   1.811 +	mov pr=r31,-1			// restore pr
   1.812  	rfi
   1.813  #endif
   1.814  END(dirty_bit)
   1.815  
   1.816  	.org ia64_ivt+0x2400
   1.817 -/////////////////////////////////////////////////////////////////////////////////////////
   1.818 +//////////////////////////////////////////////////////////////////////////
   1.819  // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
   1.820  ENTRY(iaccess_bit)
   1.821  	DBG_FAULT(9)
   1.822 @@ -862,9 +905,11 @@ ENTRY(iaccess_bit)
   1.823  	br.sptk.many fast_access_reflect;;
   1.824  #else
   1.825  	// Like Entry 8, except for instruction access
   1.826 -	mov r16=cr.ifa				// get the address that caused the fault
   1.827 -	movl r30=1f				// load continuation point in case of nested fault
   1.828 -	mov r31=pr				// save predicates
   1.829 +	mov r16=cr.ifa			// get the address that caused the
   1.830 +					//   fault
   1.831 +	movl r30=1f			// load continuation point in case 
   1.832 +					//   of nested fault
   1.833 +	mov r31=pr			// save predicates
   1.834  #ifdef CONFIG_ITANIUM
   1.835  	/*
   1.836  	 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
   1.837 @@ -872,50 +917,50 @@ ENTRY(iaccess_bit)
   1.838  	mov r17=cr.ipsr
   1.839  	;;
   1.840  	mov r18=cr.iip
   1.841 -	tbit.z p6,p0=r17,IA64_PSR_IS_BIT	// IA64 instruction set?
   1.842 +	tbit.z p6,p0=r17,IA64_PSR_IS_BIT  // IA64 instruction set?
   1.843  	;;
   1.844 -(p6)	mov r16=r18				// if so, use cr.iip instead of cr.ifa
   1.845 +(p6)	mov r16=r18			// if so, use cr.iip instead of cr.ifa
   1.846  #endif /* CONFIG_ITANIUM */
   1.847  	;;
   1.848 -	thash r17=r16				// compute virtual address of L3 PTE
   1.849 -	mov r29=b0				// save b0 in case of nested fault)
   1.850 +	thash r17=r16			// compute virtual address of L3 PTE
   1.851 +	mov r29=b0			// save b0 in case of nested fault)
   1.852  #ifdef CONFIG_SMP
   1.853 -	mov r28=ar.ccv				// save ar.ccv
   1.854 +	mov r28=ar.ccv			// save ar.ccv
   1.855  	;;
   1.856  1:	ld8 r18=[r17]
   1.857  	;;
   1.858 -	mov ar.ccv=r18				// set compare value for cmpxchg
   1.859 -	or r25=_PAGE_A,r18			// set the accessed bit
   1.860 +	mov ar.ccv=r18			// set compare value for cmpxchg
   1.861 +	or r25=_PAGE_A,r18		// set the accessed bit
   1.862  	;;
   1.863  	cmpxchg8.acq r26=[r17],r25,ar.ccv
   1.864  	mov r24=PAGE_SHIFT<<2
   1.865  	;;
   1.866  	cmp.eq p6,p7=r26,r18
   1.867  	;;
   1.868 -(p6)	itc.i r25				// install updated PTE
   1.869 +(p6)	itc.i r25			// install updated PTE
   1.870  	;;
   1.871  	/*
   1.872 -	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
   1.873 -	 * cannot possibly affect the following loads:
   1.874 +	 * Tell the assemblers dependency-violation checker that the above
   1.875 +	 * "itc" instructions cannot possibly affect the following loads:
   1.876  	 */
   1.877  	dv_serialize_data
   1.878  
   1.879 -	ld8 r18=[r17]				// read PTE again
   1.880 +	ld8 r18=[r17]			// read PTE again
   1.881  	;;
   1.882 -	cmp.eq p6,p7=r18,r25			// is it same as the newly installed
   1.883 +	cmp.eq p6,p7=r18,r25		// is it same as the newly installed
   1.884  	;;
   1.885  (p7)	ptc.l r16,r24
   1.886 -	mov b0=r29				// restore b0
   1.887 +	mov b0=r29			// restore b0
   1.888  	mov ar.ccv=r28
   1.889  #else /* !CONFIG_SMP */
   1.890  	;;
   1.891  1:	ld8 r18=[r17]
   1.892  	;;
   1.893 -	or r18=_PAGE_A,r18			// set the accessed bit
   1.894 -	mov b0=r29				// restore b0
   1.895 +	or r18=_PAGE_A,r18		// set the accessed bit
   1.896 +	mov b0=r29			// restore b0
   1.897  	;;
   1.898 -	st8 [r17]=r18				// store back updated PTE
   1.899 -	itc.i r18				// install updated PTE
   1.900 +	st8 [r17]=r18			// store back updated PTE
   1.901 +	itc.i r18			// install updated PTE
   1.902  #endif /* !CONFIG_SMP */
   1.903  	mov pr=r31,-1
   1.904  	rfi
   1.905 @@ -923,7 +968,7 @@ 1:	ld8 r18=[r17]
   1.906  END(iaccess_bit)
   1.907  
   1.908  	.org ia64_ivt+0x2800
   1.909 -/////////////////////////////////////////////////////////////////////////////////////////
   1.910 +//////////////////////////////////////////////////////////////////////////
   1.911  // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
   1.912  ENTRY(daccess_bit)
   1.913  	DBG_FAULT(10)
   1.914 @@ -933,74 +978,80 @@ ENTRY(daccess_bit)
   1.915  	mov r31=pr
   1.916  	mov r19=10
   1.917  	mov r20=0x2800
   1.918 -	br.sptk.many fast_access_reflect;;
   1.919 +	br.sptk.many fast_access_reflect
   1.920 +	;;
   1.921  #else
   1.922  	// Like Entry 8, except for data access
   1.923 -	mov r16=cr.ifa				// get the address that caused the fault
   1.924 -	movl r30=1f				// load continuation point in case of nested fault
   1.925 +	mov r16=cr.ifa			// get the address that caused the
   1.926 +					//   fault
   1.927 +	movl r30=1f			// load continuation point in case
   1.928 +					//   of nested fault
   1.929  	;;
   1.930 -	thash r17=r16				// compute virtual address of L3 PTE
   1.931 +	thash r17=r16			// compute virtual address of L3 PTE
   1.932  	mov r31=pr
   1.933 -	mov r29=b0				// save b0 in case of nested fault)
   1.934 +	mov r29=b0			// save b0 in case of nested fault)
   1.935  #ifdef CONFIG_SMP
   1.936 -	mov r28=ar.ccv				// save ar.ccv
   1.937 +	mov r28=ar.ccv			// save ar.ccv
   1.938  	;;
   1.939  1:	ld8 r18=[r17]
   1.940 -	;;					// avoid RAW on r18
   1.941 -	mov ar.ccv=r18				// set compare value for cmpxchg
   1.942 -	or r25=_PAGE_A,r18			// set the dirty bit
   1.943 +	;;				// avoid RAW on r18
   1.944 +	mov ar.ccv=r18			// set compare value for cmpxchg
   1.945 +	or r25=_PAGE_A,r18		// set the dirty bit
   1.946  	;;
   1.947  	cmpxchg8.acq r26=[r17],r25,ar.ccv
   1.948  	mov r24=PAGE_SHIFT<<2
   1.949  	;;
   1.950  	cmp.eq p6,p7=r26,r18
   1.951  	;;
   1.952 -(p6)	itc.d r25				// install updated PTE
   1.953 +(p6)	itc.d r25			// install updated PTE
   1.954  	/*
   1.955 -	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
   1.956 -	 * cannot possibly affect the following loads:
   1.957 +	 * Tell the assemblers dependency-violation checker that the above
   1.958 +	 * "itc" instructions cannot possibly affect the following loads:
   1.959  	 */
   1.960  	dv_serialize_data
   1.961  	;;
   1.962 -	ld8 r18=[r17]				// read PTE again
   1.963 +	ld8 r18=[r17]			// read PTE again
   1.964  	;;
   1.965 -	cmp.eq p6,p7=r18,r25			// is it same as the newly installed
   1.966 +	cmp.eq p6,p7=r18,r25		// is it same as the newly installed
   1.967  	;;
   1.968  (p7)	ptc.l r16,r24
   1.969  	mov ar.ccv=r28
   1.970  #else
   1.971  	;;
   1.972  1:	ld8 r18=[r17]
   1.973 -	;;					// avoid RAW on r18
   1.974 -	or r18=_PAGE_A,r18			// set the accessed bit
   1.975 +	;;				// avoid RAW on r18
   1.976 +	or r18=_PAGE_A,r18		// set the accessed bit
   1.977  	;;
   1.978 -	st8 [r17]=r18				// store back updated PTE
   1.979 -	itc.d r18				// install updated PTE
   1.980 +	st8 [r17]=r18			// store back updated PTE
   1.981 +	itc.d r18			// install updated PTE
   1.982  #endif
   1.983 -	mov b0=r29				// restore b0
   1.984 +	mov b0=r29			// restore b0
   1.985  	mov pr=r31,-1
   1.986  	rfi
   1.987  #endif
   1.988  END(daccess_bit)
   1.989  
   1.990  	.org ia64_ivt+0x2c00
   1.991 -/////////////////////////////////////////////////////////////////////////////////////////
   1.992 +//////////////////////////////////////////////////////////////////////////
   1.993  // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
   1.994  ENTRY(break_fault)
   1.995  	/*
   1.996 -	 * The streamlined system call entry/exit paths only save/restore the initial part
   1.997 -	 * of pt_regs.  This implies that the callers of system-calls must adhere to the
   1.998 -	 * normal procedure calling conventions.
   1.999 +	 * The streamlined system call entry/exit paths only save/restore 
  1.1000 +	 * the initial part of pt_regs.  This implies that the callers of
  1.1001 +	 * system-calls must adhere to the normal procedure calling 
  1.1002 +	 * conventions.
  1.1003  	 *
  1.1004  	 *   Registers to be saved & restored:
  1.1005  	 *	CR registers: cr.ipsr, cr.iip, cr.ifs
  1.1006 -	 *	AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
  1.1007 +	 *	AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore,
  1.1008 +	 *		      ar.fpsr
  1.1009  	 * 	others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
  1.1010  	 *   Registers to be restored only:
  1.1011  	 * 	r8-r11: output value from the system call.
  1.1012  	 *
  1.1013 -	 * During system call exit, scratch registers (including r15) are modified/cleared
  1.1014 -	 * to prevent leaking bits from kernel to user level.
  1.1015 +	 * During system call exit, scratch registers (including r15) are
  1.1016 +	 * modified/cleared to prevent leaking bits from kernel to user 
  1.1017 +	 * level.
  1.1018  	 */
  1.1019  	DBG_FAULT(11)
  1.1020  #ifdef XEN
  1.1021 @@ -1009,13 +1060,17 @@ ENTRY(break_fault)
  1.1022  	mov r31=pr
  1.1023  	;;
  1.1024  	cmp.eq p7,p0=r17,r0
  1.1025 -(p7)	br.spnt.few dispatch_break_fault ;;
  1.1026 +(p7)	br.spnt.few dispatch_break_fault
  1.1027 +	;;
  1.1028  #ifdef CRASH_DEBUG
  1.1029 -        // panic can occur before domain0 is created.
  1.1030 -        // in such case referencing XSI_PSR_IC causes nested_dtlb_miss
  1.1031 -        movl r18=CDB_BREAK_NUM ;;
  1.1032 -        cmp.eq p7,p0=r17,r18 ;; 
  1.1033 -(p7)    br.spnt.few dispatch_break_fault ;;
  1.1034 +        // A panic can occur before domain0 is created.  In such cases, 
  1.1035 +	// referencing XSI_PSR_IC causes nested_dtlb_miss.
  1.1036 +        movl r18=CDB_BREAK_NUM
  1.1037 +	;;
  1.1038 +        cmp.eq p7,p0=r17,r18
  1.1039 +	;; 
  1.1040 +(p7)    br.spnt.few dispatch_break_fault
  1.1041 +	;;
  1.1042  #endif
  1.1043  	movl r18=THIS_CPU(current_psr_ic_addr)
  1.1044  	;;
  1.1045 @@ -1026,17 +1081,19 @@ ENTRY(break_fault)
  1.1046  	cmp.eq p7,p0=r0,r17			// is this a psuedo-cover?
  1.1047  (p7)	br.spnt.many dispatch_privop_fault
  1.1048  	;;
  1.1049 -	// if vpsr.ic is off, we have a hyperprivop
  1.1050 -	// A hyperprivop is hand-coded assembly with psr.ic off
  1.1051 -	// which means no calls, no use of r1-r15 and no memory accesses
  1.1052 -	// except to pinned addresses!
  1.1053 +	// If vpsr.ic is off, we have a hyperprivop.  A hyperprivop is
  1.1054 +	// hand-coded assembly with psr.ic off which means it can make
  1.1055 +	// no calls, cannot use r1-r15, and it can have no memory accesses
  1.1056 +	// unless they are to pinned addresses!
  1.1057  	cmp4.eq p7,p0=r0,r19
  1.1058  (p7)	br.sptk.many fast_hyperprivop
  1.1059  	;;
  1.1060 -	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
  1.1061 +	movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
  1.1062 +	;;
  1.1063  	ld8 r22 = [r22]
  1.1064  	;;
  1.1065 -	adds r22=IA64_VCPU_BREAKIMM_OFFSET,r22;;
  1.1066 +	adds r22=IA64_VCPU_BREAKIMM_OFFSET,r22
  1.1067 +	;;
  1.1068  	ld4 r23=[r22];;
  1.1069  	cmp4.eq p6,p7=r23,r17			// Xen-reserved breakimm?
  1.1070  (p6)	br.spnt.many dispatch_break_fault
  1.1071 @@ -1056,78 +1113,86 @@ ENTRY(break_fault)
  1.1072  	mov r26=ar.pfs
  1.1073  	mov r28=cr.iip
  1.1074  #ifndef XEN
  1.1075 -	mov r31=pr				// prepare to save predicates
  1.1076 +	mov r31=pr			// prepare to save predicates
  1.1077  #endif
  1.1078  	mov r20=r1
  1.1079  	;;
  1.1080  	adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
  1.1081 -	cmp.eq p0,p7=r18,r17			// is this a system call? (p7 <- false, if so)
  1.1082 +	cmp.eq p0,p7=r18,r17		// is this a system call? 
  1.1083 +					//   (p7 <- false, if so)
  1.1084  (p7)	br.cond.spnt non_syscall
  1.1085  	;;
  1.1086 -	ld1 r17=[r16]				// load current->thread.on_ustack flag
  1.1087 -	st1 [r16]=r0				// clear current->thread.on_ustack flag
  1.1088 -	add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16	// set r1 for MINSTATE_START_SAVE_MIN_VIRT
  1.1089 +	ld1 r17=[r16]			// load current->thread.on_ustack flag
  1.1090 +	st1 [r16]=r0			// clear current->thread.on_ustack flag
  1.1091 +	add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
  1.1092 +					// set r1 for 
  1.1093 +					//   MINSTATE_START_SAVE_MIN_VIRT
  1.1094  	;;
  1.1095  	invala
  1.1096  
  1.1097  	/* adjust return address so we skip over the break instruction: */
  1.1098  
  1.1099 -	extr.u r8=r29,41,2			// extract ei field from cr.ipsr
  1.1100 +	extr.u r8=r29,41,2		// extract ei field from cr.ipsr
  1.1101  	;;
  1.1102 -	cmp.eq p6,p7=2,r8			// isr.ei==2?
  1.1103 -	mov r2=r1				// setup r2 for ia64_syscall_setup
  1.1104 +	cmp.eq p6,p7=2,r8		// isr.ei==2?
  1.1105 +	mov r2=r1			// setup r2 for ia64_syscall_setup
  1.1106  	;;
  1.1107 -(p6)	mov r8=0				// clear ei to 0
  1.1108 -(p6)	adds r28=16,r28				// switch cr.iip to next bundle cr.ipsr.ei wrapped
  1.1109 -(p7)	adds r8=1,r8				// increment ei to next slot
  1.1110 +(p6)	mov r8=0			// clear ei to 0
  1.1111 +(p6)	adds r28=16,r28			// switch cr.iip to next bundle 
  1.1112 +					//   cr.ipsr.ei wrapped
  1.1113 +(p7)	adds r8=1,r8			// increment ei to next slot
  1.1114  	;;
  1.1115 -	cmp.eq pKStk,pUStk=r0,r17		// are we in kernel mode already?
  1.1116 -	dep r29=r8,r29,41,2			// insert new ei into cr.ipsr
  1.1117 +	cmp.eq pKStk,pUStk=r0,r17	// are we in kernel mode already?
  1.1118 +	dep r29=r8,r29,41,2		// insert new ei into cr.ipsr
  1.1119  	;;
  1.1120  
  1.1121  	// switch from user to kernel RBS:
  1.1122  	MINSTATE_START_SAVE_MIN_VIRT
  1.1123  	br.call.sptk.many b7=ia64_syscall_setup
  1.1124  	;;
  1.1125 -	MINSTATE_END_SAVE_MIN_VIRT		// switch to bank 1
  1.1126 +	MINSTATE_END_SAVE_MIN_VIRT	// switch to bank 1
  1.1127  	ssm psr.ic | PSR_DEFAULT_BITS
  1.1128  	;;
  1.1129 -	srlz.i					// guarantee that interruption collection is on
  1.1130 +	srlz.i				// guarantee that interruption 
  1.1131 +					//   collection is on
  1.1132  	mov r3=NR_syscalls - 1
  1.1133  	;;
  1.1134 -(p15)	ssm psr.i				// restore psr.i
  1.1135 +(p15)	ssm psr.i			// restore psr.i
  1.1136  	// p10==true means out registers are more than 8 or r15's Nat is true
  1.1137  (p10)	br.cond.spnt.many ia64_ret_from_syscall
  1.1138  	;;
  1.1139  	movl r16=sys_call_table
  1.1140  
  1.1141 -	adds r15=-1024,r15			// r15 contains the syscall number---subtract 1024
  1.1142 +	adds r15=-1024,r15		// r15 contains the syscall number --
  1.1143 +					//   subtract 1024 from it
  1.1144  	movl r2=ia64_ret_from_syscall
  1.1145  	;;
  1.1146 -	shladd r20=r15,3,r16			// r20 = sys_call_table + 8*(syscall-1024)
  1.1147 -	cmp.leu p6,p7=r15,r3			// (syscall > 0 && syscall < 1024 + NR_syscalls) ?
  1.1148 -	mov rp=r2				// set the real return addr
  1.1149 +	shladd r20=r15,3,r16		// r20 = sys_call_table + 
  1.1150 +					//       8*(syscall-1024)
  1.1151 +	cmp.leu p6,p7=r15,r3		// (syscall > 0 && syscall < 1024 +
  1.1152 +					//  NR_syscalls) ?
  1.1153 +	mov rp=r2			// set the real return addr
  1.1154  	;;
  1.1155 -(p6)	ld8 r20=[r20]				// load address of syscall entry point
  1.1156 +(p6)	ld8 r20=[r20]			// load address of syscall entry point
  1.1157  (p7)	movl r20=sys_ni_syscall
  1.1158  
  1.1159  	add r2=TI_FLAGS+IA64_TASK_SIZE,r13
  1.1160  	;;
  1.1161 -	ld4 r2=[r2]				// r2 = current_thread_info()->flags
  1.1162 +	ld4 r2=[r2]			// r2 = current_thread_info()->flags
  1.1163  	;;
  1.1164 -	and r2=_TIF_SYSCALL_TRACEAUDIT,r2	// mask trace or audit
  1.1165 +	and r2=_TIF_SYSCALL_TRACEAUDIT,r2  // mask trace or audit
  1.1166  	;;
  1.1167  	cmp.eq p8,p0=r2,r0
  1.1168  	mov b6=r20
  1.1169  	;;
  1.1170 -(p8)	br.call.sptk.many b6=b6			// ignore this return addr
  1.1171 +(p8)	br.call.sptk.many b6=b6		// ignore this return addr
  1.1172  	br.cond.sptk ia64_trace_syscall
  1.1173  	// NOT REACHED
  1.1174  #endif
  1.1175  END(break_fault)
  1.1176  
  1.1177  	.org ia64_ivt+0x3000
  1.1178 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1179 +//////////////////////////////////////////////////////////////////////////
  1.1180  // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
  1.1181  ENTRY(interrupt)
  1.1182  	DBG_FAULT(12)
  1.1183 @@ -1138,11 +1203,16 @@ ENTRY(interrupt)
  1.1184  	// FIXME: this is a hack... use cpuinfo.ksoftirqd because its
  1.1185  	// not used anywhere else and we need a place to stash ivr and
  1.1186  	// there's no registers available unused by SAVE_MIN/REST
  1.1187 -	movl r29=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
  1.1188 -	st8 [r29]=r30;;
  1.1189 -	movl r28=slow_interrupt;;
  1.1190 -	mov r29=rp;;
  1.1191 -	mov rp=r28;;
  1.1192 +	movl r29=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET
  1.1193 +	;;
  1.1194 +	st8 [r29]=r30
  1.1195 +	;;
  1.1196 +	movl r28=slow_interrupt
  1.1197 +	;;
  1.1198 +	mov r29=rp
  1.1199 +	;;
  1.1200 +	mov rp=r28
  1.1201 +	;;
  1.1202  	br.cond.sptk.many fast_tick_reflect
  1.1203  	;;
  1.1204  slow_interrupt:
  1.1205 @@ -1175,16 +1245,16 @@ slow_interrupt:
  1.1206  END(interrupt)
  1.1207  
  1.1208  	.org ia64_ivt+0x3400
  1.1209 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1210 +//////////////////////////////////////////////////////////////////////////
  1.1211  // 0x3400 Entry 13 (size 64 bundles) Reserved
  1.1212  	DBG_FAULT(13)
  1.1213  	FAULT(13)
  1.1214  
  1.1215  #ifdef XEN
  1.1216 -	// There is no particular reason for this code to be here, other than that
  1.1217 -	// there happens to be space here that would go unused otherwise.  If this
  1.1218 -	// fault ever gets "unreserved", simply moved the following code to a more
  1.1219 -	// suitable spot...
  1.1220 +	// There is no particular reason for this code to be here, other
  1.1221 +	// than that there happens to be space here that would go unused 
  1.1222 +	// otherwise.  If this fault ever gets "unreserved", simply move
  1.1223 +	// the following code to a more suitable spot...
  1.1224  
  1.1225  GLOBAL_ENTRY(dispatch_break_fault)
  1.1226  	SAVE_MIN_WITH_COVER
  1.1227 @@ -1198,32 +1268,32 @@ dispatch_break_fault_post_save:
  1.1228  
  1.1229  	ssm psr.ic | PSR_DEFAULT_BITS
  1.1230  	;;
  1.1231 -	srlz.i					// guarantee that interruption collection is on
  1.1232 +	srlz.i			// guarantee that interruption collection is on
  1.1233  	;;
  1.1234 -(p15)	ssm psr.i				// restore psr.i
  1.1235 -	adds r3=8,r2				// set up second base pointer
  1.1236 +(p15)	ssm psr.i		// restore psr.i
  1.1237 +	adds r3=8,r2		// set up second base pointer
  1.1238  	;;
  1.1239  	SAVE_REST
  1.1240  	movl r14=ia64_leave_kernel
  1.1241  	;;
  1.1242  	mov rp=r14
  1.1243 -//	br.sptk.many ia64_prepare_handle_break
  1.1244 -    br.call.sptk.many b6=ia64_handle_break
  1.1245 +//	br.sptk.many ia64_prepare_handle_break	// TODO: why commented out?
  1.1246 +    	br.call.sptk.many b6=ia64_handle_break
  1.1247  END(dispatch_break_fault)
  1.1248  #endif
  1.1249  
  1.1250  	.org ia64_ivt+0x3800
  1.1251 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1252 +//////////////////////////////////////////////////////////////////////////
  1.1253  // 0x3800 Entry 14 (size 64 bundles) Reserved
  1.1254  	DBG_FAULT(14)
  1.1255  	FAULT(14)
  1.1256  
  1.1257  #ifndef XEN
  1.1258  	/*
  1.1259 -	 * There is no particular reason for this code to be here, other than that
  1.1260 -	 * there happens to be space here that would go unused otherwise.  If this
  1.1261 -	 * fault ever gets "unreserved", simply moved the following code to a more
  1.1262 -	 * suitable spot...
  1.1263 +	 * There is no particular reason for this code to be here, other 
  1.1264 +	 * than that there happens to be space here that would go unused 
  1.1265 +	 * otherwise.  If this fault ever gets "unreserved", simply move
  1.1266 +	 * the following code to a more suitable spot...
  1.1267  	 *
  1.1268  	 * ia64_syscall_setup() is a separate subroutine so that it can
  1.1269  	 *	allocate stacked registers so it can safely demine any
  1.1270 @@ -1271,11 +1341,11 @@ GLOBAL_ENTRY(ia64_syscall_setup)
  1.1271  # error This code assumes that b6 is the first field in pt_regs.
  1.1272  #endif
  1.1273  #endif
  1.1274 -	st8 [r1]=r19				// save b6
  1.1275 -	add r16=PT(CR_IPSR),r1			// initialize first base pointer
  1.1276 -	add r17=PT(R11),r1			// initialize second base pointer
  1.1277 +	st8 [r1]=r19			// save b6
  1.1278 +	add r16=PT(CR_IPSR),r1		// initialize first base pointer
  1.1279 +	add r17=PT(R11),r1		// initialize second base pointer
  1.1280  	;;
  1.1281 -	alloc r19=ar.pfs,8,0,0,0		// ensure in0-in7 are writable
  1.1282 +	alloc r19=ar.pfs,8,0,0,0	// ensure in0-in7 are writable
  1.1283  	st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR)	// save cr.ipsr
  1.1284  	tnat.nz p8,p0=in0
  1.1285  
  1.1286 @@ -1312,18 +1382,20 @@ GLOBAL_ENTRY(ia64_syscall_setup)
  1.1287  	tnat.nz p11,p0=in3
  1.1288  	;;
  1.1289  (p10)	mov in2=-1
  1.1290 -	tnat.nz p12,p0=in4				// [I0]
  1.1291 +	tnat.nz p12,p0=in4			// [I0]
  1.1292  (p11)	mov in3=-1
  1.1293  	;;
  1.1294  (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT)	// save ar.rnat
  1.1295  (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE)	// save ar.bspstore
  1.1296 -	shl r18=r18,16				// compute ar.rsc to be used for "loadrs"
  1.1297 +	shl r18=r18,16				// compute ar.rsc to be used
  1.1298 +						//   for "loadrs"
  1.1299  	;;
  1.1300  	st8 [r16]=r31,PT(LOADRS)-PT(PR)		// save predicates
  1.1301  	st8 [r17]=r28,PT(R1)-PT(B0)		// save b0
  1.1302 -	tnat.nz p13,p0=in5				// [I0]
  1.1303 +	tnat.nz p13,p0=in5			// [I0]
  1.1304  	;;
  1.1305 -	st8 [r16]=r18,PT(R12)-PT(LOADRS)	// save ar.rsc value for "loadrs"
  1.1306 +	st8 [r16]=r18,PT(R12)-PT(LOADRS)	// save ar.rsc value for
  1.1307 +						//   "loadrs"
  1.1308  	st8.spill [r17]=r20,PT(R13)-PT(R1)	// save original r1
  1.1309  (p12)	mov in4=-1
  1.1310  	;;
  1.1311 @@ -1336,32 +1408,34 @@ GLOBAL_ENTRY(ia64_syscall_setup)
  1.1312  	tnat.nz p14,p0=in6
  1.1313  	cmp.lt p10,p9=r11,r8	// frame size can't be more than local+8
  1.1314  	;;
  1.1315 -	stf8 [r16]=f1		// ensure pt_regs.r8 != 0 (see handle_syscall_error)
  1.1316 +	stf8 [r16]=f1		// ensure pt_regs.r8 != 0 
  1.1317 +				//   (see handle_syscall_error)
  1.1318  (p9)	tnat.nz p10,p0=r15
  1.1319 -	adds r12=-16,r1		// switch to kernel memory stack (with 16 bytes of scratch)
  1.1320 +	adds r12=-16,r1		// switch to kernel memory stack (with 16 
  1.1321 +				//   bytes of scratch)
  1.1322  
  1.1323 -	st8.spill [r17]=r15			// save r15
  1.1324 +	st8.spill [r17]=r15	// save r15
  1.1325  	tnat.nz p8,p0=in7
  1.1326  	nop.i 0
  1.1327  
  1.1328 -	mov r13=r2				// establish `current'
  1.1329 -	movl r1=__gp				// establish kernel global pointer
  1.1330 +	mov r13=r2		// establish `current'
  1.1331 +	movl r1=__gp		// establish kernel global pointer
  1.1332  	;;
  1.1333  (p14)	mov in6=-1
  1.1334  (p8)	mov in7=-1
  1.1335  	nop.i 0
  1.1336  
  1.1337 -	cmp.eq pSys,pNonSys=r0,r0		// set pSys=1, pNonSys=0
  1.1338 +	cmp.eq pSys,pNonSys=r0,r0	// set pSys=1, pNonSys=0
  1.1339  	movl r17=FPSR_DEFAULT
  1.1340  	;;
  1.1341 -	mov.m ar.fpsr=r17			// set ar.fpsr to kernel default value
  1.1342 +	mov.m ar.fpsr=r17		// set ar.fpsr to kernel default value
  1.1343  (p10)	mov r8=-EINVAL
  1.1344  	br.ret.sptk.many b7
  1.1345  END(ia64_syscall_setup)
  1.1346  #endif /* XEN */
  1.1347  	
  1.1348  	.org ia64_ivt+0x3c00
  1.1349 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1350 +//////////////////////////////////////////////////////////////////////////
  1.1351  // 0x3c00 Entry 15 (size 64 bundles) Reserved
  1.1352  	DBG_FAULT(15)
  1.1353  	FAULT(15)
  1.1354 @@ -1370,11 +1444,12 @@ END(ia64_syscall_setup)
  1.1355  	/*
  1.1356  	 * Squatting in this space ...
  1.1357  	 *
  1.1358 -	 * This special case dispatcher for illegal operation faults allows preserved
  1.1359 -	 * registers to be modified through a callback function (asm only) that is handed
  1.1360 -	 * back from the fault handler in r8. Up to three arguments can be passed to the
  1.1361 -	 * callback function by returning an aggregate with the callback as its first
  1.1362 -	 * element, followed by the arguments.
  1.1363 +	 * This special case dispatcher for illegal operation faults 
  1.1364 +	 * allows preserved registers to be modified through a callback
  1.1365 +	 * function (asm only) that is handed back from the fault handler
  1.1366 +	 * in r8.  Up to three arguments can be passed to the callback
  1.1367 +	 * function by returning an aggregate with the callback as its 
  1.1368 +	 * first element, followed by the arguments.
  1.1369  	 */
  1.1370  ENTRY(dispatch_illegal_op_fault)
  1.1371  	SAVE_MIN_WITH_COVER
  1.1372 @@ -1408,21 +1483,22 @@ END(dispatch_illegal_op_fault)
  1.1373  #endif
  1.1374  
  1.1375  	.org ia64_ivt+0x4000
  1.1376 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1377 +//////////////////////////////////////////////////////////////////////////
  1.1378  // 0x4000 Entry 16 (size 64 bundles) Reserved
  1.1379  	DBG_FAULT(16)
  1.1380  	FAULT(16)
  1.1381  
  1.1382  #ifdef XEN
  1.1383 -	// There is no particular reason for this code to be here, other than that
  1.1384 -	// there happens to be space here that would go unused otherwise.  If this
  1.1385 -	// fault ever gets "unreserved", simply moved the following code to a more
  1.1386 -	// suitable spot...
  1.1387 +	// There is no particular reason for this code to be here, other
  1.1388 +	// than that there happens to be space here that would go unused 
  1.1389 +	// otherwise.  If this fault ever gets "unreserved", simply move
  1.1390 +	// the following code to a more suitable spot...
  1.1391  
  1.1392  ENTRY(dispatch_privop_fault)
  1.1393  	SAVE_MIN_WITH_COVER
  1.1394  	;;
  1.1395 -	alloc r14=ar.pfs,0,0,4,0		// now it's safe (must be first in insn group!)
  1.1396 +	alloc r14=ar.pfs,0,0,4,0	// now it's safe (must be first in
  1.1397 +					//   insn group!)
  1.1398  	mov out0=cr.ifa
  1.1399  	adds out1=16,sp
  1.1400  	mov out2=cr.isr		// FIXME: pity to make this slow access twice
  1.1401 @@ -1430,23 +1506,24 @@ ENTRY(dispatch_privop_fault)
  1.1402  
  1.1403  	ssm psr.ic | PSR_DEFAULT_BITS
  1.1404  	;;
  1.1405 -	srlz.i					// guarantee that interruption collection is on
  1.1406 +	srlz.i				// guarantee that interruption 
  1.1407 +					//   collection is on
  1.1408  	;;
  1.1409 -(p15)	ssm psr.i				// restore psr.i
  1.1410 -	adds r3=8,r2				// set up second base pointer
  1.1411 +(p15)	ssm psr.i			// restore psr.i
  1.1412 +	adds r3=8,r2			// set up second base pointer
  1.1413  	;;
  1.1414  	SAVE_REST
  1.1415  	movl r14=ia64_leave_kernel
  1.1416  	;;
  1.1417  	mov rp=r14
  1.1418 -//	br.sptk.many ia64_prepare_handle_privop
  1.1419 -     br.call.sptk.many b6=ia64_handle_privop
  1.1420 +//	br.sptk.many ia64_prepare_handle_privop  // TODO: why commented out?
  1.1421 +     	br.call.sptk.many b6=ia64_handle_privop
  1.1422  END(dispatch_privop_fault)
  1.1423  #endif
  1.1424  
  1.1425  
  1.1426  	.org ia64_ivt+0x4400
  1.1427 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1428 +//////////////////////////////////////////////////////////////////////////
  1.1429  // 0x4400 Entry 17 (size 64 bundles) Reserved
  1.1430  	DBG_FAULT(17)
  1.1431  	FAULT(17)
  1.1432 @@ -1455,77 +1532,80 @@ END(dispatch_privop_fault)
  1.1433  ENTRY(non_syscall)
  1.1434  	SAVE_MIN_WITH_COVER
  1.1435  
  1.1436 -	// There is no particular reason for this code to be here, other than that
  1.1437 -	// there happens to be space here that would go unused otherwise.  If this
  1.1438 -	// fault ever gets "unreserved", simply moved the following code to a more
  1.1439 -	// suitable spot...
  1.1440 +	// There is no particular reason for this code to be here, other
  1.1441 +	// than that there happens to be space here that would go unused 
  1.1442 +	// otherwise.  If this fault ever gets "unreserved", simply move
  1.1443 +	// the following code to a more suitable spot...
  1.1444  
  1.1445  	alloc r14=ar.pfs,0,0,2,0
  1.1446  	mov out0=cr.iim
  1.1447  	add out1=16,sp
  1.1448 -	adds r3=8,r2			// set up second base pointer for SAVE_REST
  1.1449 +	adds r3=8,r2		// set up second base pointer for SAVE_REST
  1.1450  
  1.1451  	ssm psr.ic | PSR_DEFAULT_BITS
  1.1452  	;;
  1.1453 -	srlz.i				// guarantee that interruption collection is on
  1.1454 +	srlz.i			// guarantee that interruption collection is on
  1.1455  	;;
  1.1456 -(p15)	ssm psr.i			// restore psr.i
  1.1457 +(p15)	ssm psr.i		// restore psr.i
  1.1458  	movl r15=ia64_leave_kernel
  1.1459  	;;
  1.1460  	SAVE_REST
  1.1461  	mov rp=r15
  1.1462  	;;
  1.1463 -	br.call.sptk.many b6=ia64_bad_break	// avoid WAW on CFM and ignore return addr
  1.1464 +	br.call.sptk.many b6=ia64_bad_break	// avoid WAW on CFM and 
  1.1465 +						//   ignore return addr
  1.1466  END(non_syscall)
  1.1467  #endif
  1.1468  
  1.1469  	.org ia64_ivt+0x4800
  1.1470 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1471 +//////////////////////////////////////////////////////////////////////////
  1.1472  // 0x4800 Entry 18 (size 64 bundles) Reserved
  1.1473  	DBG_FAULT(18)
  1.1474  	FAULT(18)
  1.1475  
  1.1476  #ifndef XEN
  1.1477  	/*
  1.1478 -	 * There is no particular reason for this code to be here, other than that
  1.1479 -	 * there happens to be space here that would go unused otherwise.  If this
  1.1480 -	 * fault ever gets "unreserved", simply moved the following code to a more
  1.1481 -	 * suitable spot...
  1.1482 +	 * There is no particular reason for this code to be here, other
  1.1483 +	 * than that there happens to be space here that would go unused 
  1.1484 +	 * otherwise.  If this fault ever gets "unreserved", simply move
  1.1485 +	 * the following code to a more suitable spot...
  1.1486  	 */
  1.1487  ENTRY(dispatch_unaligned_handler)
  1.1488  	SAVE_MIN_WITH_COVER
  1.1489  	;;
  1.1490 -	alloc r14=ar.pfs,0,0,2,0		// now it's safe (must be first in insn group!)
  1.1491 +	alloc r14=ar.pfs,0,0,2,0	// now it's safe (must be first in
  1.1492 +					//   insn group!)
  1.1493  	mov out0=cr.ifa
  1.1494  	adds out1=16,sp
  1.1495  
  1.1496  	ssm psr.ic | PSR_DEFAULT_BITS
  1.1497  	;;
  1.1498 -	srlz.i					// guarantee that interruption collection is on
  1.1499 +	srlz.i				// guarantee that interruption 
  1.1500 +					//   collection is on
  1.1501  	;;
  1.1502 -(p15)	ssm psr.i				// restore psr.i
  1.1503 -	adds r3=8,r2				// set up second base pointer
  1.1504 +(p15)	ssm psr.i			// restore psr.i
  1.1505 +	adds r3=8,r2			// set up second base pointer
  1.1506  	;;
  1.1507  	SAVE_REST
  1.1508  	movl r14=ia64_leave_kernel
  1.1509  	;;
  1.1510  	mov rp=r14
  1.1511 -//	br.sptk.many ia64_prepare_handle_unaligned
  1.1512 -    br.call.sptk.many b6=ia64_handle_unaligned
  1.1513 +//	br.sptk.many ia64_prepare_handle_unaligned // TODO: why commented out?
  1.1514 +    	br.call.sptk.many b6=ia64_handle_unaligned
  1.1515  END(dispatch_unaligned_handler)
  1.1516  #endif
  1.1517  
  1.1518  	.org ia64_ivt+0x4c00
  1.1519 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1520 +//////////////////////////////////////////////////////////////////////////
  1.1521  // 0x4c00 Entry 19 (size 64 bundles) Reserved
  1.1522  	DBG_FAULT(19)
  1.1523  	FAULT(19)
  1.1524  
  1.1525  	/*
  1.1526 -	 * There is no particular reason for this code to be here, other than that
  1.1527 -	 * there happens to be space here that would go unused otherwise.  If this
  1.1528 -	 * fault ever gets "unreserved", simply moved the following code to a more
  1.1529 -	 * suitable spot...
  1.1530 +	 * There is no particular reason for this code to be here, other 
  1.1531 +	 * than that there happens to be space here that would go unused 
  1.1532 +	 * otherwise.  If this fault ever gets "unreserved", simply move
  1.1533 +	 * the following code to a more suitable spot...
  1.1534  	 */
  1.1535  
  1.1536  GLOBAL_ENTRY(dispatch_to_fault_handler)
  1.1537 @@ -1545,10 +1625,12 @@ GLOBAL_ENTRY(dispatch_to_fault_handler)
  1.1538  	;;
  1.1539  	ssm psr.ic | PSR_DEFAULT_BITS
  1.1540  	;;
  1.1541 -	srlz.i					// guarantee that interruption collection is on
  1.1542 +	srlz.i				// guarantee that interruption 
  1.1543 +					//   collection is on
  1.1544  	;;
  1.1545 -(p15)	ssm psr.i				// restore psr.i
  1.1546 -	adds r3=8,r2				// set up second base pointer for SAVE_REST
  1.1547 +(p15)	ssm psr.i			// restore psr.i
  1.1548 +	adds r3=8,r2			// set up second base pointer for
  1.1549 +					//   SAVE_REST
  1.1550  	;;
  1.1551  	SAVE_REST
  1.1552  	movl r14=ia64_leave_kernel
  1.1553 @@ -1562,7 +1644,7 @@ END(dispatch_to_fault_handler)
  1.1554  //
  1.1555  
  1.1556  	.org ia64_ivt+0x5000
  1.1557 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1558 +//////////////////////////////////////////////////////////////////////////
  1.1559  // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
  1.1560  ENTRY(page_not_present)
  1.1561  	DBG_FAULT(20)
  1.1562 @@ -1572,8 +1654,9 @@ ENTRY(page_not_present)
  1.1563  	mov r16=cr.ifa
  1.1564  	rsm psr.dt
  1.1565  	/*
  1.1566 -	 * The Linux page fault handler doesn't expect non-present pages to be in
  1.1567 -	 * the TLB.  Flush the existing entry now, so we meet that expectation.
  1.1568 +	 * The Linux page fault handler doesn't expect non-present pages
  1.1569 +	 * to be in the TLB.  Flush the existing entry now, so we meet 
  1.1570 +	 * that expectation.
  1.1571  	 */
  1.1572  	mov r17=PAGE_SHIFT<<2
  1.1573  	;;
  1.1574 @@ -1586,7 +1669,7 @@ ENTRY(page_not_present)
  1.1575  END(page_not_present)
  1.1576  
  1.1577  	.org ia64_ivt+0x5100
  1.1578 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1579 +//////////////////////////////////////////////////////////////////////////
  1.1580  // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
  1.1581  ENTRY(key_permission)
  1.1582  	DBG_FAULT(21)
  1.1583 @@ -1603,7 +1686,7 @@ ENTRY(key_permission)
  1.1584  END(key_permission)
  1.1585  
  1.1586  	.org ia64_ivt+0x5200
  1.1587 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1588 +//////////////////////////////////////////////////////////////////////////
  1.1589  // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
  1.1590  ENTRY(iaccess_rights)
  1.1591  	DBG_FAULT(22)
  1.1592 @@ -1620,17 +1703,19 @@ ENTRY(iaccess_rights)
  1.1593  END(iaccess_rights)
  1.1594  
  1.1595  	.org ia64_ivt+0x5300
  1.1596 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1597 +//////////////////////////////////////////////////////////////////////////
  1.1598  // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
  1.1599  ENTRY(daccess_rights)
  1.1600  	DBG_FAULT(23)
  1.1601  #ifdef XEN
  1.1602 -	mov r31=pr;
  1.1603 +	mov r31=pr
  1.1604 +	;;
  1.1605  	mov r16=cr.isr
  1.1606  	mov r17=cr.ifa
  1.1607  	mov r19=23
  1.1608  	movl r20=0x5300
  1.1609 -	br.sptk.many fast_access_reflect;;
  1.1610 +	br.sptk.many fast_access_reflect
  1.1611 +	;;
  1.1612  #else
  1.1613  	mov r16=cr.ifa
  1.1614  	rsm psr.dt
  1.1615 @@ -1642,7 +1727,7 @@ ENTRY(daccess_rights)
  1.1616  END(daccess_rights)
  1.1617  
  1.1618  	.org ia64_ivt+0x5400
  1.1619 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1620 +//////////////////////////////////////////////////////////////////////////
  1.1621  // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
  1.1622  ENTRY(general_exception)
  1.1623  	DBG_FAULT(24)
  1.1624 @@ -1662,12 +1747,12 @@ ENTRY(general_exception)
  1.1625  END(general_exception)
  1.1626  
  1.1627  	.org ia64_ivt+0x5500
  1.1628 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1629 +//////////////////////////////////////////////////////////////////////////
  1.1630  // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
  1.1631  ENTRY(disabled_fp_reg)
  1.1632  	DBG_FAULT(25)
  1.1633  #ifdef XEN
  1.1634 -#if 0
  1.1635 +#if 0				// TODO: can this be removed?
  1.1636  	mov r20=pr
  1.1637  	movl r16=0x2000000000000000
  1.1638  	movl r17=0x2000000000176b60
  1.1639 @@ -1686,7 +1771,7 @@ ENTRY(disabled_fp_reg)
  1.1640  	;;
  1.1641  #endif
  1.1642  	FAULT_OR_REFLECT(25)
  1.1643 -//floating_panic:
  1.1644 +//floating_panic:		// TODO: can this be removed?
  1.1645  //	br.sptk.many floating_panic
  1.1646  	;;
  1.1647  #endif
  1.1648 @@ -1699,7 +1784,7 @@ ENTRY(disabled_fp_reg)
  1.1649  END(disabled_fp_reg)
  1.1650  
  1.1651  	.org ia64_ivt+0x5600
  1.1652 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1653 +//////////////////////////////////////////////////////////////////////////
  1.1654  // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
  1.1655  ENTRY(nat_consumption)
  1.1656  	DBG_FAULT(26)
  1.1657 @@ -1711,7 +1796,7 @@ ENTRY(nat_consumption)
  1.1658  END(nat_consumption)
  1.1659  
  1.1660  	.org ia64_ivt+0x5700
  1.1661 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1662 +//////////////////////////////////////////////////////////////////////////
  1.1663  // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
  1.1664  ENTRY(speculation_vector)
  1.1665  	DBG_FAULT(27)
  1.1666 @@ -1720,12 +1805,13 @@ ENTRY(speculation_vector)
  1.1667  	FAULT_OR_REFLECT(27)
  1.1668  #else
  1.1669  	/*
  1.1670 -	 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
  1.1671 -	 * this part of the architecture is not implemented in hardware on some CPUs, such
  1.1672 -	 * as Itanium.  Thus, in general we need to emulate the behavior.  IIM contains
  1.1673 -	 * the relative target (not yet sign extended).  So after sign extending it we
  1.1674 -	 * simply add it to IIP.  We also need to reset the EI field of the IPSR to zero,
  1.1675 -	 * i.e., the slot to restart into.
  1.1676 +	 * A [f]chk.[as] instruction needs to take the branch to the
  1.1677 +	 * recovery code but this part of the architecture is not 
  1.1678 +	 * implemented in hardware on some CPUs, such as Itanium.  Thus,
  1.1679 +	 * in general we need to emulate the behavior.  IIM contains the
  1.1680 +	 * relative target (not yet sign extended).  So after sign extending 
  1.1681 +	 * it we simply add it to IIP.  We also need to reset the EI field
  1.1682 +	 * of the IPSR to zero, i.e., the slot to restart into.
  1.1683  	 *
  1.1684  	 * cr.imm contains zero_ext(imm21)
  1.1685  	 */
  1.1686 @@ -1753,13 +1839,13 @@ ENTRY(speculation_vector)
  1.1687  END(speculation_vector)
  1.1688  
  1.1689  	.org ia64_ivt+0x5800
  1.1690 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1691 +//////////////////////////////////////////////////////////////////////////
  1.1692  // 0x5800 Entry 28 (size 16 bundles) Reserved
  1.1693  	DBG_FAULT(28)
  1.1694  	FAULT(28)
  1.1695  
  1.1696  	.org ia64_ivt+0x5900
  1.1697 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1698 +//////////////////////////////////////////////////////////////////////////
  1.1699  // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
  1.1700  ENTRY(debug_vector)
  1.1701  	DBG_FAULT(29)
  1.1702 @@ -1771,7 +1857,7 @@ ENTRY(debug_vector)
  1.1703  END(debug_vector)
  1.1704  
  1.1705  	.org ia64_ivt+0x5a00
  1.1706 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1707 +//////////////////////////////////////////////////////////////////////////
  1.1708  // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
  1.1709  ENTRY(unaligned_access)
  1.1710  	DBG_FAULT(30)
  1.1711 @@ -1786,7 +1872,7 @@ ENTRY(unaligned_access)
  1.1712  END(unaligned_access)
  1.1713  
  1.1714  	.org ia64_ivt+0x5b00
  1.1715 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1716 +//////////////////////////////////////////////////////////////////////////
  1.1717  // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
  1.1718  ENTRY(unsupported_data_reference)
  1.1719  	DBG_FAULT(31)
  1.1720 @@ -1798,7 +1884,7 @@ ENTRY(unsupported_data_reference)
  1.1721  END(unsupported_data_reference)
  1.1722  
  1.1723  	.org ia64_ivt+0x5c00
  1.1724 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1725 +//////////////////////////////////////////////////////////////////////////
  1.1726  // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
  1.1727  ENTRY(floating_point_fault)
  1.1728  	DBG_FAULT(32)
  1.1729 @@ -1810,7 +1896,7 @@ ENTRY(floating_point_fault)
  1.1730  END(floating_point_fault)
  1.1731  
  1.1732  	.org ia64_ivt+0x5d00
  1.1733 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1734 +//////////////////////////////////////////////////////////////////////////
  1.1735  // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
  1.1736  ENTRY(floating_point_trap)
  1.1737  	DBG_FAULT(33)
  1.1738 @@ -1822,7 +1908,7 @@ ENTRY(floating_point_trap)
  1.1739  END(floating_point_trap)
  1.1740  
  1.1741  	.org ia64_ivt+0x5e00
  1.1742 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1743 +//////////////////////////////////////////////////////////////////////////
  1.1744  // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
  1.1745  ENTRY(lower_privilege_trap)
  1.1746  	DBG_FAULT(34)
  1.1747 @@ -1834,7 +1920,7 @@ ENTRY(lower_privilege_trap)
  1.1748  END(lower_privilege_trap)
  1.1749  
  1.1750  	.org ia64_ivt+0x5f00
  1.1751 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1752 +//////////////////////////////////////////////////////////////////////////
  1.1753  // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
  1.1754  ENTRY(taken_branch_trap)
  1.1755  	DBG_FAULT(35)
  1.1756 @@ -1846,7 +1932,7 @@ ENTRY(taken_branch_trap)
  1.1757  END(taken_branch_trap)
  1.1758  
  1.1759  	.org ia64_ivt+0x6000
  1.1760 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1761 +//////////////////////////////////////////////////////////////////////////
  1.1762  // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
  1.1763  ENTRY(single_step_trap)
  1.1764  	DBG_FAULT(36)
  1.1765 @@ -1858,56 +1944,58 @@ ENTRY(single_step_trap)
  1.1766  END(single_step_trap)
  1.1767  
  1.1768  	.org ia64_ivt+0x6100
  1.1769 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1770 +//////////////////////////////////////////////////////////////////////////
  1.1771  // 0x6100 Entry 37 (size 16 bundles) Reserved
  1.1772  	DBG_FAULT(37)
  1.1773  	FAULT(37)
  1.1774  
  1.1775  	.org ia64_ivt+0x6200
  1.1776 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1777 +//////////////////////////////////////////////////////////////////////////
  1.1778  // 0x6200 Entry 38 (size 16 bundles) Reserved
  1.1779  	DBG_FAULT(38)
  1.1780  	FAULT(38)
  1.1781  
  1.1782  	.org ia64_ivt+0x6300
  1.1783 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1784 +//////////////////////////////////////////////////////////////////////////
  1.1785  // 0x6300 Entry 39 (size 16 bundles) Reserved
  1.1786  	DBG_FAULT(39)
  1.1787  	FAULT(39)
  1.1788  
  1.1789  	.org ia64_ivt+0x6400
  1.1790 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1791 +//////////////////////////////////////////////////////////////////////////
  1.1792  // 0x6400 Entry 40 (size 16 bundles) Reserved
  1.1793  	DBG_FAULT(40)
  1.1794  	FAULT(40)
  1.1795  
  1.1796  	.org ia64_ivt+0x6500
  1.1797 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1798 +//////////////////////////////////////////////////////////////////////////
  1.1799  // 0x6500 Entry 41 (size 16 bundles) Reserved
  1.1800  	DBG_FAULT(41)
  1.1801  	FAULT(41)
  1.1802  
  1.1803  	.org ia64_ivt+0x6600
  1.1804 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1805 +//////////////////////////////////////////////////////////////////////////
  1.1806  // 0x6600 Entry 42 (size 16 bundles) Reserved
  1.1807  	DBG_FAULT(42)
  1.1808  	FAULT(42)
  1.1809  
  1.1810  	.org ia64_ivt+0x6700
  1.1811 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1812 +//////////////////////////////////////////////////////////////////////////
  1.1813  // 0x6700 Entry 43 (size 16 bundles) Reserved
  1.1814  	DBG_FAULT(43)
  1.1815  	FAULT(43)
  1.1816  
  1.1817  	.org ia64_ivt+0x6800
  1.1818 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1819 +//////////////////////////////////////////////////////////////////////////
  1.1820  // 0x6800 Entry 44 (size 16 bundles) Reserved
  1.1821  	DBG_FAULT(44)
  1.1822  	FAULT(44)
  1.1823  
  1.1824  	.org ia64_ivt+0x6900
  1.1825 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1826 -// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
  1.1827 +//////////////////////////////////////////////////////////////////////////
  1.1828 +// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,
  1.1829 +//						       44,58,60,61,62,72,
  1.1830 +//						       73,75,76,77)
  1.1831  ENTRY(ia32_exception)
  1.1832  	DBG_FAULT(45)
  1.1833  #ifdef XEN
  1.1834 @@ -1918,7 +2006,7 @@ ENTRY(ia32_exception)
  1.1835  END(ia32_exception)
  1.1836  
  1.1837  	.org ia64_ivt+0x6a00
  1.1838 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1839 +//////////////////////////////////////////////////////////////////////////
  1.1840  // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept  (30,31,59,70,71)
  1.1841  ENTRY(ia32_intercept)
  1.1842  	DBG_FAULT(46)
  1.1843 @@ -1952,7 +2040,7 @@ 1:
  1.1844  END(ia32_intercept)
  1.1845  
  1.1846  	.org ia64_ivt+0x6b00
  1.1847 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1848 +//////////////////////////////////////////////////////////////////////////
  1.1849  // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt  (74)
  1.1850  ENTRY(ia32_interrupt)
  1.1851  	DBG_FAULT(47)
  1.1852 @@ -1969,121 +2057,121 @@ ENTRY(ia32_interrupt)
  1.1853  END(ia32_interrupt)
  1.1854  
  1.1855  	.org ia64_ivt+0x6c00
  1.1856 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1857 +//////////////////////////////////////////////////////////////////////////
  1.1858  // 0x6c00 Entry 48 (size 16 bundles) Reserved
  1.1859  	DBG_FAULT(48)
  1.1860  	FAULT(48)
  1.1861  
  1.1862  	.org ia64_ivt+0x6d00
  1.1863 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1864 +//////////////////////////////////////////////////////////////////////////
  1.1865  // 0x6d00 Entry 49 (size 16 bundles) Reserved
  1.1866  	DBG_FAULT(49)
  1.1867  	FAULT(49)
  1.1868  
  1.1869  	.org ia64_ivt+0x6e00
  1.1870 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1871 +//////////////////////////////////////////////////////////////////////////
  1.1872  // 0x6e00 Entry 50 (size 16 bundles) Reserved
  1.1873  	DBG_FAULT(50)
  1.1874  	FAULT(50)
  1.1875  
  1.1876  	.org ia64_ivt+0x6f00
  1.1877 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1878 +//////////////////////////////////////////////////////////////////////////
  1.1879  // 0x6f00 Entry 51 (size 16 bundles) Reserved
  1.1880  	DBG_FAULT(51)
  1.1881  	FAULT(51)
  1.1882  
  1.1883  	.org ia64_ivt+0x7000
  1.1884 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1885 +//////////////////////////////////////////////////////////////////////////
  1.1886  // 0x7000 Entry 52 (size 16 bundles) Reserved
  1.1887  	DBG_FAULT(52)
  1.1888  	FAULT(52)
  1.1889  
  1.1890  	.org ia64_ivt+0x7100
  1.1891 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1892 +//////////////////////////////////////////////////////////////////////////
  1.1893  // 0x7100 Entry 53 (size 16 bundles) Reserved
  1.1894  	DBG_FAULT(53)
  1.1895  	FAULT(53)
  1.1896  
  1.1897  	.org ia64_ivt+0x7200
  1.1898 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1899 +//////////////////////////////////////////////////////////////////////////
  1.1900  // 0x7200 Entry 54 (size 16 bundles) Reserved
  1.1901  	DBG_FAULT(54)
  1.1902  	FAULT(54)
  1.1903  
  1.1904  	.org ia64_ivt+0x7300
  1.1905 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1906 +//////////////////////////////////////////////////////////////////////////
  1.1907  // 0x7300 Entry 55 (size 16 bundles) Reserved
  1.1908  	DBG_FAULT(55)
  1.1909  	FAULT(55)
  1.1910  
  1.1911  	.org ia64_ivt+0x7400
  1.1912 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1913 +//////////////////////////////////////////////////////////////////////////
  1.1914  // 0x7400 Entry 56 (size 16 bundles) Reserved
  1.1915  	DBG_FAULT(56)
  1.1916  	FAULT(56)
  1.1917  
  1.1918  	.org ia64_ivt+0x7500
  1.1919 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1920 +//////////////////////////////////////////////////////////////////////////
  1.1921  // 0x7500 Entry 57 (size 16 bundles) Reserved
  1.1922  	DBG_FAULT(57)
  1.1923  	FAULT(57)
  1.1924  
  1.1925  	.org ia64_ivt+0x7600
  1.1926 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1927 +//////////////////////////////////////////////////////////////////////////
  1.1928  // 0x7600 Entry 58 (size 16 bundles) Reserved
  1.1929  	DBG_FAULT(58)
  1.1930  	FAULT(58)
  1.1931  
  1.1932  	.org ia64_ivt+0x7700
  1.1933 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1934 +//////////////////////////////////////////////////////////////////////////
  1.1935  // 0x7700 Entry 59 (size 16 bundles) Reserved
  1.1936  	DBG_FAULT(59)
  1.1937  	FAULT(59)
  1.1938  
  1.1939  	.org ia64_ivt+0x7800
  1.1940 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1941 +//////////////////////////////////////////////////////////////////////////
  1.1942  // 0x7800 Entry 60 (size 16 bundles) Reserved
  1.1943  	DBG_FAULT(60)
  1.1944  	FAULT(60)
  1.1945  
  1.1946  	.org ia64_ivt+0x7900
  1.1947 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1948 +//////////////////////////////////////////////////////////////////////////
  1.1949  // 0x7900 Entry 61 (size 16 bundles) Reserved
  1.1950  	DBG_FAULT(61)
  1.1951  	FAULT(61)
  1.1952  
  1.1953  	.org ia64_ivt+0x7a00
  1.1954 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1955 +//////////////////////////////////////////////////////////////////////////
  1.1956  // 0x7a00 Entry 62 (size 16 bundles) Reserved
  1.1957  	DBG_FAULT(62)
  1.1958  	FAULT(62)
  1.1959  
  1.1960  	.org ia64_ivt+0x7b00
  1.1961 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1962 +//////////////////////////////////////////////////////////////////////////
  1.1963  // 0x7b00 Entry 63 (size 16 bundles) Reserved
  1.1964  	DBG_FAULT(63)
  1.1965  	FAULT(63)
  1.1966  
  1.1967  	.org ia64_ivt+0x7c00
  1.1968 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1969 +//////////////////////////////////////////////////////////////////////////
  1.1970  // 0x7c00 Entry 64 (size 16 bundles) Reserved
  1.1971  	DBG_FAULT(64)
  1.1972  	FAULT(64)
  1.1973  
  1.1974  	.org ia64_ivt+0x7d00
  1.1975 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1976 +//////////////////////////////////////////////////////////////////////////
  1.1977  // 0x7d00 Entry 65 (size 16 bundles) Reserved
  1.1978  	DBG_FAULT(65)
  1.1979  	FAULT(65)
  1.1980  
  1.1981  	.org ia64_ivt+0x7e00
  1.1982 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1983 +//////////////////////////////////////////////////////////////////////////
  1.1984  // 0x7e00 Entry 66 (size 16 bundles) Reserved
  1.1985  	DBG_FAULT(66)
  1.1986  	FAULT(66)
  1.1987  
  1.1988  	.org ia64_ivt+0x7f00
  1.1989 -/////////////////////////////////////////////////////////////////////////////////////////
  1.1990 +//////////////////////////////////////////////////////////////////////////
  1.1991  // 0x7f00 Entry 67 (size 16 bundles) Reserved
  1.1992  	DBG_FAULT(67)
  1.1993  	FAULT(67)
  1.1994 @@ -2104,21 +2192,22 @@ GLOBAL_ENTRY(dispatch_reflection)
  1.1995  	adds out1=16,sp
  1.1996  	mov out2=cr.isr
  1.1997  	mov out3=cr.iim
  1.1998 -//	mov out3=cr.itir
  1.1999 +//	mov out3=cr.itir		// TODO: why commented out?
  1.2000  
  1.2001  	ssm psr.ic | PSR_DEFAULT_BITS
  1.2002  	;;
  1.2003 -	srlz.i					// guarantee that interruption collection is on
  1.2004 +	srlz.i				// guarantee that interruption 
  1.2005 +					//   collection is on
  1.2006  	;;
  1.2007 -(p15)	ssm psr.i				// restore psr.i
  1.2008 -	adds r3=8,r2				// set up second base pointer
  1.2009 +(p15)	ssm psr.i			// restore psr.i
  1.2010 +	adds r3=8,r2			// set up second base pointer
  1.2011  	;;
  1.2012  	SAVE_REST
  1.2013  	movl r14=ia64_leave_kernel
  1.2014  	;;
  1.2015  	mov rp=r14
  1.2016 -//	br.sptk.many ia64_prepare_handle_reflection
  1.2017 -    br.call.sptk.many b6=ia64_handle_reflection
  1.2018 +//	br.sptk.many ia64_prepare_handle_reflection // TODO: why commented out?
  1.2019 +    	br.call.sptk.many b6=ia64_handle_reflection
  1.2020  END(dispatch_reflection)
  1.2021  
  1.2022  #define SAVE_MIN_COVER_DONE	DO_SAVE_MIN(,mov r30=cr.ifs,)
  1.2023 @@ -2134,10 +2223,10 @@ END(dispatch_slow_hyperprivop)
  1.2024  #ifdef CONFIG_IA32_SUPPORT
  1.2025  
  1.2026  	/*
  1.2027 -	 * There is no particular reason for this code to be here, other than that
  1.2028 -	 * there happens to be space here that would go unused otherwise.  If this
  1.2029 -	 * fault ever gets "unreserved", simply moved the following code to a more
  1.2030 -	 * suitable spot...
  1.2031 +	 * There is no particular reason for this code to be here, other 
  1.2032 +	 * than that there happens to be space here that would go unused 
  1.2033 +	 * otherwise.  If this fault ever gets "unreserved", simply move
  1.2034 +	 * the following code to a more suitable spot...
  1.2035  	 */
  1.2036  
  1.2037  	// IA32 interrupt entry point
  1.2038 @@ -2148,7 +2237,7 @@ ENTRY(dispatch_to_ia32_handler)
  1.2039  	mov r14=cr.isr
  1.2040  	ssm psr.ic | PSR_DEFAULT_BITS
  1.2041  	;;
  1.2042 -	srlz.i					// guarantee that interruption collection is on
  1.2043 +	srlz.i			// guarantee that interruption collection is on
  1.2044  	;;
  1.2045  (p15)	ssm psr.i
  1.2046  	adds r3=8,r2		// Base pointer for SAVE_REST
  1.2047 @@ -2161,15 +2250,17 @@ ENTRY(dispatch_to_ia32_handler)
  1.2048  	cmp.ne p6,p0=r14,r15
  1.2049  (p6)	br.call.dpnt.many b6=non_ia32_syscall
  1.2050  
  1.2051 -	adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp	// 16 byte hole per SW conventions
  1.2052 +	adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp	// 16 byte hole per SW 
  1.2053 +						//   conventions
  1.2054  	adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
  1.2055  	;;
  1.2056  	cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
  1.2057  	ld8 r8=[r14]		// get r8
  1.2058  	;;
  1.2059 -	st8 [r15]=r8		// save original EAX in r1 (IA32 procs don't use the GP)
  1.2060 +	st8 [r15]=r8		// save original EAX in r1 (IA32 procs 
  1.2061 +				//   don't use the GP)
  1.2062  	;;
  1.2063 -	alloc r15=ar.pfs,0,0,6,0	// must first in an insn group
  1.2064 +	alloc r15=ar.pfs,0,0,6,0	// must be first in an insn group
  1.2065  	;;
  1.2066  	ld4 r8=[r14],8		// r8 == eax (syscall number)
  1.2067  	mov r15=IA32_NR_syscalls
  1.2068 @@ -2208,7 +2299,7 @@ non_ia32_syscall:
  1.2069  	alloc r15=ar.pfs,0,0,2,0
  1.2070  	mov out0=r14				// interrupt #
  1.2071  	add out1=16,sp				// pointer to pt_regs
  1.2072 -	;;			// avoid WAW on CFM
  1.2073 +	;;					// avoid WAW on CFM
  1.2074  	br.call.sptk.many rp=ia32_bad_interrupt
  1.2075  .ret1:	movl r15=ia64_leave_kernel
  1.2076  	;;